Apple SoC DT updates for 5.16. Adds pinctrl and PCIe nodes.
-----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSU7I7lUkZru3Mt15+lhN6SrnTN2AUCYXlFhAAKCRClhN6SrnTN 2LD8AQDtmREY69BH2TAwaOK4J8g3TY+4oqYcTfwrh5D1PVfq0AD+NsCQWz8zxHF7 oBkOWdbaTyPqSRg6E4LliR9VUgWFOwQ= =BAGP -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmF5VbsACgkQmmx57+YA GNmUxhAAgSWfVo2VjDLaCWFDeAVWvJfhFAPENJqcfT8/b2X0vGpXLrPIzVEEvHfe 4qd0uSyBxLvm1virI/goccjmBW33imS+hLGaecD1bzMmcdMfepL+3J8BqIZwCMD6 zrX4jQt1uB+BTScPlJz/qPB0MJcL83cTXiAu6BW/QS974xX71XjAcJsTUr7iAqQ1 RjFaMGaUvynm9n7HDAi6ODFVDu6dBcVp1pARxJ2k9hZYuVw6PfjojiFjUQkubO1Q LUiDo17RDtbu6BoGkZd4hn15XmdKXdj8AKKxS0PlFyYJRGOlE3fj49wX0rCx363P aQgzxlZcUQeSInH2TbayJSYI9ZnkMMxs3UKJ30bY/n+InA0DJIUOWvulIF+cobqW tFohTTbkPGnGc0ZVe1UwPfJGjxwbbcQjEoS9wRl3XzLuI90GQUCo+oUq1RoypMdW /EQLAMUk7ixF72AkJxo6pR0f4thJ1UDmkz3i20MqXBNP70eL/PUak8XEwlEC8fsu srRVw+reqTNpMb0dXYwvdk6djXB8oX3FKBRzn33f87da2AoIbw+lggzmhe0aCwLD zyTDuJP5dNhIXkwxq2PchYxIei1SpLywVAnFFrT9UKGPyUfcHP2mLFPFMH12ncTA FqFN3GJP2Nat4xdN5rEYICh8+KKLKZZXbjd6KN08z5mJIOeR6NQ= =CuMn -----END PGP SIGNATURE----- Merge tag 'asahi-soc-dt-5.16-v2' of https://github.com/AsahiLinux/linux into arm/dt Apple SoC DT updates for 5.16. Adds pinctrl and PCIe nodes. * tag 'asahi-soc-dt-5.16-v2' of https://github.com/AsahiLinux/linux: arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address arm64: dts: apple: t8103: Add root port interrupt routing arm64: dts: apple: t8103: Add PCIe DARTs arm64: apple: Add PCIe node arm64: apple: Add pinctrl nodes Link: https://lore.kernel.org/r/6d41b29c-dafa-9b0e-d9ff-fe01eb6dce82@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c17c7cc775
|
|
@ -17,6 +17,7 @@
|
|||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -43,3 +44,25 @@
|
|||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Force the bus number assignments so that we can declare some of the
|
||||
* on-board devices and properties that are populated by the bootloader
|
||||
* (such as MAC addresses).
|
||||
*/
|
||||
&port00 {
|
||||
bus-range = <1 1>;
|
||||
};
|
||||
|
||||
&port01 {
|
||||
bus-range = <2 2>;
|
||||
};
|
||||
|
||||
&port02 {
|
||||
bus-range = <3 3>;
|
||||
ethernet0: pci@0,0 {
|
||||
reg = <0x30000 0x0 0x0 0x0 0x0>;
|
||||
/* To be filled by the loader */
|
||||
local-mac-address = [00 10 18 00 00 00];
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <dt-bindings/interrupt-controller/apple-aic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/pinctrl/apple.h>
|
||||
|
||||
/ {
|
||||
compatible = "apple,t8103", "apple,arm-platform";
|
||||
|
|
@ -131,5 +132,211 @@
|
|||
interrupt-controller;
|
||||
reg = <0x2 0x3b100000 0x0 0x8000>;
|
||||
};
|
||||
|
||||
pinctrl_ap: pinctrl@23c100000 {
|
||||
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||||
reg = <0x2 0x3c100000 0x0 0x100000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_ap 0 0 212>;
|
||||
apple,npins = <212>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pcie_pins: pcie-pins {
|
||||
pinmux = <APPLE_PINMUX(150, 1)>,
|
||||
<APPLE_PINMUX(151, 1)>,
|
||||
<APPLE_PINMUX(32, 1)>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_aop: pinctrl@24a820000 {
|
||||
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||||
reg = <0x2 0x4a820000 0x0 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_aop 0 0 42>;
|
||||
apple,npins = <42>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_nub: pinctrl@23d1f0000 {
|
||||
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||||
reg = <0x2 0x3d1f0000 0x0 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_nub 0 0 23>;
|
||||
apple,npins = <23>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_smc: pinctrl@23e820000 {
|
||||
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||||
reg = <0x2 0x3e820000 0x0 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_smc 0 0 16>;
|
||||
apple,npins = <16>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie0_dart_0: dart@681008000 {
|
||||
compatible = "apple,t8103-dart";
|
||||
reg = <0x6 0x81008000 0x0 0x4000>;
|
||||
#iommu-cells = <1>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie0_dart_1: dart@682008000 {
|
||||
compatible = "apple,t8103-dart";
|
||||
reg = <0x6 0x82008000 0x0 0x4000>;
|
||||
#iommu-cells = <1>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie0_dart_2: dart@683008000 {
|
||||
compatible = "apple,t8103-dart";
|
||||
reg = <0x6 0x83008000 0x0 0x4000>;
|
||||
#iommu-cells = <1>;
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie0: pcie@690000000 {
|
||||
compatible = "apple,t8103-pcie", "apple,pcie";
|
||||
device_type = "pci";
|
||||
|
||||
reg = <0x6 0x90000000 0x0 0x1000000>,
|
||||
<0x6 0x80000000 0x0 0x100000>,
|
||||
<0x6 0x81000000 0x0 0x4000>,
|
||||
<0x6 0x82000000 0x0 0x4000>,
|
||||
<0x6 0x83000000 0x0 0x4000>;
|
||||
reg-names = "config", "rc", "port0", "port1", "port2";
|
||||
|
||||
interrupt-parent = <&aic>;
|
||||
interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
msi-controller;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
|
||||
|
||||
|
||||
iommu-map = <0x100 &pcie0_dart_0 1 1>,
|
||||
<0x200 &pcie0_dart_1 1 1>,
|
||||
<0x300 &pcie0_dart_2 1 1>;
|
||||
iommu-map-mask = <0xff00>;
|
||||
|
||||
bus-range = <0 3>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
|
||||
<0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
|
||||
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port00: pci@0,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 152 0>;
|
||||
max-link-speed = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
|
||||
<0 0 0 2 &port00 0 0 0 1>,
|
||||
<0 0 0 3 &port00 0 0 0 2>,
|
||||
<0 0 0 4 &port00 0 0 0 3>;
|
||||
};
|
||||
|
||||
port01: pci@1,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x800 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 153 0>;
|
||||
max-link-speed = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
|
||||
<0 0 0 2 &port01 0 0 0 1>,
|
||||
<0 0 0 3 &port01 0 0 0 2>,
|
||||
<0 0 0 4 &port01 0 0 0 3>;
|
||||
};
|
||||
|
||||
port02: pci@2,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x1000 0x0 0x0 0x0 0x0>;
|
||||
reset-gpios = <&pinctrl_ap 33 0>;
|
||||
max-link-speed = <1>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
|
||||
<0 0 0 2 &port02 0 0 0 1>,
|
||||
<0 0 0 3 &port02 0 0 0 2>,
|
||||
<0 0 0 4 &port02 0 0 0 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue