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ARM: SoC DT updates for v5.16

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This is a rather large update for the ARM devicetree files, after a few
 quieter releases, with 775 total commits and 47 branches pulled into
 this one. There are 5 new SoC types plus some minor variations, and
 a total of 60 new machines, so I'm limiting the summary to the main
 noteworthy items:
 
  - Apple M1 gain support for PCI and pinctrl, getting a bit
    closer to a usable system out of the box.
 
  - Qualcomm gains support for Snapdragon 690 (aka SM6350) as
    well as SM7225, 11 new smartphones, and three additional
    Chromebooks, and improvements all over the place.
 
  - Samsung gains support for ExynosAutov9, an automotive version
    of their smartphone SoC, but otherwise no major changes.
 
  - Microchip adds the SAMA5D29 SoC in the SAMA5 family, and a
    number of improvements for the recently added SAMA7 family.
    The LAN966 SoC that was added in the platform code does not
    have dts files yet. Two board files are added for the older
    at91sam9g20 SoC
 
  - Aspeed supports two additional server boards using their AST2600
    as BMC, and improves support for qemu models
 
  - Rockchip RK3566/RK3688 gets added, along with six new
    development boards using RK3328/RK3399/RK3566, and one
    Chromebook tablet.
 
  - Two NAS boxes are added using the ARMv4 based Gemini platform
 
  - One new board is added to the Intel Arria SoC FPGA family
 
  - Marvell adds one network switch based on Armada 381 and the
    new MOCHAbin 7040 development board
 
  - NXP adds support for the S32G2 automotive SoC, two imx6 based
    ebook readers, and three additional development boards, which
    is notably less than their usual additions, but they also gain
    improvements to their many existing boards
 
  - STmicroelectronics adds their stm32mp13 SoC family along with
    a reference board
 
  - Renesas adds new versions of their R-Car Gen3 SoCs and many
    updates for their older generations
 
  - Broadcom adds support for a number of Cisco Meraki wireless
    controllers, along with two new boards and other updates for
    BCM53xx/BCM47xx networking SoCs and the Raspberry Pi
    boards
 
  - Mediatek improves support for the MT81xx SoCs used in Chromebooks
    as well as the MT76xx networking SoCs
 
  - NVIDIA adds a number of cleanups and additional support for
    more hardware on the already supported machines
 
  - TI K3 adds support for three new boards along with cleanups
 
  - Toshiba adds one board for the Visconti family
 
  - Xilinx adds five new ZynqMP based machines
 
  - Amlogic support is added for the Radxa Zero and two Jethub
    home automation controllers, along with changes to other
    machines
 
  - Rob Herring continues his work on fixing dtc warnings all over
    the tree.
 
  - Minor updates for TI OMAP, Mstar, Allwinner/sunxi, Hisilicon,
    Ux500, Unisoc
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Merge tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "This is a rather large update for the ARM devicetree files, after a
  few quieter releases, with 775 total commits and 47 branches pulled
  into this one.

  There are 5 new SoC types plus some minor variations, and a total of
  60 new machines, so I'm limiting the summary to the main noteworthy
  items:

   - Apple M1 gain support for PCI and pinctrl, getting a bit closer to
     a usable system out of the box.

   - Qualcomm gains support for Snapdragon 690 (aka SM6350) as well as
     SM7225, 11 new smartphones, and three additional Chromebooks, and
     improvements all over the place.

   - Samsung gains support for ExynosAutov9, an automotive version of
     their smartphone SoC, but otherwise no major changes.

   - Microchip adds the SAMA5D29 SoC in the SAMA5 family, and a number
     of improvements for the recently added SAMA7 family. The LAN966 SoC
     that was added in the platform code does not have dts files yet.
     Two board files are added for the older at91sam9g20 SoC

   - Aspeed supports two additional server boards using their AST2600 as
     BMC, and improves support for qemu models

   - Rockchip RK3566/RK3688 gets added, along with six new development
     boards using RK3328/RK3399/RK3566, and one Chromebook tablet.

   - Two NAS boxes are added using the ARMv4 based Gemini platform

   - One new board is added to the Intel Arria SoC FPGA family

   - Marvell adds one network switch based on Armada 381 and the new
     MOCHAbin 7040 development board

   - NXP adds support for the S32G2 automotive SoC, two imx6 based ebook
     readers, and three additional development boards, which is notably
     less than their usual additions, but they also gain improvements to
     their many existing boards

   - STmicroelectronics adds their stm32mp13 SoC family along with a
     reference board

   - Renesas adds new versions of their R-Car Gen3 SoCs and many updates
     for their older generations

   - Broadcom adds support for a number of Cisco Meraki wireless
     controllers, along with two new boards and other updates for
     BCM53xx/BCM47xx networking SoCs and the Raspberry Pi boards

   - Mediatek improves support for the MT81xx SoCs used in Chromebooks
     as well as the MT76xx networking SoCs

   - NVIDIA adds a number of cleanups and additional support for more
     hardware on the already supported machines

   - TI K3 adds support for three new boards along with cleanups

   - Toshiba adds one board for the Visconti family

   - Xilinx adds five new ZynqMP based machines

   - Amlogic support is added for the Radxa Zero and two Jethub home
     automation controllers, along with changes to other machines

   - Rob Herring continues his work on fixing dtc warnings all over the
     tree.

   - Minor updates for TI OMAP, Mstar, Allwinner/sunxi, Hisilicon,
     Ux500, Unisoc"

* tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (720 commits)
  arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address
  arm64: dts: apple: t8103: Add root port interrupt routing
  arm64: dts: apple: t8103: Add PCIe DARTs
  arm64: apple: Add PCIe node
  arm64: apple: Add pinctrl nodes
  ARM: dts: arm: Update ICST clock nodes 'reg' and node names
  ARM: dts: arm: Update register-bit-led nodes 'reg' and node names
  arm64: dts: exynos: add chipid node for exynosautov9 SoC
  ARM: dts: qcom: fix typo in IPQ8064 thermal-sensor node
  Revert "arm64: dts: qcom: msm8916-asus-z00l: Add sensors"
  arm64: dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node
  arm64: dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property
  arm64: dts: qcom: sm8350: Add CPU topology and idle-states
  arm64: dts: qcom: Drop unneeded extra device-specific includes
  arm64: dts: qcom: msm8916: Drop standalone smem node
  arm64: dts: qcom: Fix node name of rpm-msg-ram device nodes
  arm64: dts: qcom: msm8916-asus-z00l: Add sensors
  arm64: dts: qcom: msm8916-asus-z00l: Add SDCard
  arm64: dts: qcom: msm8916-asus-z00l: Add touchscreen
  arm64: dts: qcom: sdm845-oneplus: remove devinfo-size from ramoops node
  ...
This commit is contained in:
Linus Torvalds 2021-11-03 16:56:03 -07:00
commit ae45d84fc3
706 changed files with 47882 additions and 8105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.mailmap
View File

@ -279,6 +279,7 @@ Nicolas Pitre <nico@fluxnic.net> <nicolas.pitre@linaro.org>
Nicolas Pitre <nico@fluxnic.net> <nico@linaro.org>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.com>
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Oleksij Rempel <linux@rempel-privat.de> <bug-track@fisher-privat.net>
Oleksij Rempel <linux@rempel-privat.de> <external.Oleksij.Rempel@de.bosch.com>
Oleksij Rempel <linux@rempel-privat.de> <fixed-term.Oleksij.Rempel@de.bosch.com>

3
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -86,6 +86,7 @@ properties:
- enum:
- amlogic,p281
- oranth,tx3-mini
- jethome,jethub-j80
- const: amlogic,s905w
- const: amlogic,meson-gxl
@ -133,6 +134,7 @@ properties:
items:
- enum:
- amlogic,s400
- jethome,jethub-j100
- const: amlogic,a113d
- const: amlogic,meson-axg
@ -141,6 +143,7 @@ properties:
- enum:
- amediatech,x96-max
- amlogic,u200
- radxa,zero
- seirobotics,sei510
- const: amlogic,g12a

12
Documentation/devicetree/bindings/arm/atmel-at91.yaml
View File

@ -126,6 +126,18 @@ properties:
- const: atmel,sama5d3
- const: atmel,sama5
- description: CalAmp LMU5000 board
items:
- const: calamp,lmu5000
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- description: Exegin Q5xR5 board
items:
- const: exegin,q5xr5
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- items:
- enum:
- atmel,sama5d31

1
Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
View File

@ -19,6 +19,7 @@ properties:
items:
- enum:
- raspberrypi,400
- raspberrypi,4-compute-module
- raspberrypi,4-model-b
- const: brcm,bcm2711

65
Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
View File

@ -22,16 +22,61 @@ properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- brcm,bcm58522
- brcm,bcm58525
- brcm,bcm58535
- brcm,bcm58622
- brcm,bcm58623
- brcm,bcm58625
- brcm,bcm88312
- const: brcm,nsp
oneOf:
- description: BCM58522 based boards
items:
- enum:
- brcm,bcm958522er
- const: brcm,bcm58522
- const: brcm,nsp
- description: BCM58525 based boards
items:
- enum:
- brcm,bcm958525er
- brcm,bcm958525xmc
- const: brcm,bcm58525
- const: brcm,nsp
- description: BCM58535 based boards
items:
- const: brcm,bcm58535
- const: brcm,nsp
- description: BCM58622 based boards
items:
- enum:
- brcm,bcm958622hr
- const: brcm,bcm58622
- const: brcm,nsp
- description: BCM58623 based boards
items:
- enum:
- brcm,bcm958623hr
- const: brcm,bcm58623
- const: brcm,nsp
- description: BCM58625 based boards
items:
- enum:
- brcm,bcm958625hr
- brcm,bcm958625k
- meraki,mx64
- meraki,mx64-a0
- meraki,mx64w
- meraki,mx64w-a0
- meraki,mx65
- meraki,mx65w
- const: brcm,bcm58625
- const: brcm,nsp
- description: BCM88312 based boards
items:
- enum:
- brcm,bcm988312hr
- const: brcm,bcm88312
- const: brcm,nsp
additionalProperties: true

2
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -171,6 +171,8 @@ properties:
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
- qcom,kryo560
- qcom,kryo570
- qcom,kryo685
- qcom,scorpion

99
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -235,7 +235,7 @@ properties:
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
- technologic,imx6q-ts4900
- technologic,imx6q-ts7970
- toradex,apalis_imx6q # Apalis iMX6 Module
- toradex,apalis_imx6q # Apalis iMX6 Modules
- udoo,imx6q-udoo # Udoo i.MX6 Quad Board
- uniwest,imx6q-evi # Uniwest Evi
- variscite,dt6customboard
@ -314,18 +314,12 @@ properties:
- const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6q
- description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Module
- description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Modules
items:
- enum:
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
- const: toradex,apalis_imx6q
- const: fsl,imx6q
- description: i.MX6Q Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1
items:
- const: toradex,apalis_imx6q-ixora-v1.1
- const: toradex,apalis_imx6q-ixora
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
- const: toradex,apalis_imx6q
- const: fsl,imx6q
@ -393,6 +387,8 @@ properties:
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Modules
- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 V1.1 Modules
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
- vdl,lanmcu # Van der Laan LANMCU board
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
@ -466,20 +462,18 @@ properties:
- const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6dl
- description: i.MX6DL Toradex Colibri iMX6 Module on Colibri
Evaluation Board V3
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S Modules
items:
- const: toradex,colibri_imx6dl-eval-v3
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
- enum:
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6DL/S Module on Colibri Evaluation Board V3
- const: toradex,colibri_imx6dl # Colibri iMX6DL/S Module
- const: fsl,imx6dl
- description: i.MX6DL Toradex Colibri iMX6 Module V1.1 on Colibri
Evaluation Board V3
- description: i.MX6DL Boards with Toradex Colibri iMX6DL/S V1.1 Modules
items:
- const: toradex,colibri_imx6dl-v1_1-eval-v3
- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
- const: toradex,colibri_imx6dl-eval-v3
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
- enum:
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6DL/S V1.1 M. on Colibri Evaluation Board V3
- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6DL/S V1.1 Module
- const: fsl,imx6dl
- description: i.MX6S DHCOM DRC02 Board
@ -494,6 +488,7 @@ properties:
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
- kobo,tolino-shine2hd
- kobo,tolino-shine3
- kobo,tolino-vision5
- revotics,imx6sl-warp # Revotics WaRP Board
- const: fsl,imx6sl
@ -502,6 +497,7 @@ properties:
- enum:
- fsl,imx6sll-evk
- kobo,clarahd
- kobo,librah2o
- const: fsl,imx6sll
- description: i.MX6SX based Boards
@ -586,8 +582,9 @@ properties:
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Eval Board
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules
- const: fsl,imx6ull
- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
@ -605,6 +602,27 @@ properties:
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
items:
- enum:
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
- const: fsl,imx6dl
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
items:
- enum:
- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board
- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- const: fsl,imx6dl
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
items:
- enum:
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
- const: fsl,imx6dl
- description: Kontron N6411 S Board
items:
- const: kontron,imx6ull-n6411-s
@ -622,6 +640,7 @@ properties:
items:
- enum:
- element14,imx7s-warp # Element14 Warp i.MX7 Board
- toradex,colibri-imx7s # Colibri iMX7S Module
- const: fsl,imx7s
- description: i.MX7S Boards with Toradex Colibri iMX7S Module
@ -653,15 +672,8 @@ properties:
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
- technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
- toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
- toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on
# Aster Carrier Board
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on
# Colibri Evaluation Board V3
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on
# Colibri Evaluation Board V3
- toradex,colibri-imx7d # Colibri iMX7D Module
- toradex,colibri-imx7d-emmc # Colibri iMX7D 1GB (eMMC) Module
- zii,imx7d-rmu2 # ZII RMU2 Board
- zii,imx7d-rpu2 # ZII RPU2 Board
- const: fsl,imx7d
@ -686,12 +698,12 @@ properties:
- description: i.MX7D Boards with Toradex Colibri i.MX7D Module
items:
- enum:
- toradex,colibri-imx7d-aster # Module on Aster Carrier Board
- toradex,colibri-imx7d-eval-v3 # Module on Colibri Evaluation Board V3
- toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3
- const: toradex,colibri-imx7d
- const: fsl,imx7d
- description: i.MX7D Boards with Toradex Colibri i.MX7D eMMC Module
- description: i.MX7D Boards with Toradex Colibri i.MX7D 1GB (eMMC) Module
items:
- enum:
- toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board
@ -812,10 +824,10 @@ properties:
- enum:
- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
- toradex,colibri-imx8x # Colibri iMX8X Module
- toradex,colibri-imx8x # Colibri iMX8X Modules
- const: fsl,imx8qxp
- description: Toradex Colibri i.MX8 Evaluation Board
- description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules
items:
- enum:
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
@ -847,9 +859,10 @@ properties:
- description: VF610 based Boards
items:
- enum:
- fsl,vf610-twr # VF610 Tower Board
- lwn,bk4 # Liebherr BK4 controller
- phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board
- fsl,vf610-twr # VF610 Tower Board
- toradex,vf610-colibri_vf61 # Colibri VF61 Modules
- const: fsl,vf610
- description: Toradex Colibri VF61 Module on Colibri Evaluation Board
@ -886,6 +899,7 @@ properties:
- enum:
- fsl,ls1021a-moxa-uc-8410a
- fsl,ls1021a-qds
- fsl,ls1021a-tsn
- fsl,ls1021a-twr
- const: fsl,ls1021a
@ -977,6 +991,8 @@ properties:
- description: LX2160A based Boards
items:
- enum:
- fsl,lx2160a-bluebox3
- fsl,lx2160a-bluebox3-rev-a
- fsl,lx2160a-qds
- fsl,lx2160a-rdb
- fsl,lx2162a-qds
@ -990,6 +1006,13 @@ properties:
- const: solidrun,lx2160a-cex7
- const: fsl,lx2160a
- description: S32G2 based Boards
items:
- enum:
- nxp,s32g274a-evb
- nxp,s32g274a-rdb2
- const: nxp,s32g2
- description: S32V234 based Boards
items:
- enum:

1
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@ -32,6 +32,7 @@ properties:
- const: mediatek,mt6580
- items:
- enum:
- fairphone,fp1
- mundoreader,bq-aquaris5
- const: mediatek,mt6589
- items:

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View File

@ -43,6 +43,9 @@ properties:
"#clock-cells":
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
@ -56,4 +59,5 @@ examples:
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

23
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -25,6 +25,7 @@ description: |
The 'SoC' element must be one of the following strings:
apq8016
apq8026
apq8074
apq8084
apq8096
@ -44,6 +45,8 @@ description: |
sdm660
sdm845
sdx55
sdx65
sm7225
sm8150
sm8250
sm8350
@ -94,6 +97,14 @@ properties:
- items:
- enum:
- lg,lenok
- const: qcom,apq8026
- items:
- enum:
- asus,nexus7-flo
- lg,nexus4-mako
- sony,xperia-yuga
- qcom,apq8064-cm-qs600
- qcom,apq8064-ifc6410
- const: qcom,apq8064
@ -129,6 +140,7 @@ properties:
- enum:
- fairphone,fp2
- lge,hammerhead
- samsung,klte
- sony,xperia-amami
- sony,xperia-castor
- sony,xperia-honami
@ -163,6 +175,7 @@ properties:
- items:
- enum:
- qcom,ipq4019-ap-dk01.1-c1
- qcom,ipq4019-ap-dk04.1-c3
- qcom,ipq4019-ap-dk07.1-c1
- qcom,ipq4019-ap-dk07.1-c2
@ -206,6 +219,11 @@ properties:
- qcom,sdx55-t55
- const: qcom,sdx55
- items:
- enum:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,ipq6018-cp01
@ -217,6 +235,11 @@ properties:
- qcom,sa8155p-adp
- const: qcom,sa8155p
- items:
- enum:
- fairphone,fp4
- const: qcom,sm7225
- items:
- enum:
- qcom,sm8150-mtp

61
Documentation/devicetree/bindings/arm/renesas.yaml
View File

@ -255,12 +255,19 @@ properties:
- enum:
- renesas,h3ulcb
- renesas,m3ulcb
- renesas,m3nulcb
- enum:
- renesas,r8a779m0
- renesas,r8a779m1
- renesas,r8a779m2
- renesas,r8a779m3
- renesas,r8a779m4
- renesas,r8a779m5
- renesas,r8a779m8
- enum:
- renesas,r8a7795
- renesas,r8a77961
- renesas,r8a77965
- description: R-Car M3-N (R8A77965)
items:
@ -308,6 +315,14 @@ properties:
- const: renesas,falcon-cpu
- const: renesas,r8a779a0
- description: R-Car H3e (R8A779M0)
items:
- enum:
- renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m0
- const: renesas,r8a7795
- description: R-Car H3e-2G (R8A779M1)
items:
- enum:
@ -316,6 +331,14 @@ properties:
- const: renesas,r8a779m1
- const: renesas,r8a7795
- description: R-Car M3e (R8A779M2)
items:
- enum:
- renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m2
- const: renesas,r8a77961
- description: R-Car M3e-2G (R8A779M3)
items:
- enum:
@ -324,6 +347,44 @@ properties:
- const: renesas,r8a779m3
- const: renesas,r8a77961
- description: R-Car M3Ne (R8A779M4)
items:
- enum:
- renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m4
- const: renesas,r8a77965
- description: R-Car M3Ne-2G (R8A779M5)
items:
- enum:
- renesas,m3nulcb # M3NULCB (R-Car Starter Kit Pro)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m5
- const: renesas,r8a77965
- description: R-Car E3e (R8A779M6)
items:
- enum:
- renesas,ebisu # Ebisu
- const: renesas,r8a779m6
- const: renesas,r8a77990
- description: R-Car D3e (R8A779M7)
items:
- enum:
- renesas,draak # Draak
- const: renesas,r8a779m7
- const: renesas,r8a77995
- description: R-Car H3Ne (R8A779M8)
items:
- enum:
- renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier)
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version)
- const: renesas,r8a779m8
- const: renesas,r8a7795
- description: RZ/N1D (R9A06G032)
items:
- enum:

48
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -115,6 +115,11 @@ properties:
- const: firefly,roc-rk3328-cc
- const: rockchip,rk3328
- description: Firefly ROC-RK3328-PC
items:
- const: firefly,roc-rk3328-pc
- const: rockchip,rk3328
- description: Firefly ROC-RK3399-PC
items:
- enum:
@ -122,6 +127,12 @@ properties:
- firefly,roc-rk3399-pc-mezzanine
- const: rockchip,rk3399
- description: Firefly ROC-RK3399-PC-PLUS
items:
- enum:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
@ -287,6 +298,34 @@ properties:
- const: google,veyron
- const: rockchip,rk3288
- description: Google Scarlet - Dumo (ASUS Chromebook Tablet CT100)
items:
- const: google,scarlet-rev15-sku0
- const: google,scarlet-rev15
- const: google,scarlet-rev14-sku0
- const: google,scarlet-rev14
- const: google,scarlet-rev13-sku0
- const: google,scarlet-rev13
- const: google,scarlet-rev12-sku0
- const: google,scarlet-rev12
- const: google,scarlet-rev11-sku0
- const: google,scarlet-rev11
- const: google,scarlet-rev10-sku0
- const: google,scarlet-rev10
- const: google,scarlet-rev9-sku0
- const: google,scarlet-rev9
- const: google,scarlet-rev8-sku0
- const: google,scarlet-rev8
- const: google,scarlet-rev7-sku0
- const: google,scarlet-rev7
- const: google,scarlet-rev6-sku0
- const: google,scarlet-rev6
- const: google,scarlet-rev5-sku0
- const: google,scarlet-rev5
- const: google,scarlet
- const: google,gru
- const: rockchip,rk3399
- description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10)
items:
- const: google,scarlet-rev15-sku7
@ -455,16 +494,23 @@ properties:
- const: pine64,rockpro64
- const: rockchip,rk3399
- description: Pine64 Quartz64 Model A
items:
- const: pine64,quartz64-a
- const: rockchip,rk3566
- description: Radxa Rock
items:
- const: radxa,rock
- const: rockchip,rk3188
- description: Radxa ROCK Pi 4A/B/C
- description: Radxa ROCK Pi 4A/A+/B/B+/C
items:
- enum:
- radxa,rockpi4a
- radxa,rockpi4a-plus
- radxa,rockpi4b
- radxa,rockpi4b-plus
- radxa,rockpi4c
- const: radxa,rockpi4
- const: rockchip,rk3399

4
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
View File

@ -22,7 +22,9 @@ select:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
required:
- compatible
@ -34,7 +36,9 @@ properties:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- const: syscon
- const: simple-mfd

6
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
View File

@ -199,6 +199,12 @@ properties:
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
- const: samsung,exynos7
- description: Exynos Auto v9 based boards
items:
- enum:
- samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
- const: samsung,exynosautov9
required:
- compatible

5
Documentation/devicetree/bindings/arm/sprd/sprd.yaml
View File

@ -30,6 +30,11 @@ properties:
- sprd,sp9863a-1h10
- const: sprd,sc9863a
- items:
- enum:
- sprd,ums512-1h10
- const: sprd,ums512
additionalProperties: true
...

4
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@ -55,6 +55,10 @@ properties:
- enum:
- st,stm32h750i-art-pi
- const: st,stm32h750
- items:
- enum:
- st,stm32mp135f-dk
- const: st,stm32mp135
- items:
- enum:
- shiratech,stm32mp157a-iot-box # IoT Box

1
Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
View File

@ -30,6 +30,7 @@ properties:
enum:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-h3-mbus
- allwinner,sun8i-r40-mbus
- allwinner,sun50i-a64-mbus
reg:

38
Documentation/devicetree/bindings/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml Normal file
View File

@ -0,0 +1,38 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner CPU Configuration Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- allwinner,sun6i-a31-cpuconfig
- allwinner,sun8i-a23-cpuconfig
- allwinner,sun8i-a83t-cpucfg
- allwinner,sun8i-a83t-r-cpucfg
- allwinner,sun9i-a80-cpucfg
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
cpucfg@1f01c00 {
compatible = "allwinner,sun6i-a31-cpuconfig";
reg = <0x01f01c00 0x300>;
};
...

33
Documentation/devicetree/bindings/arm/sunxi/allwinner,sun9i-a80-prcm.yaml Normal file
View File

@ -0,0 +1,33 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun9i-a80-prcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 PRCM Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
const: allwinner,sun9i-a80-prcm
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
prcm@8001400 {
compatible = "allwinner,sun9i-a80-prcm";
reg = <0x08001400 0x200>;
};
...

15
Documentation/devicetree/bindings/arm/ti/k3.yaml
View File

@ -24,16 +24,27 @@ properties:
- enum:
- ti,am654-evm
- siemens,iot2050-basic
- siemens,iot2050-basic-pg2
- siemens,iot2050-advanced
- siemens,iot2050-advanced-pg2
- const: ti,am654
- description: K3 J721E SoC
items:
oneOf:
- const: ti,j721e
- items:
- enum:
- ti,j721e-evm
- ti,j721e-sk
- const: ti,j721e
- description: K3 J7200 SoC
items:
oneOf:
- const: ti,j7200
- items:
- enum:
- ti,j7200-evm
- const: ti,j7200
- description: K3 AM642 SoC
items:

1
Documentation/devicetree/bindings/arm/toshiba.yaml
View File

@ -18,6 +18,7 @@ properties:
items:
- enum:
- toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board
- toshiba,tmpv7708-visrobo-vrb # TMPV7708 VisROBO VRB board
- const: toshiba,tmpv7708
additionalProperties: true

17
Documentation/devicetree/bindings/arm/xilinx.yaml
View File

@ -87,6 +87,7 @@ properties:
- xlnx,zynqmp-zcu102-revA
- xlnx,zynqmp-zcu102-revB
- xlnx,zynqmp-zcu102-rev1.0
- xlnx,zynqmp-zcu102-rev1.1
- const: xlnx,zynqmp-zcu102
- const: xlnx,zynqmp
@ -115,6 +116,22 @@ properties:
- const: xlnx,zynqmp-zcu111
- const: xlnx,zynqmp
- description: Xilinx Kria SOMs
items:
- const: xlnx,zynqmp-sm-k26-rev1
- const: xlnx,zynqmp-sm-k26-revB
- const: xlnx,zynqmp-sm-k26-revA
- const: xlnx,zynqmp-sm-k26
- const: xlnx,zynqmp
- description: Xilinx Kria SOMs (starter)
items:
- const: xlnx,zynqmp-smk-k26-rev1
- const: xlnx,zynqmp-smk-k26-revB
- const: xlnx,zynqmp-smk-k26-revA
- const: xlnx,zynqmp-smk-k26
- const: xlnx,zynqmp
additionalProperties: true
...

3
Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
View File

@ -47,6 +47,9 @@ properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
required:
- "#clock-cells"
- compatible

3
Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml
View File

@ -51,6 +51,9 @@ properties:
dma-names:
const: audio-rx
power-domains:
maxItems: 1
required:
- compatible
- reg

3
Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml
View File

@ -24,6 +24,9 @@ properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg

3
Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml
View File

@ -24,6 +24,9 @@ properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg

6
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
View File

@ -19,6 +19,11 @@ Required properties:
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
Optional properties:
- resets: list of phandle + reset specifier pair, as described in [1].
[1] Documentation/devicetree/bindings/reset/reset.txt
MIPI TX Configuration Module
============================
@ -45,6 +50,7 @@ dsi0: dsi@1401b000 {
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";

106
Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml Normal file
View File

@ -0,0 +1,106 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Device tree binding for NVIDIA Tegra NVDEC
description: |
NVDEC is the hardware video decoder present on NVIDIA Tegra210
and newer chips. It is located on the Host1x bus and typically
programmed through Host1x channels.
maintainers:
- Thierry Reding <treding@gmail.com>
- Mikko Perttunen <mperttunen@nvidia.com>
properties:
$nodename:
pattern: "^nvdec@[0-9a-f]*$"
compatible:
enum:
- nvidia,tegra210-nvdec
- nvidia,tegra186-nvdec
- nvidia,tegra194-nvdec
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: nvdec
resets:
maxItems: 1
reset-names:
items:
- const: nvdec
power-domains:
maxItems: 1
iommus:
maxItems: 1
dma-coherent: true
interconnects:
items:
- description: DMA read memory client
- description: DMA read 2 memory client
- description: DMA write memory client
interconnect-names:
items:
- const: dma-mem
- const: read-1
- const: write
nvidia,host1x-class:
description: |
Host1x class of the engine, used to specify the targeted engine
when programming the engine through Host1x channels or when
configuring engine-specific behavior in Host1x.
default: 0xf0
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
nvdec@15480000 {
compatible = "nvidia,tegra186-nvdec";
reg = <0x15480000 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVDEC>;
clock-names = "nvdec";
resets = <&bpmp TEGRA186_RESET_NVDEC>;
reset-names = "nvdec";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
interconnect-names = "dma-mem", "read-1", "write";
iommus = <&smmu TEGRA186_SID_NVDEC>;
};

157
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
View File

@ -1,157 +0,0 @@
Device tree bindings for OMAP general purpose memory controllers (GPMC)
The actual devices are instantiated from the child nodes of a GPMC node.
Required properties:
- compatible: Should be set to one of the following:
ti,omap2420-gpmc (omap2420)
ti,omap2430-gpmc (omap2430)
ti,omap3430-gpmc (omap3430 & omap3630)
ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
ti,am3352-gpmc (am335x devices)
- reg: A resource specifier for the register space
(see the example below)
- ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
completed.
- #address-cells: Must be set to 2 to allow memory address translation
- #size-cells: Must be set to 1 to allow CS address passing
- gpmc,num-cs: The maximum number of chip-select lines that controller
can support.
- gpmc,num-waitpins: The maximum number of wait pins that controller can
support.
- ranges: Must be set up to reflect the memory layout with four
integer values for each chip-select line in use:
<cs-number> 0 <physical address of mapping> <size>
Currently, calculated values derived from the contents
of the per-CS register GPMC_CONFIG7 (as set up by the
bootloader) are used for the physical address decoding.
As this will change in the future, filling correct
values here is a requirement.
- interrupt-controller: The GPMC driver implements and interrupt controller for
the NAND events "fifoevent" and "termcount" plus the
rising/falling edges on the GPMC_WAIT pins.
The interrupt number mapping is as follows
0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 pin edge
3 - GPMC_WAIT1 pin edge, and so on.
- interrupt-cells: Must be set to 2
- gpio-controller: The GPMC driver implements a GPIO controller for the
GPMC WAIT pins that can be used as general purpose inputs.
0 maps to GPMC_WAIT0 pin.
- gpio-cells: Must be set to 2
Required properties when using NAND prefetch dma:
- dmas GPMC NAND prefetch dma channel
- dma-names Must be set to "rxtx"
Timing properties for child nodes. All are optional and default to 0.
- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
- gpmc,cs-on-ns: Assertion time
- gpmc,cs-rd-off-ns: Read deassertion time
- gpmc,cs-wr-off-ns: Write deassertion time
ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
- gpmc,adv-on-ns: Assertion time
- gpmc,adv-rd-off-ns: Read deassertion time
- gpmc,adv-wr-off-ns: Write deassertion time
- gpmc,adv-aad-mux-on-ns: Assertion time for AAD
- gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD
- gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD
WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
- gpmc,we-on-ns Assertion time
- gpmc,we-off-ns: Deassertion time
OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
- gpmc,oe-on-ns: Assertion time
- gpmc,oe-off-ns: Deassertion time
- gpmc,oe-aad-mux-on-ns: Assertion time for AAD
- gpmc,oe-aad-mux-off-ns: Deassertion time for AAD
Access time and cycle time timings (in nanoseconds) corresponding to
GPMC_CONFIG5:
- gpmc,page-burst-access-ns: Multiple access word delay
- gpmc,access-ns: Start-cycle to first data valid delay
- gpmc,rd-cycle-ns: Total read cycle time
- gpmc,wr-cycle-ns: Total write cycle time
- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
- gpmc,clk-activation-ns: GPMC clock activation time
- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
data
Boolean timing parameters. If property is present parameter enabled and
disabled if omitted:
- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
accesses to a different CS
- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
accesses to the same CS
- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
- gpmc,time-para-granularity: Multiply all access times by 2
The following are only applicable to OMAP3+ and AM335x:
- gpmc,wr-access-ns: In synchronous write mode, for single or
burst accesses, defines the number of
GPMC_FCLK cycles from start access time
to the GPMC_CLK rising edge used by the
memory device for the first data capture.
- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
the time when the first data is driven on
the address-data bus.
GPMC chip-select settings properties for child nodes. All are optional.
- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
- gpmc,burst-wrap Enables wrap bursting
- gpmc,burst-read Enables read page/burst mode
- gpmc,burst-write Enables write page/burst mode
- gpmc,device-width Total width of device(s) connected to a GPMC
chip-select in bytes. The GPMC supports 8-bit
and 16-bit devices and so this property must be
1 or 2.
- gpmc,mux-add-data Address and data multiplexing configuration.
Valid values are 1 for address-address-data
multiplexing mode and 2 for address-data
multiplexing mode.
- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
is this is not set.
- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
is this is not set.
- gpmc,wait-pin Wait-pin used by client. Must be less than
"gpmc,num-waitpins".
- gpmc,wait-on-read Enables wait monitoring on reads.
- gpmc,wait-on-write Enables wait monitoring on writes.
Example for an AM33xx board:
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
/* child nodes go here */
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: device tree bindings for children of the Texas Instruments GPMC
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
This binding is meant for the child nodes of the GPMC node. The node
represents any device connected to the GPMC bus. It may be a Flash chip,
RAM chip or Ethernet controller, etc. These properties are meant for
configuring the GPMC settings/timings and will accompany the bindings
supported by the respective device.
properties:
reg: true
# GPMC Timing properties for child nodes. All are optional and default to 0.
gpmc,sync-clk-ps:
description: Minimum clock period for synchronous mode
default: 0
# Chip-select signal timings corresponding to GPMC_CONFIG2:
gpmc,cs-on-ns:
description: Assertion time
default: 0
gpmc,cs-rd-off-ns:
description: Read deassertion time
default: 0
gpmc,cs-wr-off-ns:
description: Write deassertion time
default: 0
# ADV signal timings corresponding to GPMC_CONFIG3:
gpmc,adv-on-ns:
description: Assertion time
default: 0
gpmc,adv-rd-off-ns:
description: Read deassertion time
default: 0
gpmc,adv-wr-off-ns:
description: Write deassertion time
default: 0
gpmc,adv-aad-mux-on-ns:
description: Assertion time for AAD
default: 0
gpmc,adv-aad-mux-rd-off-ns:
description: Read deassertion time for AAD
default: 0
gpmc,adv-aad-mux-wr-off-ns:
description: Write deassertion time for AAD
default: 0
# WE signals timings corresponding to GPMC_CONFIG4:
gpmc,we-on-ns:
description: Assertion time
default: 0
gpmc,we-off-ns:
description: Deassertion time
default: 0
# OE signals timings corresponding to GPMC_CONFIG4:
gpmc,oe-on-ns:
description: Assertion time
default: 0
gpmc,oe-off-ns:
description: Deassertion time
default: 0
gpmc,oe-aad-mux-on-ns:
description: Assertion time for AAD
default: 0
gpmc,oe-aad-mux-off-ns:
description: Deassertion time for AAD
default: 0
# Access time and cycle time timings (in nanoseconds) corresponding to
# GPMC_CONFIG5:
gpmc,page-burst-access-ns:
description: Multiple access word delay
default: 0
gpmc,access-ns:
description: Start-cycle to first data valid delay
default: 0
gpmc,rd-cycle-ns:
description: Total read cycle time
default: 0
gpmc,wr-cycle-ns:
description: Total write cycle time
default: 0
gpmc,bus-turnaround-ns:
description: Turn-around time between successive accesses
default: 0
gpmc,cycle2cycle-delay-ns:
description: Delay between chip-select pulses
default: 0
gpmc,clk-activation-ns:
description: GPMC clock activation time
default: 0
gpmc,wait-monitoring-ns:
description: Start of wait monitoring with regard to valid data
default: 0
# Boolean timing parameters. If property is present, parameter is enabled
# otherwise disabled.
gpmc,adv-extra-delay:
description: ADV signal is delayed by half GPMC clock
type: boolean
gpmc,cs-extra-delay:
description: CS signal is delayed by half GPMC clock
type: boolean
gpmc,cycle2cycle-diffcsen:
description: |
Add "cycle2cycle-delay" between successive accesses
to a different CS
type: boolean
gpmc,cycle2cycle-samecsen:
description: |
Add "cycle2cycle-delay" between successive accesses
to the same CS
type: boolean
gpmc,oe-extra-delay:
description: OE signal is delayed by half GPMC clock
type: boolean
gpmc,we-extra-delay:
description: WE signal is delayed by half GPMC clock
type: boolean
gpmc,time-para-granularity:
description: Multiply all access times by 2
type: boolean
# The following two properties are applicable only to OMAP3+ and AM335x:
gpmc,wr-access-ns:
description: |
In synchronous write mode, for single or
burst accesses, defines the number of
GPMC_FCLK cycles from start access time
to the GPMC_CLK rising edge used by the
memory device for the first data capture.
default: 0
gpmc,wr-data-mux-bus-ns:
description: |
In address-data multiplex mode, specifies
the time when the first data is driven on
the address-data bus.
default: 0
# GPMC chip-select settings properties for child nodes. All are optional.
gpmc,burst-length:
description: Page/burst length.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 4, 8, 16]
default: 0
gpmc,burst-wrap:
description: Enables wrap bursting
type: boolean
gpmc,burst-read:
description: Enables read page/burst mode
type: boolean
gpmc,burst-write:
description: Enables write page/burst mode
type: boolean
gpmc,device-width:
description: |
Total width of device(s) connected to a GPMC
chip-select in bytes. The GPMC supports 8-bit
and 16-bit devices and so this property must be
1 or 2.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
default: 1
gpmc,mux-add-data:
description: |
Address and data multiplexing configuration.
Valid values are
0 for Non multiplexed mode
1 for address-address-data multiplexing mode and
2 for address-data multiplexing mode.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
gpmc,sync-read:
description: |
Enables synchronous read. Defaults to asynchronous
is this is not set.
type: boolean
gpmc,sync-write:
description: |
Enables synchronous writes. Defaults to asynchronous
is this is not set.
type: boolean
gpmc,wait-pin:
description: |
Wait-pin used by client. Must be less than "gpmc,num-waitpins".
$ref: /schemas/types.yaml#/definitions/uint32
gpmc,wait-on-read:
description: Enables wait monitoring on reads.
type: boolean
gpmc,wait-on-write:
description: Enables wait monitoring on writes.
type: boolean
required:
- reg
# the GPMC child will have its own native properties
additionalProperties: true

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC Memory Controller device-tree bindings
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
- Asynchronous SRAM-like memories and ASICs
- Asynchronous, synchronous, and page mode burst NOR flash
- NAND flash
- Pseudo-SRAM devices
properties:
compatible:
items:
- enum:
- ti,am3352-gpmc
- ti,omap2420-gpmc
- ti,omap2430-gpmc
- ti,omap3430-gpmc
- ti,omap4430-gpmc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
description: |
Functional clock. Used for bus timing calculations and
GPMC configuration.
clock-names:
items:
- const: fck
dmas:
items:
- description: DMA channel for GPMC NAND prefetch
dma-names:
items:
- const: rxtx
"#address-cells": true
"#size-cells": true
gpmc,num-cs:
description: maximum number of supported chip-select lines.
$ref: /schemas/types.yaml#/definitions/uint32
gpmc,num-waitpins:
description: maximum number of supported wait pins.
$ref: /schemas/types.yaml#/definitions/uint32
ranges:
minItems: 1
description: |
Must be set up to reflect the memory layout with four
integer values for each chip-select line in use,
<cs-number> 0 <physical address of mapping> <size>
items:
- description: NAND bank 0
- description: NOR/SRAM bank 0
- description: NOR/SRAM bank 1
'#interrupt-cells':
const: 2
interrupt-controller:
description: |
The GPMC driver implements and interrupt controller for
the NAND events "fifoevent" and "termcount" plus the
rising/falling edges on the GPMC_WAIT pins.
The interrupt number mapping is as follows
0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 pin edge
3 - GPMC_WAIT1 pin edge, and so on.
'#gpio-cells':
const: 2
gpio-controller:
description: |
The GPMC driver implements a GPIO controller for the
GPMC WAIT pins that can be used as general purpose inputs.
0 maps to GPMC_WAIT0 pin.
ti,hwmods:
description:
Name of the HWMOD associated with GPMC. This is for legacy
omap2/3 platforms only.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
ti,no-idle-on-init:
description:
Prevent idling the module at init. This is for legacy omap2/3
platforms only.
type: boolean
deprecated: true
patternProperties:
"@[0-7],[a-f0-9]+$":
type: object
description: |
The child device node represents the device connected to the GPMC
bus. The device can be a NAND chip, SRAM device, NOR device
or an ASIC.
allOf:
- $ref: "ti,gpmc-child.yaml"
unevaluatedProperties: false
required:
- compatible
- reg
- gpmc,num-cs
- gpmc,num-waitpins
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
clocks = <&l3s_clkctrl>;
clock-names = "fck";
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>;
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
};
};

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Device tree bindings for GPMC connected NANDs
GPMC connected NAND (found on OMAP boards) are represented as child nodes of
the GPMC controller with a name of "nand".
All timing relevant properties as well as generic gpmc child properties are
explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For NAND specific properties such as ECC modes or bus width, please refer to
Documentation/devicetree/bindings/mtd/nand-controller.yaml
Required properties:
- compatible: "ti,omap2-nand"
- reg: range id (CS number), base offset and length of the
NAND I/O space
- interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
Optional properties:
- nand-bus-width: Set this numeric value to 16 if the hardware
is wired that way. If not specified, a bus
width of 8 is assumed.
- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
"sw" 1-bit Hamming ecc code via software
"hw" <deprecated> use "ham1" instead
"hw-romcode" <deprecated> use "ham1" instead
"ham1" 1-bit Hamming ecc code
"bch4" 4-bit BCH ecc code
"bch8" 8-bit BCH ecc code
"bch16" 16-bit BCH ECC code
Refer below "How to select correct ECC scheme for your device ?"
- ti,nand-xfer-type: A string setting the data transfer type. One of:
"prefetch-polled" Prefetch polled mode (default)
"polled" Polled mode, without prefetch
"prefetch-dma" Prefetch enabled DMA mode
"prefetch-irq" Prefetch enabled irq mode
- elm_id: <deprecated> use "ti,elm-id" instead
- ti,elm-id: Specifies phandle of the ELM devicetree node.
ELM is an on-chip hardware engine on TI SoC which is used for
locating ECC errors for BCHx algorithms. SoC devices which have
ELM hardware engines should specify this device node in .dtsi
Using ELM for ECC error correction frees some CPU cycles.
- rb-gpios: GPIO specifier for the ready/busy# pin.
For inline partition table parsing (optional):
- #address-cells: should be set to 1
- #size-cells: should be set to 1
Example for an AM33xx board:
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x36c>;
interrupts = <100>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
elm_id = <&elm>;
interrupt-controller;
#interrupt-cells = <2>;
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
/* partitions go here */
};
};
How to select correct ECC scheme for your device ?
--------------------------------------------------
Higher ECC scheme usually means better protection against bit-flips and
increased system lifetime. However, selection of ECC scheme is dependent
on various other factors also like;
(1) support of built in hardware engines.
Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot
support ecc-schemes with hardware error-correction (BCHx_HW). However
such SoC can use ecc-schemes with software library for error-correction
(BCHx_HW_DETECTION_SW). The error correction capability with software
library remains equivalent to their hardware counter-part, but there is
slight CPU penalty when too many bit-flips are detected during reads.
(2) Device parameters like OOBSIZE.
Other factor which governs the selection of ecc-scheme is oob-size.
Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
so the device should have enough free bytes available its OOB/Spare
area to accommodate ECC for entire page. In general following expression
helps in determining if given device can accommodate ECC syndrome:
"2 + (PAGESIZE / 512) * ECC_BYTES" <= OOBSIZE"
where
OOBSIZE number of bytes in OOB/spare area
PAGESIZE number of bytes in main-area of device page
ECC_BYTES number of ECC bytes generated to protect
512 bytes of data, which is:
'3' for HAM1_xx ecc schemes
'7' for BCH4_xx ecc schemes
'14' for BCH8_xx ecc schemes
'26' for BCH16_xx ecc schemes
Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and
trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
which is greater than capacity of NAND device (OOBSIZE=64)
Hence, BCH16 cannot be supported on given device. But it can
probably use lower ecc-schemes like BCH8.
Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
which can be accommodated in the OOB/Spare area of this device
(OOBSIZE=128). So this device can use BCH16 ecc-scheme.

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Device tree bindings for NOR flash connect to TI GPMC
NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
child nodes of the GPMC controller with a name of "nor".
All timing relevant properties as well as generic GPMC child properties are
explained in a separate documents. Please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Required properties:
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
16-bit devices and so must be either 1 or 2 bytes.
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
- gpmc,cs-on-ns: Chip-select assertion time
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
- gpmc,oe-on-ns: Output-enable assertion time
- gpmc,oe-off-ns: Output-enable de-assertion time
- gpmc,we-on-ns Write-enable assertion time
- gpmc,we-off-ns: Write-enable de-assertion time
- gpmc,access-ns: Start cycle to first data capture (read access)
- gpmc,rd-cycle-ns: Total read cycle time
- gpmc,wr-cycle-ns: Total write cycle time
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
- reg: Chip-select, base address (relative to chip-select)
and size of NOR flash. Note that base address will be
typically 0 as this is the start of the chip-select.
Optional properties:
- gpmc,XXX Additional GPMC timings and settings parameters. See
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Optional properties for partition table parsing:
- #address-cells: should be set to 1
- #size-cells: should be set to 1
Example:
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc", "simple-bus";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x1000>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x10000000 0x08000000>;
nor@0,0 {
compatible = "cfi-flash";
linux,mtd-name= "intel,pf48f6000m0y1be";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x08000000>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
partition@0 {
label = "bootloader-nor";
reg = <0 0x40000>;
};
partition@40000 {
label = "params-nor";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "kernel-nor";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "filesystem-nor";
reg = <0x240000 0x7d80000>;
};
};
};

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Device tree bindings for GPMC connected OneNANDs
GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of
the GPMC controller with a name of "onenand".
All timing relevant properties as well as generic gpmc child properties are
explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Required properties:
- compatible: "ti,omap2-onenand"
- reg: The CS line the peripheral is connected to
- gpmc,device-width: Width of the ONENAND device connected to the GPMC
in bytes. Must be 1 or 2.
Optional properties:
- int-gpios: GPIO specifier for the INT pin.
For inline partition table parsing (optional):
- #address-cells: should be set to 1
- #size-cells: should be set to 1
Example for an OMAP3430 board:
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x1000000>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
onenand@0 {
compatible = "ti,omap2-onenand";
reg = <0 0 0>; /* CS0, offset 0 */
gpmc,device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
/* partitions go here */
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC NAND Flash controller.
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
GPMC NAND controller/Flash is represented as a child of the
GPMC controller node.
properties:
compatible:
const: ti,omap2-nand
reg:
maxItems: 1
interrupts:
items:
- description: Interrupt for fifoevent
- description: Interrupt for termcount
"#address-cells": true
"#size-cells": true
ti,nand-ecc-opt:
description: Desired ECC algorithm
$ref: /schemas/types.yaml#/definitions/string
enum: [sw, ham1, bch4, bch8, bch16]
ti,nand-xfer-type:
description: Data transfer method between controller and chip.
$ref: /schemas/types.yaml#/definitions/string
enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
default: prefetch-polled
ti,elm-id:
description:
phandle to the ELM (Error Location Module).
$ref: /schemas/types.yaml#/definitions/phandle
nand-bus-width:
description:
Bus width to the NAND chip
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
default: 8
patternProperties:
"@[0-9a-f]+$":
$ref: "/schemas/mtd/partitions/partition.yaml"
allOf:
- $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
required:
- compatible
- reg
- ti,nand-ecc-opt
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
#address-cells = <1>;
#size-cells = <1>;
/* NAND generic properties */
nand-bus-width = <8>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
/* GPMC properties*/
gpmc,device-width = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
};
};

81
Documentation/devicetree/bindings/mtd/ti,gpmc-onenand.yaml Normal file
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@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-onenand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OneNAND over Texas Instruments GPMC bus.
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
GPMC connected OneNAND (found on OMAP boards) are represented
as child nodes of the GPMC controller.
properties:
compatible:
const: ti,omap2-onenand
reg:
items:
- description: |
Chip Select number, register offset and size of
OneNAND register window.
"#address-cells": true
"#size-cells": true
int-gpios:
description: GPIO specifier for the INT pin.
patternProperties:
"@[0-9a-f]+$":
$ref: "/schemas/mtd/partitions/partition.yaml"
allOf:
- $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
examples:
- |
gpmc: memory-controller@6e000000 {
compatible = "ti,omap3430-gpmc";
reg = <0x6e000000 0x02d0>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
clocks = <&l3s_clkctrl>;
clock-names = "fck";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
<1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
onenand@0,0 {
compatible = "ti,omap2-onenand";
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x00000000 0x00100000>;
};
partition@100000 {
label = "config";
reg = <0x00100000 0x002c0000>;
};
};
};

97
Documentation/devicetree/bindings/net/gpmc-eth.txt
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@ -1,97 +0,0 @@
Device tree bindings for Ethernet chip connected to TI GPMC
Besides being used to interface with external memory devices, the
General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
such as ethernet controllers to processors using the TI GPMC as a data bus.
Ethernet controllers connected to TI GPMC are represented as child nodes of
the GPMC controller with an "ethernet" name.
All timing relevant properties as well as generic GPMC child properties are
explained in a separate documents. Please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For the properties relevant to the ethernet controller connected to the GPMC
refer to the binding documentation of the device. For example, the documentation
for the SMSC 911x is Documentation/devicetree/bindings/net/smsc,lan9115.yaml
Child nodes need to specify the GPMC bus address width using the "bank-width"
property but is possible that an ethernet controller also has a property to
specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
address width, it supports devices with 32-bit word registers.
For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
Required properties:
- bank-width: Address width of the device in bytes. GPMC supports 8-bit
and 16-bit devices and so must be either 1 or 2 bytes.
- compatible: Compatible string property for the ethernet child device.
- gpmc,cs-on-ns: Chip-select assertion time
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
- gpmc,oe-on-ns: Output-enable assertion time
- gpmc,oe-off-ns: Output-enable de-assertion time
- gpmc,we-on-ns: Write-enable assertion time
- gpmc,we-off-ns: Write-enable de-assertion time
- gpmc,access-ns: Start cycle to first data capture (read access)
- gpmc,rd-cycle-ns: Total read cycle time
- gpmc,wr-cycle-ns: Total write cycle time
- reg: Chip-select, base address (relative to chip-select)
and size of the memory mapped for the device.
Note that base address will be typically 0 as this
is the start of the chip-select.
Optional properties:
- gpmc,XXX Additional GPMC timings and settings parameters. See
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Example:
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x1000>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <5 0 0x2c000000 0x1000000>;
ethernet@5,0 {
compatible = "smsc,lan9221", "smsc,lan9115";
reg = <5 0 0xff>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
interrupt-parent = <&gpio6>;
interrupts = <16>;
vmmc-supply = <&vddvario>;
vmmc_aux-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};
};

2
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
View File

@ -197,7 +197,7 @@ Tegra194 RC mode:
Tegra194 EP mode:
-----------------
pcie_ep@141a0000 {
pcie-ep@141a0000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */

22
Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt
View File

@ -1,22 +0,0 @@
* Freescale LINFlexD UART
The LINFlexD controller implements several LIN protocol versions, as well as
support for full-duplex UART communication through 8-bit and 9-bit frames.
See chapter 47 ("LINFlexD") in the reference manual[1].
Required properties:
- compatible :
- "fsl,s32v234-linflexuart" for LINFlexD configured in UART mode, which
is compatible with the one integrated on S32V234 SoC
- reg : Address and length of the register set for the device
- interrupts : Should contain uart interrupt
Example:
uart0: serial@40053000 {
compatible = "fsl,s32v234-linflexuart";
reg = <0x0 0x40053000 0x0 0x1000>;
interrupts = <0 59 4>;
};
[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM

48
Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml Normal file
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@ -0,0 +1,48 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/fsl,s32-linflexuart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale LINFlexD UART
description: |
The LINFlexD controller implements several LIN protocol versions, as well
as support for full-duplex UART communication through 8-bit and 9-bit
frames. See chapter 47 ("LINFlexD") in the reference manual
https://www.nxp.com/webapp/Download?colCode=S32V234RM.
maintainers:
- Chester Lin <clin@suse.com>
allOf:
- $ref: "serial.yaml"
properties:
compatible:
oneOf:
- const: fsl,s32v234-linflexuart
- items:
- const: nxp,s32g2-linflexuart
- const: fsl,s32v234-linflexuart
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
serial@40053000 {
compatible = "fsl,s32v234-linflexuart";
reg = <0x40053000 0x1000>;
interrupts = <0 59 4>;
};

94
Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml Normal file
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@ -0,0 +1,94 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MM DISP blk-ctrl
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
description:
The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
the NoC and ensuring proper power sequencing of the display and MIPI CSI
peripherals located in the DISP domain of the SoC.
properties:
compatible:
items:
- const: fsl,imx8mm-disp-blk-ctrl
- const: syscon
reg:
maxItems: 1
'#power-domain-cells':
const: 1
power-domains:
minItems: 5
maxItems: 5
power-domain-names:
items:
- const: bus
- const: csi-bridge
- const: lcdif
- const: mipi-dsi
- const: mipi-csi
clocks:
minItems: 10
maxItems: 10
clock-names:
items:
- const: csi-bridge-axi
- const: csi-bridge-apb
- const: csi-bridge-core
- const: lcdif-axi
- const: lcdif-apb
- const: lcdif-pix
- const: dsi-pclk
- const: dsi-ref
- const: csi-aclk
- const: csi-pclk
required:
- compatible
- reg
- power-domains
- power-domain-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/power/imx8mm-power.h>
disp_blk_ctl: blk_ctrl@32e28000 {
compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
<&pgc_mipi>, <&pgc_mipi>;
power-domain-names = "bus", "csi-bridge", "lcdif",
"mipi-dsi", "mipi-csi";
clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_CSI1_ROOT>,
<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_DISP_ROOT>,
<&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>,
<&clk IMX8MM_CLK_CSI1_CORE>,
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
"lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
"dsi-ref", "csi-aclk", "csi-pclk";
#power-domain-cells = <1>;
};

76
Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MM VPU blk-ctrl
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
description:
The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
the NoC and ensuring proper power sequencing of the VPU peripherals
located in the VPU domain of the SoC.
properties:
compatible:
items:
- const: fsl,imx8mm-vpu-blk-ctrl
- const: syscon
reg:
maxItems: 1
'#power-domain-cells':
const: 1
power-domains:
minItems: 4
maxItems: 4
power-domain-names:
items:
- const: bus
- const: g1
- const: g2
- const: h1
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: g1
- const: g2
- const: h1
required:
- compatible
- reg
- power-domains
- power-domain-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/power/imx8mm-power.h>
vpu_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
<&pgc_vpu_g2>, <&pgc_vpu_h1>;
power-domain-names = "bus", "g1", "g2", "h1";
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
<&clk IMX8MM_CLK_VPU_G2_ROOT>,
<&clk IMX8MM_CLK_VPU_H1_ROOT>;
clock-names = "g1", "g2", "h1";
#power-domain-cells = <1>;
};

3
Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
View File

@ -20,6 +20,9 @@ properties:
- const: allwinner,sun6i-a31-i2s
- const: allwinner,sun8i-a83t-i2s
- const: allwinner,sun8i-h3-i2s
- items:
- const: allwinner,sun8i-r40-i2s
- const: allwinner,sun8i-h3-i2s
- items:
- const: allwinner,sun8i-v3-i2s
- const: allwinner,sun8i-h3-i2s

10
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -193,6 +193,8 @@ patternProperties:
description: B&R Industrial Automation GmbH
"^bticino,.*":
description: Bticino International
"^calamp,.*":
description: CalAmp Corp.
"^calaosystems,.*":
description: CALAO Systems SAS
"^calxeda,.*":
@ -337,6 +339,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
"^edimax,.*":
description: EDIMAX Technology Co., Ltd
"^edt,.*":
description: Emerging Display Technologies
"^eeti,.*":
@ -397,6 +401,8 @@ patternProperties:
description: Exar Corporation
"^excito,.*":
description: Excito
"^exegin,.*":
description: Exegin Technologies Limited
"^ezchip,.*":
description: EZchip Semiconductor
"^facebook,.*":
@ -581,6 +587,8 @@ patternProperties:
description: JEDEC Solid State Technology Association
"^jesurun,.*":
description: Shenzhen Jesurun Electronics Business Dept.
"^jethome,.*":
description: JetHome (IP Sokolov P.A.)
"^jianda,.*":
description: Jiandangjing Technology Co., Ltd.
"^kam,.*":
@ -1108,6 +1116,8 @@ patternProperties:
description: SpinalHDL
"^sprd,.*":
description: Spreadtrum Communications Inc.
"^ssi,.*":
description: SSI Computer Corp
"^sst,.*":
description: Silicon Storage Technology, Inc.
"^sstar,.*":

1
MAINTAINERS
View File

@ -6352,6 +6352,7 @@ L: linux-tegra@vger.kernel.org
S: Supported
T: git git://anongit.freedesktop.org/tegra/linux.git
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
F: Documentation/devicetree/bindings/gpu/host1x/
F: drivers/gpu/drm/tegra/
F: drivers/gpu/host1x/
F: include/linux/host1x.h

26
arch/arm/boot/dts/Makefile
View File

@ -25,6 +25,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
usb_a9263.dtb \
at91-foxg20.dtb \
at91-kizbox.dtb \
at91-lmu5000.dtb \
at91sam9g20ek.dtb \
at91sam9g20ek_2mmc.dtb \
tny_a9g20.dtb \
@ -40,6 +41,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91-kizboxmini-base.dtb \
at91-kizboxmini-mb.dtb \
at91-kizboxmini-rd.dtb \
at91-q5xr5.dtb \
at91-smartkiz.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
@ -92,6 +94,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2711-rpi-cm4-io.dtb \
bcm2835-rpi-zero.dtb \
bcm2835-rpi-zero-w.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
@ -117,6 +120,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
bcm4709-tplink-archer-c9-v1.dtb \
bcm47094-asus-rt-ac88u.dtb \
bcm47094-dlink-dir-885l.dtb \
bcm47094-linksys-panamera.dtb \
bcm47094-luxul-abr-4500.dtb \
@ -157,6 +161,12 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
bcm958525xmc.dtb \
bcm958622hr.dtb \
bcm958623hr.dtb \
bcm958625-meraki-mx64.dtb \
bcm958625-meraki-mx64-a0.dtb \
bcm958625-meraki-mx64w.dtb \
bcm958625-meraki-mx64w-a0.dtb \
bcm958625-meraki-mx65.dtb \
bcm958625-meraki-mx65w.dtb \
bcm958625hr.dtb \
bcm988312hr.dtb \
bcm958625k.dtb
@ -219,9 +229,11 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-dlink-dir-685.dtb \
gemini-dlink-dns-313.dtb \
gemini-nas4220b.dtb \
gemini-ns2502.dtb \
gemini-rut1xx.dtb \
gemini-sl93512r.dtb \
gemini-sq201.dtb \
gemini-ssi1328.dtb \
gemini-wbd111.dtb \
gemini-wbd222.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
@ -635,10 +647,12 @@ dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-tolino-shine2hd.dtb \
imx6sl-tolino-shine3.dtb \
imx6sl-tolino-vision5.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb \
imx6sll-kobo-clarahd.dtb
imx6sll-kobo-clarahd.dtb \
imx6sll-kobo-librah2o.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
@ -671,6 +685,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
@ -939,6 +954,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \
ox810se-wd-mbwe.dtb \
ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8026-lg-lenok.dtb \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
@ -959,6 +975,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq8064-rb3011.dtb \
qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8916-samsung-serranove.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
@ -1075,6 +1092,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_mercury_aa1.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
@ -1113,6 +1131,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32h743i-eval.dtb \
stm32h743i-disco.dtb \
stm32h750i-art-pi.dtb \
stm32mp135f-dk.dtb \
stm32mp153c-dhcom-drc02.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157a-dhcor-avenger96.dtb \
@ -1387,6 +1406,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-381-netgear-gs110emx.dtb \
armada-382-rd-ac3x-48g4x2xl.dtb \
armada-385-atl-x530.dtb\
armada-385-clearfog-gtr-s4.dtb \
@ -1497,4 +1517,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
aspeed-bmc-quanta-q71l.dtb \
aspeed-bmc-supermicro-x11spi.dtb
aspeed-bmc-supermicro-x11spi.dtb \
aspeed-bmc-inventec-transformers.dtb \
aspeed-bmc-tyan-s7106.dtb

1
arch/arm/boot/dts/am335x-pocketbeagle.dts
View File

@ -205,6 +205,7 @@
&am33xx_pinmux {
compatible = "pinconf-single";
pinctrl-names = "default";
pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio

42
arch/arm/boot/dts/arm-realview-eb.dtsi
View File

@ -198,96 +198,112 @@
syscon: syscon@10000000 {
compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;

42
arch/arm/boot/dts/arm-realview-pb1176.dts
View File

@ -216,96 +216,112 @@
syscon: syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;

48
arch/arm/boot/dts/arm-realview-pb11mp.dts
View File

@ -303,114 +303,132 @@
pb11mp_syscon: syscon@10000000 {
compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
linux,default-trigger = "cpu1";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
linux,default-trigger = "cpu2";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
linux,default-trigger = "cpu3";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;
clocks = <&xtal24mhz>;
};
oscclk5: osc5@d4 {
oscclk5: clock-controller@d4 {
compatible = "arm,syscon-icst307";
reg = <0xd4 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd4>;
clocks = <&xtal24mhz>;
};
oscclk6: osc6@d8 {
oscclk6: clock-controller@d8 {
compatible = "arm,syscon-icst307";
reg = <0xd8 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd8>;

42
arch/arm/boot/dts/arm-realview-pbx.dtsi
View File

@ -220,96 +220,112 @@
syscon: syscon@10000000 {
compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;

295
arch/arm/boot/dts/armada-381-netgear-gs110emx.dts Normal file
View File

@ -0,0 +1,295 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Netgear GS110EMX";
compatible = "netgear,gs110emx", "marvell,armada380";
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&front_button_pins>;
pinctrl-names = "default";
factory_default {
label = "Factory Default";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>; /* 128 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
rtc@a3800 {
/*
* If the rtc doesn't work, run "date reset"
* twice in u-boot.
*/
status = "okay";
};
};
};
};
&eth0 {
/* ethernet@70000 */
bm,pool-long = <0>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
phy-mode = "rgmii-id";
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
fixed-link {
full-duplex;
pause;
speed = <1000>;
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
switch@0 {
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&switch_interrupt_pins>;
pinctrl-names = "default";
#size-cells = <0>;
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
mdio-external {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@b {
reg = <0xb>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy2: ethernet-phy@c {
reg = <0xc>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
ethernet = <&eth0>;
label = "cpu";
reg = <0>;
fixed-link {
full-duplex;
pause;
speed = <1000>;
};
};
port@1 {
label = "lan1";
phy-handle = <&switch0phy1>;
reg = <1>;
};
port@2 {
label = "lan2";
phy-handle = <&switch0phy2>;
reg = <2>;
};
port@3 {
label = "lan3";
phy-handle = <&switch0phy3>;
reg = <3>;
};
port@4 {
label = "lan4";
phy-handle = <&switch0phy4>;
reg = <4>;
};
port@5 {
label = "lan5";
phy-handle = <&switch0phy5>;
reg = <5>;
};
port@6 {
label = "lan6";
phy-handle = <&switch0phy6>;
reg = <6>;
};
port@7 {
label = "lan7";
phy-handle = <&switch0phy7>;
reg = <7>;
};
port@8 {
label = "lan8";
phy-handle = <&switch0phy8>;
reg = <8>;
};
port@9 {
/* 88X3310P external phy */
label = "lan9";
phy-handle = <&phy1>;
phy-mode = "xaui";
reg = <9>;
};
port@a {
/* 88X3310P external phy */
label = "lan10";
phy-handle = <&phy2>;
phy-mode = "xaui";
reg = <0xa>;
};
};
};
};
&pinctrl {
front_button_pins: front-button-pins {
marvell,pins = "mpp38";
marvell,function = "gpio";
};
switch_interrupt_pins: switch-interrupt-pins {
marvell,pins = "mpp39";
marvell,function = "gpio";
};
};
&spi0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
read-only;
reg = <0x00000000 0x00100000>;
};
partition@100000 {
label = "env";
reg = <0x00100000 0x00010000>;
};
partition@200000 {
label = "rsv";
reg = <0x00110000 0x00010000>;
};
partition@300000 {
label = "image0";
reg = <0x00120000 0x00900000>;
};
partition@400000 {
label = "config";
reg = <0x00a20000 0x00300000>;
};
partition@480000 {
label = "debug";
reg = <0x00d20000 0x002e0000>;
};
};
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};

5
arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
View File

@ -159,6 +159,11 @@
//24LC128 EEPROM
&i2c3 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
pagesize = <64>;
};
};
//P0 Power regulators

21
arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
View File

@ -86,6 +86,18 @@
linux,code = <ASPEED_GPIO(J, 1)>;
};
S0_scp_auth_fail {
label = "S0_SCP_AUTH_FAIL";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
S1_scp_auth_fail {
label = "S1_SCP_AUTH_FAIL";
gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 5)>;
};
S1_overtemp {
label = "S1_OVERTEMP";
gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
@ -590,7 +602,7 @@
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
/*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
"OCP_MAIN_PWREN","RESET_BUTTON","","",
/*S0-S7*/ "","","","","","","","",
/*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
@ -604,4 +616,11 @@
"S1_BMC_DDR_ADR","","","","",
/*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
"BMC_OCP_PG";
i2c4_o_en {
gpio-hog;
gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_I2C4_O_EN";
};
};

875
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
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File diff suppressed because it is too large Load Diff

1227
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
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File diff suppressed because it is too large Load Diff

9
arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
View File

@ -3,6 +3,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "FP5280G2 BMC";
@ -245,7 +246,7 @@
label = "bmc";
m25p,fast-read;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
#include "openbmc-flash-layout-64.dtsi"
};
};
@ -902,4 +903,10 @@
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
#include "ibm-power9-dual.dtsi"

328
arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts Normal file
View File

@ -0,0 +1,328 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2021 Inventec Corp.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include "aspeed-g6-pinctrl.dtsi"
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "TRANSFORMERS BMC";
compatible = "inventec,transformer-bmc", "aspeed,ast2600";
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
leds {
compatible = "gpio-leds";
// UID led
uid {
label = "UID_LED";
gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
};
// Heart beat led
heartbeat {
label = "HB_LED";
gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
};
};
};
&mdio0 {
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mac3 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii4_default>;
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <33000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
#include "openbmc-flash-layout.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
spi-max-frequency = <33000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "bios";
spi-max-frequency = <33000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&wdt1 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart5 {
status = "okay";
};
&i2c0 {
status = "okay";
//Set bmc' slave address;
bmc_slave@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c2 {
status = "okay";
};
&i2c3 {
// FRU AT24C512C-SSHM-T
status = "okay";
eeprom@50 {
compatible = "atmel,24c512";
reg = <0x50>;
pagesize = <128>;
};
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
tmp75@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
tmp75@4f {
compatible = "ti,tmp75";
reg = <0x4f>;
};
tmp468@48 {
compatible = "ti,tmp468";
reg = <0x48>;
};
};
&i2c7 {
status = "okay";
adm1278@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c8 {
// FRU AT24C512C-SSHM-T
status = "okay";
eeprom@51 {
compatible = "atmel,24c512";
reg = <0x51>;
pagesize = <128>;
};
eeprom@53 {
compatible = "atmel,24c512";
reg = <0x53>;
pagesize = <128>;
};
};
&i2c9 {
// M.2
status = "okay";
};
&i2c10 {
// I2C EXPANDER
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
};
i2c-switch@73 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
};
};
&i2c11 {
// I2C EXPANDER
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
pcie_eeprom_riser1: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
eeprom@55 {
compatible = "atmel,24c512";
reg = <0x55>;
pagesize = <128>;
};
};
pcie_eeprom_riser2: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
eeprom@55 {
compatible = "atmel,24c512";
reg = <0x55>;
pagesize = <128>;
};
};
pcie_eeprom_riser3: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@55 {
compatible = "atmel,24c512";
reg = <0x55>;
pagesize = <128>;
};
};
};
};
&i2c12 {
status = "okay";
psu0:psu0@58 {
compatible = "pmbus";
reg = <0x58>;
};
};
&gpio0 {
status = "okay";
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
/*B0-B7*/ "presence-ps0","power-chassis-good","","","","","presence-ps1","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "","","","","power-chassis-control","","","",
/*G0-G7*/ "","","jtag-mux","","","","","",
/*H0-H7*/ "","","","","reset-button","power-button","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","tck-mux","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","nmi-button","","","","","","",
/*V0-V7*/ "","","","","power-config-full-load","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&emmc_controller {
status = "okay";
};
&emmc {
status = "okay";
non-removable;
max-frequency = <52000000>;
bus-width = <8>;
};
&vhub {
status = "okay";
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
};
&rtc {
status = "okay";
};

488
arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts Normal file
View File

@ -0,0 +1,488 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Tyan S7106 BMC";
compatible = "tyan,s7106-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
p2a_memory: region@987f0000 {
no-map;
reg = <0x987f0000 0x00010000>; /* 64KB */
};
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0x9f000000 0x01000000>; /* 16M */
};
gfx_memory: framebuffer {
size = <0x01000000>; /* 16M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
leds {
compatible = "gpio-leds";
identify {
gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
};
heartbeat {
gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 12>, <&adc 13>, <&adc 14>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 15>;
};
};
&fmc {
status = "okay";
flash@0 {
label = "bmc";
status = "okay";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
};
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart2 {
/* RS-232 connector on header */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default
&pinctrl_rxd2_default>;
};
&uart3 {
/* Alternative to vuart to internally connect (route) to uart1
* when vuart cannot be used due to BIOS limitations.
*/
status = "okay";
};
&uart4 {
/* Alternative to vuart to internally connect (route) to the
* external port usually used by uart1 when vuart cannot be
* used due to BIOS limitations.
*/
status = "okay";
};
&uart5 {
/* BMC "debug" (console) UART; connected to RS-232 connector
* on header; selectable via jumpers as alternative to uart2
*/
status = "okay";
};
&vuart {
status = "okay";
};
&lpc_ctrl {
status = "okay";
};
&p2a {
status = "okay";
memory-region = <&p2a_memory>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&adc {
status = "okay";
};
&vhub {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm3_default
&pinctrl_pwm4_default>;
/* CPU fan #0 */
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
/* CPU fan #1 */
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
/* PWM group for chassis fans #1, #2, #3 and #4 */
fan@2 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
/* PWM group for chassis fans #5 and #6 */
fan@6 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
};
&i2c0 {
status = "okay";
/* Hardware monitor with temperature sensors */
nct7802@28 {
compatible = "nuvoton,nct7802";
reg = <0x28>;
};
/* Also connected to:
* - IPMB pin header
* - CPU #0 memory error LED @ 0x3A
* - CPU #1 memory error LED @ 0x3C
*/
};
&i2c1 {
/* Directly connected to PCH SMBUS #0 */
status = "okay";
};
&i2c2 {
status = "okay";
/* BMC EEPROM, incl. mainboard FRU */
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
/* Also connected to:
* - fan header
* - mini-SAS HD connector
* - SSATA SGPIO
* - via switch (BMC_SMB3_PCH_IE_SML3_EN, active low)
* to PCH SMBUS #3
*/
};
&i2c3 {
status = "okay";
/* PSU1 FRU @ 0xA0 */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
/* PSU2 FRU @ 0xA2 */
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* PSU1 @ 0xB0 */
power-supply@58 {
compatible = "pmbus";
reg = <0x58>;
};
/* PSU2 @ 0xB2 */
power-supply@59 {
compatible = "pmbus";
reg = <0x59>;
};
/* Also connected to:
* - PCH SMBUS #1
*/
};
&i2c4 {
status = "okay";
/* Connected to:
* - PCH SMBUS #2
*/
/* Connected via switch to:
* - CPU #0 channels ABC VDDQ @ 0x80
* - CPU #0 channels DEF VDDQ @ 0x81
* - CPU #1 channels ABC VDDQ @ 0x82
* - CPU #1 channels DEF VDDQ @ 0x83
* - CPU #0 VCCIO & VMCP @ 0x52
* - CPU #1 VCCIO & VMCP @ 0x53
* - CPU #0 VCCIN @ 0xC0
* - CPU #0 VSA @ 0xC2
* - CPU #1 VCCIN @ 0xC4
* - CPU #1 VSA @ 0xC6
* - J110
*/
};
&i2c5 {
status = "okay";
/* Connected via switch (PCH_BMC_SMB_SW_P) to:
* - mainboard FRU @ 0xAE
* - XDP connector
* - ME debug header
* - clock buffer @ 0xD8
* - i2c4 via switch (PCH_VR_SMBUS_SW_P; controlled by PCH)
* - PCH SMBUS
*/
};
&i2c6 {
status = "okay";
/* Connected via switch (BMC_PE_SMB_EN_1_N) to
* bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
* - 0,0: PCIE slot 1, SMB #1
* - 0,1: PCIE slot 1, SMB #2
* - 1,0: PCIE slot 2, SMB #1
* - 1,1: PCIE slot 2, SMB #2
*/
/* Connected via switch (BMC_PE_SMB_EN_2_N) to
* bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
* - 0,0: OCP0 (A) SMB
* - 0,1: OCP0 (C) SMB
* - 1,0: OCP1 (A) SMB
* - 1,1: NC
*/
};
&i2c7 {
status = "okay";
/* Connected to:
* - PCH SMBUS #4
*/
};
&i2c8 {
status = "okay";
/* Not connected */
};
&mac0 {
status = "okay";
use-ncsi;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&ibt {
status = "okay";
};
&kcs1 {
status = "okay";
aspeed,lpc-io-reg = <0xca8>;
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
};
/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
};
/* We're following the GPIO naming as defined at
* https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md.
*
* Notes on led-identify and id-button:
* - A physical button is connected to id-button which
* triggers the clock on a D flip-flop. The /Q output of the
* flip-flop drives its D input.
* - The flip-flop's Q output drives led-identify which is
* connected to LEDs.
* - With that, every button press toggles the LED between on and off.
*
* Notes on power-, reset- and nmi- button and control:
* - The -button signals can be used to monitor physical buttons.
* - The -control signals can be used to actuate the specific
* operation.
* - In hardware, the -button signals are connected to the -control
* signals through drivers with the -control signals being
* protected through diodes.
*/
&gpio {
status = "okay";
gpio-line-names =
/*A0*/ "",
/*A1*/ "",
/*A2*/ "led-identify", /* in/out: BMC_IDLED_ON_N */
/*A3*/ "",
/*A4*/ "",
/*A5*/ "",
/*A6*/ "",
/*A7*/ "",
/*B0-B7*/ "","","","","","","","",
/*C0*/ "",
/*C1*/ "",
/*C2*/ "",
/*C3*/ "",
/*C4*/ "id-button", /* in/out: BMC_IDBTN_IN_OUT_N */
/*C5*/ "post-complete", /* in: FM_BIOS_POST_CMPLT_N */
/*C6*/ "",
/*C7*/ "",
/*D0*/ "",
/*D1*/ "",
/*D2*/ "power-chassis-good", /* in: SYS_PWROK_BUF */
/*D3*/ "platform-reset", /* in: SYS_PLTRST_N */
/*D4*/ "",
/*D5*/ "",
/*D6*/ "",
/*D7*/ "",
/*E0*/ "power-button", /* in: BMC_PWBTN_IN_N */
/*E1*/ "power-chassis-control", /* out: BMC_PWRBTN_OUT_N */
/*E2*/ "reset-button", /* in: BMC_RSTBTN_IN_N */
/*E3*/ "reset-control", /* out: BMC_RSTBTN_OUT_N */
/*E4*/ "nmi-button", /* in: BMC_NMIBTN_IN_N */
/*E5*/ "nmi-control", /* out: BMC_NMIBTN_OUT_N */
/*E6*/ "",
/*E7*/ "led-heartbeat", /* out: BMC_HEARTBRAT_LED_N */
/*F0*/ "",
/*F1*/ "clear-cmos-control", /* out: BMC_CLR_CMOS_N */
/*F2*/ "",
/*F3*/ "",
/*F4*/ "led-fault", /* out: AST_HW_FAULT_N */
/*F5*/ "",
/*F6*/ "",
/*F7*/ "",
/*G0*/ "BMC_PE_SMB_EN_1_N", /* out */
/*G1*/ "BMC_PE_SMB_EN_2_N", /* out */
/*G2*/ "",
/*G3*/ "",
/*G4*/ "",
/*G5*/ "",
/*G6*/ "",
/*G7*/ "",
/*H0-H7*/ "","","","","","","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0*/ "",
/*Q1*/ "",
/*Q2*/ "",
/*Q3*/ "",
/*Q4*/ "BMC_PE_SMB_SW_BIT0", /* out */
/*Q5*/ "BMC_PE_SMB_SW_BIT1", /* out */
/*Q6*/ "",
/*Q7*/ "",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0*/ "",
/*AA1*/ "",
/*AA2*/ "",
/*AA3*/ "BMC_SMB3_PCH_IE_SML3_EN", /* out */
/*AA4*/ "",
/*AA5*/ "",
/*AA6*/ "",
/*AA7*/ "",
/*AB0-AB7*/ "","","","","","","","";
};

6
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -383,6 +383,12 @@
interrupts = <8>;
status = "disabled";
};
uart_routing: uart-routing@9c {
compatible = "aspeed,ast2400-uart-routing";
reg = <0x9c 0x4>;
status = "disabled";
};
};
uart2: serial@1e78d000 {

6
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -491,6 +491,12 @@
#reset-cells = <1>;
};
uart_routing: uart-routing@9c {
compatible = "aspeed,ast2500-uart-routing";
reg = <0x9c 0x4>;
status = "disabled";
};
lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
reg = <0xa0 0x24 0xc8 0x8>;

26
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -364,6 +364,26 @@
status = "disabled";
};
adc0: adc@1e6e9000 {
compatible = "aspeed,ast2600-adc0";
reg = <0x1e6e9000 0x100>;
clocks = <&syscon ASPEED_CLK_APB2>;
resets = <&syscon ASPEED_RESET_ADC>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
status = "disabled";
};
adc1: adc@1e6e9100 {
compatible = "aspeed,ast2600-adc1";
reg = <0x1e6e9100 0x100>;
clocks = <&syscon ASPEED_CLK_APB2>;
resets = <&syscon ASPEED_RESET_ADC>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
status = "disabled";
};
gpio0: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
@ -551,6 +571,12 @@
#reset-cells = <1>;
};
uart_routing: uart-routing@98 {
compatible = "aspeed,ast2600-uart-routing";
reg = <0x98 0x8>;
status = "disabled";
};
ibt: ibt@140 {
compatible = "aspeed,ast2600-ibt-bmc";
reg = <0x140 0x18>;

147
arch/arm/boot/dts/at91-lmu5000.dts Normal file
View File

@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree file for CalAmp LMU5000 board
*
* Copyright (C) 2013 Adam Porter <porter.adam@gmail.com>
*/
/dts-v1/;
#include "at91sam9g20.dtsi"
/ {
model = "CalAmp LMU5000";
compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
};
};
&dbgu {
status = "okay";
};
&ebi {
status = "okay";
nand_controller: nand-controller {
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
kernel@0 {
label = "kernel";
reg = <0x0 0x400000>;
};
rootfs@400000 {
label = "rootfs";
reg = <0x400000 0x3C00000>;
};
user1@4000000 {
label = "user1";
reg = <0x4000000 0x2000000>;
};
user2@6000000 {
label = "user2";
reg = <0x6000000 0x2000000>;
};
};
};
};
};
&macb0 {
phy-mode = "mii";
status = "okay";
};
&pinctrl {
board {
pinctrl_pck0_as_mck: pck0_as_mck {
atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
usb0 {
pinctrl_usb1_vbus_gpio: usb0_vbus_gpio {
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
&ssc0 {
status = "okay";
pinctrl-0 = <&pinctrl_ssc0_tx>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usart0 {
pinctrl-0 =
<&pinctrl_usart0
&pinctrl_usart0_rts
&pinctrl_usart0_cts
&pinctrl_usart0_dtr_dsr
&pinctrl_usart0_dcd
&pinctrl_usart0_ri>;
status = "okay";
};
&usart2 {
status = "okay";
};
&usb0 {
num-ports = <2>;
status = "okay";
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&watchdog {
status = "okay";
};

199
arch/arm/boot/dts/at91-q5xr5.dts Normal file
View File

@ -0,0 +1,199 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree file for Exegin Q5xR5 board
*
* Copyright (C) 2014 Owen Kirby <osk@exegin.com>
*/
/dts-v1/;
#include "at91sam9g20.dtsi"
/ {
model = "Exegin Q5x (rev5)";
compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2";
};
memory {
reg = <0x20000000 0x0>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <18432000>;
};
};
};
&dbgu {
status = "okay";
};
&ebi {
status = "okay";
flash: flash@0 {
compatible = "cfi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x1000000 0x800000>;
bank-width = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
kernel@0 {
label = "kernel";
reg = <0x0 0x200000>;
};
rootfs@200000 {
label = "rootfs";
reg = <0x200000 0x600000>;
};
};
};
};
&macb0 {
phy-mode = "mii";
status = "okay";
};
&pinctrl {
board {
pinctrl_pck0_as_mck: pck0_as_mck {
atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
spi0 {
pinctrl_spi0: spi0-0 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi0_npcs0: spi0_npcs0 {
atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi0_npcs1: spi0_npcs1 {
atmel,pins = <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
spi1 {
pinctrl_spi1: spi1-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi1_npcs0: spi1_npcs0 {
atmel,pins = <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi1_npcs1: spi1_npcs1 {
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>;
cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
status = "okay";
m25p80@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
at91boot@0 {
label = "at91boot";
reg = <0x0 0x4000>;
};
uenv@4000 {
label = "uboot-env";
reg = <0x4000 0x4000>;
};
uboot@8000 {
label = "uboot";
reg = <0x8000 0x3E000>;
};
};
spidev@1 {
compatible = "spidev";
spi-max-frequency = <2000000>;
reg = <1>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>;
cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>;
status = "okay";
spidev@0 {
compatible = "spidev";
spi-max-frequency = <2000000>;
reg = <0>;
};
spidev@1 {
compatible = "spidev";
spi-max-frequency = <2000000>;
reg = <1>;
};
};
&usart0 {
pinctrl-0 =
<&pinctrl_usart0
&pinctrl_usart0_rts
&pinctrl_usart0_cts
&pinctrl_usart0_dtr_dsr
&pinctrl_usart0_dcd
&pinctrl_usart0_ri>;
status = "okay";
};
&usb0 {
num-ports = <2>;
status = "okay";
};
&usb1 {
status = "okay";
};
&watchdog {
status = "okay";
};

12
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
View File

@ -8,6 +8,7 @@
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Atmel SAMA5D27 SoM1";
@ -95,8 +96,11 @@
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
at24@50 {
@ -113,6 +117,12 @@
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_qspi1_default: qspi1_default {
sck_cs {
pinmux = <PIN_PB5__QSPI1_SCK>,

23
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -130,8 +130,11 @@
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
sda-gpios = <&pioA PIN_PA24 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PA23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
};
@ -215,8 +218,11 @@
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -252,6 +258,13 @@
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD4__GPIO>,
<PIN_PD5__GPIO>;
bias-disable;
};
pinctrl_isc_base: isc_base {
pinmux = <PIN_PC21__ISC_PCK>,
<PIN_PC22__ISC_VSYNC>,
@ -441,6 +454,12 @@
bias-disable;
};
pinctrl_i2c3_gpio: i2c3_gpio {
pinmux = <PIN_PA24__GPIO>,
<PIN_PA23__GPIO>;
bias-disable;
};
pinctrl_flx4_default: flx4_uart_default {
pinmux = <PIN_PC28__FLEXCOM4_IO0>,
<PIN_PC29__FLEXCOM4_IO1>,

70
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
View File

@ -30,6 +30,14 @@
clock-frequency = <24000000>;
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-wilc1000";
reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_wilc_pwrseq>;
pinctrl-names = "default";
};
};
&flx1 {
@ -310,5 +318,67 @@
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
pinctrl_sdmmc1_default: sdmmc1_default {
cmd-data {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-disable;
};
conf-ck {
pinmux = <PIN_PA22__SDMMC1_CK>;
bias-disable;
};
};
pinctrl_wilc_default: wilc_default {
conf-irq {
pinmux = <PIN_PB25__GPIO>;
bias-disable;
};
};
pinctrl_wilc_pwrseq: wilc_pwrseq {
conf-ce-nrst {
pinmux = <PIN_PA27__GPIO>,
<PIN_PA29__GPIO>;
bias-disable;
};
conf-rtcclk {
pinmux = <PIN_PB13__PCK1>;
bias-disable;
};
};
};
&sdmmc1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
mmc-pwrseq = <&wifi_pwrseq>;
no-1-8-v;
non-removable;
bus-width = <4>;
status = "okay";
wilc: wifi@0 {
reg = <0>;
compatible = "microchip,wilc1000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wilc_default>;
clocks = <&pmc PMC_TYPE_SYSTEM 9>;
clock-names = "rtc";
interrupts = <PIN_PB25 IRQ_TYPE_NONE>;
interrupt-parent = <&pioA>;
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
assigned-clock-rates = <32768>;
};
};

22
arch/arm/boot/dts/at91-sama5d2_icp.dts
View File

@ -307,8 +307,11 @@
};
&i2c0 { /* mikrobus i2c */
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@ -316,8 +319,11 @@
&i2c1 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@ -402,6 +408,12 @@
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD19__GPIO>,
<PIN_PD20__GPIO>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PD0__GPIO>;
bias-pull-up;
@ -463,6 +475,12 @@
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_mikrobus1_an: mikrobus1_an {
pinmux = <PIN_PD26__GPIO>;
bias-disable;

20
arch/arm/boot/dts/at91-sama7g5ek.dts
View File

@ -122,6 +122,14 @@
};
};
&adc {
vddana-supply = <&vddout25>;
vref-supply = <&vddout25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
};
@ -679,6 +687,18 @@
status = "okay";
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&trng {
status = "okay";
};

2
arch/arm/boot/dts/at91-tse850-3.dts
View File

@ -262,7 +262,7 @@
&macb1 {
status = "okay";
phy-mode = "rgmii";
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -166,7 +166,7 @@
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
pinctrl@fffff400 {
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";

6
arch/arm/boot/dts/axp209.dtsi
View File

@ -53,7 +53,7 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp202-ac-power-supply";
status = "disabled";
};
@ -69,7 +69,7 @@
#gpio-cells = <2>;
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp209-battery-power-supply";
status = "disabled";
};
@ -112,7 +112,7 @@
};
};
usb_power_supply: usb-power-supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp202-usb-power-supply";
status = "disabled";
};

6
arch/arm/boot/dts/axp22x.dtsi
View File

@ -52,7 +52,7 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp221-ac-power-supply";
status = "disabled";
};
@ -62,7 +62,7 @@
#io-channel-cells = <1>;
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
};
@ -163,7 +163,7 @@
};
};
usb_power_supply: usb_power_supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp221-usb-power-supply";
status = "disabled";
};

10
arch/arm/boot/dts/axp81x.dtsi
View File

@ -48,7 +48,7 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp813-ac-power-supply";
status = "disabled";
};
@ -63,18 +63,18 @@
gpio-controller;
#gpio-cells = <2>;
gpio0_ldo: gpio0-ldo {
gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo {
gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp813-battery-power-supply";
status = "disabled";
};
@ -172,7 +172,7 @@
};
};
usb_power_supply: usb-power-supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp813-usb-power-supply";
};
};

70
arch/arm/boot/dts/bcm-nsp-ax.dtsi Normal file
View File

@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom Northstar Plus Ax stepping-specific bindings.
* Notable differences from B0+ are the secondary-boot-reg and
* lack of DMA coherency.
*/
&cpu1 {
secondary-boot-reg = <0xffff042c>;
};
&dma {
/delete-property/ dma-coherent;
};
&sdio {
/delete-property/ dma-coherent;
};
&amac0 {
/delete-property/ dma-coherent;
};
&amac1 {
/delete-property/ dma-coherent;
};
&amac2 {
/delete-property/ dma-coherent;
};
&ehci0 {
/delete-property/ dma-coherent;
};
&mailbox {
/delete-property/ dma-coherent;
};
&xhci {
/delete-property/ dma-coherent;
};
&ehci0 {
/delete-property/ dma-coherent;
};
&ohci0 {
/delete-property/ dma-coherent;
};
&i2c0 {
/delete-property/ dma-coherent;
};
&sata {
/delete-property/ dma-coherent;
};
&pcie0 {
/delete-property/ dma-coherent;
};
&pcie1 {
/delete-property/ dma-coherent;
};
&pcie2 {
/delete-property/ dma-coherent;
};

52
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -77,7 +77,7 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
mpcore@19000000 {
mpcore-bus@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
@ -166,7 +166,7 @@
};
};
axi@18000000 {
axi: axi@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x0011c40c>;
#address-cells = <1>;
@ -219,7 +219,7 @@
status = "disabled";
};
sdio: sdhci@21000 {
sdio: mmc@21000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x21000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
@ -310,6 +310,7 @@
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
xhci: usb@29000 {
@ -362,6 +363,42 @@
status = "disabled";
};
mdio: mdio@32000 {
compatible = "brcm,iproc-mdio";
reg = <0x32000 0x8>;
#size-cells = <0>;
#address-cells = <1>;
};
mdio-mux@32000 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
reg = <0x32000 0x4>;
mux-mask = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
mdio_int: mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
usb3_phy: usb3-phy@10 {
compatible = "brcm,ns-bx-usb3-phy";
reg = <0x10>;
usb3-dmp-syscon = <&usb3_dmp>;
#phy-cells = <0>;
status = "disabled";
};
};
mdio_ext: mdio@200 {
reg = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
};
};
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
@ -520,13 +557,8 @@
};
};
usb3_phy: usb3-phy@104000 {
compatible = "brcm,ns-bx-usb3-phy";
reg = <0x104000 0x1000>,
<0x032000 0x1000>;
reg-names = "dmp", "ccb-mii";
#phy-cells = <0>;
status = "disabled";
usb3_dmp: syscon@104000 {
reg = <0x104000 0x1000>;
};
};

38
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -3,6 +3,7 @@
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
@ -26,11 +27,6 @@
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
@ -56,6 +52,10 @@
};
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&ddc0 {
status = "okay";
};
@ -178,23 +178,6 @@
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* EMMC2 is used to drive the SD card */
&emmc2 {
vqmmc-supply = <&sd_io_1v8_reg>;
@ -237,13 +220,6 @@
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -260,3 +236,7 @@
&vec {
status = "disabled";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};

138
arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts Normal file
View File

@ -0,0 +1,138 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711-rpi-cm4.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
model = "Raspberry Pi Compute Module 4 IO Board";
leds {
led-act {
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};
&ddc0 {
status = "okay";
};
&ddc1 {
status = "okay";
};
&gpio {
/*
* Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
* the official GPU firmware DT blob.
*
* Legend:
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"RGMII_MDIO",
"RGMIO_MDC",
/* Used by BT module */
"CTS0",
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
/* Shared with SPI flash */
"PWM0_MISO",
"PWM1_MOSI",
"STATUS_LED_G_CLK",
"SPIFLASH_CE_N",
"SDA0",
"SCL0",
"RGMII_RXCLK",
"RGMII_RXCTL",
"RGMII_RXD0",
"RGMII_RXD1",
"RGMII_RXD2",
"RGMII_RXD3",
"RGMII_TXCLK",
"RGMII_TXCTL",
"RGMII_TXD0",
"RGMII_TXD1",
"RGMII_TXD2",
"RGMII_TXD3";
};
&hdmi0 {
status = "okay";
};
&hdmi1 {
status = "okay";
};
&genet {
status = "okay";
};
&pixelvalve0 {
status = "okay";
};
&pixelvalve1 {
status = "okay";
};
&pixelvalve2 {
status = "okay";
};
&pixelvalve4 {
status = "okay";
};
&vc4 {
status = "okay";
};
&vec {
status = "disabled";
};

113
arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi Normal file
View File

@ -0,0 +1,113 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,4-compute-module", "brcm,bcm2711";
chosen {
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-settling-time-us = <5000>;
gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1>,
<3300000 0x0>;
status = "okay";
};
sd_vcc_reg: sd_vcc_reg {
compatible = "regulator-fixed";
regulator-name = "vcc-sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
};
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
/* EMMC2 is used to drive the eMMC */
&emmc2 {
bus-width = <8>;
vqmmc-supply = <&sd_io_1v8_reg>;
vmmc-supply = <&sd_vcc_reg>;
broken-cd;
/* Even the IP block is limited to 100 MHz
* this provides a throughput gain
*/
mmc-hs200-1_8v;
status = "okay";
};
&expgpio {
gpio-line-names = "BT_ON",
"WL_ON",
"PWR_LED_OFF",
"ANT1",
"VDD_SD_IO_SEL",
"CAM_GPIO",
"SD_PWR_ON",
"ANT2";
ant1: ant1-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_HIGH>;
/* internal antenna enabled */
output-high;
line-name = "ant1";
};
ant2: ant2-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
/* external antenna disabled */
output-low;
line-name = "ant2";
};
};
&genet {
phy-handle = <&phy1>;
phy-mode = "rgmii-rxid";
status = "okay";
};
&genet_mdio {
phy1: ethernet-phy@0 {
/* No PHY interrupt */
reg = <0x0>;
};
};
/* uart0 communicates with the BT module */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
};
/* uart1 is mapped to the pin header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};

31
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
View File

@ -7,6 +7,7 @@
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
@ -27,11 +28,10 @@
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};
&bt {
shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
};
&gpio {
@ -110,19 +110,7 @@
};
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&sdhost {
@ -135,13 +123,6 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
};
};
&uart1 {
@ -149,3 +130,7 @@
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
&wifi_pwrseq {
reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};

36
arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
View File

@ -3,6 +3,7 @@
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
@ -130,28 +131,6 @@
status = "okay";
};
/*
* SDHCI is used to control the SDIO for wireless
*
* WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
* by a single GPIO. We can't give GPIO control to one of the drivers,
* otherwise the other part would get unexpectedly disturbed.
*/
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@ -160,16 +139,15 @@
bus-width = <4>;
};
/* uart0 communicates with the BT module */
/* uart0 communicates with the BT module
*
* WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
* by a single GPIO. We can't give GPIO control to one of the drivers,
* otherwise the other part would get unexpectedly disturbed.
*/
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
};
};
/* uart1 is mapped to the pin header */

36
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
View File

@ -4,6 +4,7 @@
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-lan7515.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
@ -31,11 +32,10 @@
linux,default-trigger = "default-on";
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
@ -137,23 +137,6 @@
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@ -166,13 +149,6 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -181,3 +157,7 @@
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};

36
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
View File

@ -4,6 +4,7 @@
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
@ -24,11 +25,10 @@
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
@ -134,13 +134,6 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -150,23 +143,6 @@
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@ -174,3 +150,7 @@
status = "okay";
bus-width = <4>;
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};

34
arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi Normal file
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0
/ {
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
};
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* uart0 communicates with the BT module */
&uart0 {
status = "okay";
bt: bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
};
};

39
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View File

@ -20,7 +20,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
@ -94,3 +94,40 @@
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

37
arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
View File

@ -117,3 +117,40 @@
};
};
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

2
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
View File

@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

2
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
View File

@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;

2
arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
View File

@ -16,7 +16,7 @@
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

2
arch/arm/boot/dts/bcm4709-netgear-r7000.dts
View File

@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

44
arch/arm/boot/dts/bcm4709-netgear-r8000.dts
View File

@ -30,7 +30,7 @@
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;
@ -187,3 +187,45 @@
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@8 {
reg = <8>;
label = "cpu";
ethernet = <&gmac2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};

2
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
View File

@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

200
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts Normal file
View File

@ -0,0 +1,200 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>
*/
/dts-v1/;
#include "bcm47094.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
model = "Asus RT-AC88U";
chosen {
bootargs = "earlycon";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;
};
nvram@1c080000 {
compatible = "brcm,nvram";
reg = <0x1c080000 0x00180000>;
};
leds {
compatible = "gpio-leds";
power {
label = "white:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
wan-red {
label = "red:wan";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
lan {
label = "white:lan";
gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
};
usb2 {
label = "white:usb2";
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port2>;
linux,default-trigger = "usbport";
};
usb3 {
label = "white:usb3";
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port1>, <&xhci_port1>;
linux,default-trigger = "usbport";
};
wps {
label = "white:wps";
gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
};
reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
wifi {
label = "Wi-Fi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
};
led {
label = "Backlight";
linux,code = <KEY_BRIGHTNESS_ZERO>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
};
};
&srab {
compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab";
status = "okay";
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
sw0_p5: port@5 {
reg = <5>;
label = "extsw";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@7 {
reg = <7>;
ethernet = <&gmac1>;
label = "cpu";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@8 {
reg = <8>;
ethernet = <&gmac2>;
label = "cpu";
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&usb2 {
vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
&usb3_phy {
status = "okay";
};
&nandcs {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x00000000 0x00080000>;
read-only;
};
partition@80000 {
label = "nvram";
reg = <0x00080000 0x00180000>;
};
partition@200000 {
label = "firmware";
reg = <0x00200000 0x07e00000>;
compatible = "brcm,trx";
};
};
};

42
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
View File

@ -118,3 +118,45 @@
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@8 {
reg = <8>;
label = "cpu";
ethernet = <&gmac2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};

2
arch/arm/boot/dts/bcm47094-linksys-panamera.dts
View File

@ -129,7 +129,7 @@
};
};
mdio-bus-mux@18003000 {
mdio-mux@18003000 {
/* BIT(9) = 1 => external mdio */
mdio@200 {

37
arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
View File

@ -68,3 +68,40 @@
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

37
arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
View File

@ -68,3 +68,40 @@
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

2
arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
View File

@ -16,7 +16,7 @@
bootargs = "earlycon";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;

37
arch/arm/boot/dts/bcm47189-tenda-ac9.dts
View File

@ -105,3 +105,40 @@
};
};
};
&switch {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

35
arch/arm/boot/dts/bcm53016-meraki-mr32.dts
View File

@ -20,7 +20,7 @@
bootargs = " console=ttyS0,115200n8 earlycon";
};
memory {
memory@0 {
reg = <0x00000000 0x08000000>;
device_type = "memory";
};
@ -110,6 +110,12 @@
reg = <0x50>;
pagesize = <32>;
read-only;
#address-cells = <1>;
#size-cells = <1>;
mac_address: mac-address@66 {
reg = <0x66 0x6>;
};
};
};
};
@ -133,6 +139,11 @@
*/
};
&gmac0 {
nvmem-cell-names = "mac-address";
nvmem-cells = <&mac_address>;
};
&gmac1 {
status = "disabled";
};
@ -195,3 +206,25 @@
};
};
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "poe";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
fixed-link {
speed = <1000>;
duplex-full;
};
};
};
};

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