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clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks

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The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the
SoC. Update the definition of these clocks to allow this to be wired up
to the appropriate clock source.

Retain "xo" as the global named parent to make the change a nop in the
event that DT doesn't carry the necessary clocks definition.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20200106080546.3192125-2-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Bjorn Andersson 2020-01-06 00:05:45 -08:00 committed by Stephen Boyd
parent bcd63d222b
commit ab91f72e01
2 changed files with 38 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/clock/qcom,gcc.yaml
View File

@ -47,6 +47,11 @@ properties:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
#qcom,gcc-msm8996
- items:
- description: XO source
- description: Second XO source
- description: Sleep clock source
#qcom,gcc-msm8998
- items:
- description: Board XO source
@ -65,6 +70,11 @@ properties:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
#qcom,gcc-msm8996
- items:
- const: cxo
- const: cxo2
- const: sleep_clk
#qcom,gcc-msm8998
- items:
- const: xo

35
drivers/clk/qcom/gcc-msm8996.c
View File

@ -3046,7 +3046,10 @@ static struct clk_branch gcc_usb3_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -3060,7 +3063,10 @@ static struct clk_branch gcc_hdmi_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hdmi_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -3074,7 +3080,10 @@ static struct clk_branch gcc_edp_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_edp_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -3088,7 +3097,10 @@ static struct clk_branch gcc_ufs_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -3102,7 +3114,10 @@ static struct clk_branch gcc_pcie_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -3116,7 +3131,10 @@ static struct clk_branch gcc_rx2_usb2_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx2_usb2_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -3130,7 +3148,10 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx1_usb2_clkref_clk",
.parent_names = (const char *[]){ "xo" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "cxo2",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},