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MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.

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1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
周琰杰 (Zhou Yanjie) 2020-09-22 09:24:44 +08:00 committed by Thomas Bogendoerfer
parent a9fee3a513
commit a5ce852398
1 changed files with 2 additions and 0 deletions
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2
arch/mips/mm/sc-mips.c
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@ -228,6 +228,7 @@ static inline int __init mips_sc_probe(void)
* contradicted by all documentation.
*/
case MACH_INGENIC_JZ4770:
case MACH_INGENIC_JZ4775:
c->scache.ways = 4;
break;
@ -236,6 +237,7 @@ static inline int __init mips_sc_probe(void)
* but that is contradicted by all documentation.
*/
case MACH_INGENIC_X1000:
case MACH_INGENIC_X1000E:
c->scache.sets = 256;
c->scache.ways = 4;
break;