Merge branches 'clk-https', 'clk-renesas', 'clk-kconfig', 'clk-amlogic' and 'clk-imx' into clk-next
* clk-https: Replace HTTP links with HTTPS ones: Common CLK framework * clk-renesas: clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: renesas: Add r8a774e1 CPG Core Clock Definitions dt-bindings: power: Add r8a774e1 SYSC power domain definitions clk: renesas: rzg2: Mark RWDT clocks as critical clk: renesas: rcar-gen3: Mark RWDT clocks as critical clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot dt-bindings: clock: renesas: cpg: Convert to json-schema * clk-kconfig: clk: hsdk: Fix bad dependency on IOMEM clk: Specify IOMEM dependency for HSDK pll driver clk: Drop duplicate selection in Kconfig clk: AST2600: Add mux for EMMC clock clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER * clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs * clk-imx: clk: imx: vf610: add CAAM clock clk: imx8mp: add mu root clk
This commit is contained in:
Stephen Boyd
commit
987106e5f2
@ -9,7 +9,7 @@ specifier is an array of zero, one or more cells identifying the clock
|
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output on a device. The length of a clock specifier is defined by the
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value of a #clock-cells property in the clock provider node.
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[1] http://patchwork.ozlabs.org/patch/31551/
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[1] https://patchwork.ozlabs.org/patch/31551/
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==Clock providers==
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241
Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml
Normal file
241
Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml
Normal file
@ -0,0 +1,241 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Clock Pulse Generator (CPG)
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
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includes PLLs, and fixed and variable ratio dividers.
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The CPG may also provide a Clock Domain for SoC devices, in combination with
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the CPG Module Stop (MSTP) Clocks.
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properties:
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compatible:
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oneOf:
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- const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
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- const: renesas,r8a7740-cpg-clocks # R-Mobile A1
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- const: renesas,r8a7778-cpg-clocks # R-Car M1
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- const: renesas,r8a7779-cpg-clocks # R-Car H1
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- items:
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- enum:
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- renesas,r7s72100-cpg-clocks # RZ/A1H
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- const: renesas,rz-cpg-clocks # RZ/A1
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- const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
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reg:
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maxItems: 1
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clocks: true
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'#clock-cells':
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const: 1
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clock-output-names: true
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renesas,mode:
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description: Board-specific settings of the MD_CK* bits on R-Mobile A1
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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'#power-domain-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- clock-output-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a73a4-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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clock-output-names:
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items:
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- const: main
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- const: pll0
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- const: pll1
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- const: pll2
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- const: pll2s
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- const: pll2h
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- const: z
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- const: z2
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- const: i
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- const: m3
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- const: b
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- const: m1
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- const: m2
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- const: zx
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- const: zs
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- const: hp
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7740-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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- description: extalr
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clock-output-names:
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items:
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- const: system
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- const: pllc0
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- const: pllc1
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- const: pllc2
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- const: r
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- const: usb24s
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- const: i
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- const: zg
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- const: b
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- const: m1
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- const: hp
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- const: hpp
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- const: usbp
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- const: s
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- const: zb
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- const: m3
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- const: cp
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required:
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- renesas,mode
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7778-cpg-clocks
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then:
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properties:
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clocks:
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maxItems: 1
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clock-output-names:
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items:
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- const: plla
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- const: pllb
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- const: b
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- const: out
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- const: p
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- const: s
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- const: s1
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r8a7779-cpg-clocks
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then:
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properties:
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clocks:
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maxItems: 1
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clock-output-names:
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items:
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- const: plla
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- const: z
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- const: zs
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- const: s
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- const: s1
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- const: p
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- const: b
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- const: out
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r7s72100-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: usb_x1
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clock-output-names:
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items:
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- const: pll
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- const: i
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- const: g
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- if:
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properties:
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compatible:
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contains:
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const: renesas,sh73a0-cpg-clocks
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then:
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properties:
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clocks:
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items:
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- description: extal1
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- description: extal2
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clock-output-names:
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items:
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- const: main
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- const: pll0
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- const: pll1
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- const: pll2
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- const: pll3
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- const: dsi0phy
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- const: dsi1phy
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- const: zg
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- const: m3
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- const: b
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- const: m1
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- const: m2
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- const: z
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- const: zx
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- const: hp
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|
||||
- if:
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||||
properties:
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compatible:
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||||
contains:
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enum:
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- renesas,r8a7778-cpg-clocks
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||||
- renesas,r8a7779-cpg-clocks
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||||
- renesas,rz-cpg-clocks
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then:
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||||
required:
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||||
- '#power-domain-cells'
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||||
additionalProperties: false
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|
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examples:
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||||
- |
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||||
#include <dt-bindings/clock/r8a7740-clock.h>
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
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"usb24s", "i", "zg", "b", "m1", "hp", "hpp",
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"usbp", "s", "zb", "m3", "cp";
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renesas,mode = <0x05>;
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};
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@ -33,6 +33,7 @@ properties:
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- renesas,r8a774a1-cpg-mssr # RZ/G2M
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- renesas,r8a774b1-cpg-mssr # RZ/G2N
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- renesas,r8a774c0-cpg-mssr # RZ/G2E
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- renesas,r8a774e1-cpg-mssr # RZ/G2H
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- renesas,r8a7790-cpg-mssr # R-Car H2
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- renesas,r8a7791-cpg-mssr # R-Car M2-W
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- renesas,r8a7792-cpg-mssr # R-Car V2H
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||||
@ -1,33 +0,0 @@
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* Renesas R8A73A4 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
|
||||
and several fixed ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a73a4-cpg-clocks"
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||||
|
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- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clocks ("extal1" and "extal2")
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||||
|
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- #clock-cells: Must be 1
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||||
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
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"pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
|
||||
"m1", "m2", "zx", "zs", and "hp".
|
||||
|
||||
|
||||
Example
|
||||
-------
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||||
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a73a4-cpg-clocks";
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reg = <0 0xe6150000 0 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll2",
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"pll2s", "pll2h", "z", "z2",
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"i", "m3", "b", "m1", "m2",
|
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"zx", "zs", "hp";
|
||||
};
|
||||
@ -1,41 +0,0 @@
|
||||
These bindings should be considered EXPERIMENTAL for now.
|
||||
|
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* Renesas R8A7740 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
|
||||
and several fixed ratio and variable ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7740-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the three parent clocks
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
|
||||
"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
|
||||
|
||||
- renesas,mode: board-specific settings of the MD_CK* bits
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1",
|
||||
"pllc2", "r",
|
||||
"usb24s",
|
||||
"i", "zg", "b", "m1", "hp",
|
||||
"hpp", "usbp", "s", "zb", "m3",
|
||||
"cp";
|
||||
};
|
||||
|
||||
&cpg_clocks {
|
||||
renesas,mode = <0x05>;
|
||||
};
|
||||
@ -1,47 +0,0 @@
|
||||
* Renesas R8A7778 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7778. It includes two PLLs and
|
||||
several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7778-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"plla", "pllb", "b", "out", "p", "s", and "s1".
|
||||
- #power-domain-cells: Must be 0
|
||||
|
||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
||||
through an MSTP clock should refer to the CPG device node in their
|
||||
"power-domains" property, as documented by the generic PM domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7778-cpg-clocks";
|
||||
reg = <0xffc80000 0x80>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-output-names = "plla", "pllb", "b",
|
||||
"out", "p", "s", "s1";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSTP Clock Domain member device node:
|
||||
|
||||
sdhi0: sd@ffe4c000 {
|
||||
compatible = "renesas,sdhi-r8a7778";
|
||||
reg = <0xffe4c000 0x100>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
@ -1,49 +0,0 @@
|
||||
* Renesas R8A7779 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7779. It includes one PLL and
|
||||
several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7779-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clock
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "plla",
|
||||
"z", "zs", "s", "s1", "p", "b", "out".
|
||||
- #power-domain-cells: Must be 0
|
||||
|
||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
||||
through an MSTP clock should refer to the CPG device node in their
|
||||
"power-domains" property, as documented by the generic PM domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7779-cpg-clocks";
|
||||
reg = <0xffc80000 0x30>;
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
|
||||
"b", "out";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSTP Clock Domain member device node:
|
||||
|
||||
sata: sata@fc600000 {
|
||||
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
@ -1,53 +0,0 @@
|
||||
* Renesas RZ/A1 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
|
||||
CPU and GPU clocks, and several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of
|
||||
- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
|
||||
and "renesas,rz-cpg-clocks" as a fallback.
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
- clocks: References to possible parent clocks. Order must match clock modes
|
||||
in the datasheet. For the r7s72100, this is extal, usb_x1.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "pll",
|
||||
"i", and "g"
|
||||
- #power-domain-cells: Must be 0
|
||||
|
||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
||||
through an MSTP clock should refer to the CPG device node in their
|
||||
"power-domains" property, as documented by the generic PM domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg_clocks: cpg_clocks@fcfe0000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "renesas,r7s72100-cpg-clocks",
|
||||
"renesas,rz-cpg-clocks";
|
||||
reg = <0xfcfe0000 0x18>;
|
||||
clocks = <&extal_clk>, <&usb_x1_clk>;
|
||||
clock-output-names = "pll", "i", "g";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSTP Clock Domain member device node:
|
||||
|
||||
mtu2: timer@fcff0000 {
|
||||
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
|
||||
reg = <0xfcff0000 0x400>;
|
||||
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "tgi0a";
|
||||
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
@ -1,35 +0,0 @@
|
||||
These bindings should be considered EXPERIMENTAL for now.
|
||||
|
||||
* Renesas SH73A0 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the SH73A0 SoC. It includes four PLLs
|
||||
and several fixed ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,sh73a0-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clocks ("extal1" and "extal2")
|
||||
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||||
"pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
|
||||
"m1", "m2", "z", "zx", and "hp".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,sh73a0-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||||
"pll3", "dsi0phy", "dsi1phy",
|
||||
"zg", "m3", "b", "m1", "m2",
|
||||
"z", "zx", "hp";
|
||||
};
|
||||
@ -6,7 +6,7 @@ found in the datasheet[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si514 datasheet
|
||||
http://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall be "silabs,si514"
|
||||
|
||||
@ -2,7 +2,7 @@ Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
|
||||
|
||||
Reference
|
||||
[1] Si5351A/B/C Data Sheet
|
||||
http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
|
||||
|
||||
The Si5351a/b/c are programmable i2c clock generators with up to 8 output
|
||||
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
|
||||
|
||||
@ -7,9 +7,9 @@ found in the data sheets[2][3].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si570/571 Data Sheet
|
||||
http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
|
||||
[3] Si598/599 Data Sheet
|
||||
http://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall be one of "silabs,si570", "silabs,si571",
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
|
||||
synthesizer/multiplier/divider.
|
||||
|
||||
Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf
|
||||
Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf
|
||||
|
||||
I2C device node required properties:
|
||||
- compatible: shall be "ti,cdce706".
|
||||
|
||||
@ -4,10 +4,10 @@ Reference
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] http://www.ti.com/product/cdce913
|
||||
[3] http://www.ti.com/product/cdce925
|
||||
[4] http://www.ti.com/product/cdce937
|
||||
[5] http://www.ti.com/product/cdce949
|
||||
[2] https://www.ti.com/product/cdce913
|
||||
[3] https://www.ti.com/product/cdce925
|
||||
[4] https://www.ti.com/product/cdce937
|
||||
[5] https://www.ti.com/product/cdce949
|
||||
|
||||
The driver provides clock sources for each output Y1 through Y5.
|
||||
|
||||
|
||||
@ -50,6 +50,7 @@ source "drivers/clk/versatile/Kconfig"
|
||||
config CLK_HSDK
|
||||
bool "PLL Driver for HSDK platform"
|
||||
depends on OF || COMPILE_TEST
|
||||
depends on HAS_IOMEM
|
||||
help
|
||||
This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
|
||||
control.
|
||||
@ -120,7 +121,6 @@ config COMMON_CLK_SI5351
|
||||
tristate "Clock driver for SiLabs 5351A/B/C"
|
||||
depends on I2C
|
||||
select REGMAP_I2C
|
||||
select RATIONAL
|
||||
help
|
||||
This driver supports Silicon Labs 5351A/B/C programmable clock
|
||||
generators.
|
||||
@ -162,7 +162,6 @@ config COMMON_CLK_CDCE706
|
||||
tristate "Clock driver for TI CDCE706 clock synthesizer"
|
||||
depends on I2C
|
||||
select REGMAP_I2C
|
||||
select RATIONAL
|
||||
help
|
||||
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
|
||||
|
||||
|
||||
@ -131,6 +131,18 @@ static const struct clk_div_table ast2600_eclk_div_table[] = {
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
|
||||
{ 0x0, 2 },
|
||||
{ 0x1, 4 },
|
||||
{ 0x2, 6 },
|
||||
{ 0x3, 8 },
|
||||
{ 0x4, 10 },
|
||||
{ 0x5, 12 },
|
||||
{ 0x6, 14 },
|
||||
{ 0x7, 16 },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static const struct clk_div_table ast2600_mac_div_table[] = {
|
||||
{ 0x0, 4 },
|
||||
{ 0x1, 4 },
|
||||
@ -390,6 +402,11 @@ static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
|
||||
return hw;
|
||||
}
|
||||
|
||||
static const char *const emmc_extclk_parent_names[] = {
|
||||
"emmc_extclk_hpll_in",
|
||||
"mpll",
|
||||
};
|
||||
|
||||
static const char * const vclk_parent_names[] = {
|
||||
"dpll",
|
||||
"d1pll",
|
||||
@ -459,15 +476,31 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(hw);
|
||||
aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
|
||||
|
||||
/* EMMC ext clock divider */
|
||||
hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
|
||||
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
|
||||
&aspeed_g6_clk_lock);
|
||||
/* EMMC ext clock */
|
||||
hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
|
||||
0, 1, 2);
|
||||
if (IS_ERR(hw))
|
||||
return PTR_ERR(hw);
|
||||
hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
|
||||
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
|
||||
ast2600_div_table,
|
||||
|
||||
hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
|
||||
emmc_extclk_parent_names,
|
||||
ARRAY_SIZE(emmc_extclk_parent_names), 0,
|
||||
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
|
||||
0, &aspeed_g6_clk_lock);
|
||||
if (IS_ERR(hw))
|
||||
return PTR_ERR(hw);
|
||||
|
||||
hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
|
||||
0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
|
||||
15, 0, &aspeed_g6_clk_lock);
|
||||
if (IS_ERR(hw))
|
||||
return PTR_ERR(hw);
|
||||
|
||||
hw = clk_hw_register_divider_table(dev, "emmc_extclk",
|
||||
"emmc_extclk_gate", 0,
|
||||
scu_g6_base +
|
||||
ASPEED_G6_CLK_SELECTION1, 12,
|
||||
3, 0, ast2600_emmc_extclk_div_table,
|
||||
&aspeed_g6_clk_lock);
|
||||
if (IS_ERR(hw))
|
||||
return PTR_ERR(hw);
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
*
|
||||
* Copyright (c) 2014 Cadence Design Systems Inc.
|
||||
*
|
||||
* Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf
|
||||
* Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com
|
||||
* Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
|
||||
*
|
||||
* Authors:
|
||||
* Jyri Sarha <jsarha@ti.com>
|
||||
|
||||
@ -7,9 +7,9 @@
|
||||
*
|
||||
* References:
|
||||
* [1] "Si5351A/B/C Data Sheet"
|
||||
* http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
|
||||
* https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
|
||||
* [2] "Manually Generating an Si5351 Register Map"
|
||||
* http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
|
||||
* https://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
@ -680,6 +680,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
|
||||
hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
|
||||
hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
|
||||
hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0);
|
||||
hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
|
||||
hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
|
||||
hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
|
||||
|
||||
@ -438,6 +438,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
||||
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
|
||||
clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);
|
||||
clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));
|
||||
clk[VF610_CLK_CAAM] = imx_clk_gate2("caam", "ipg_bus", CCM_CCGR11, CCM_CCGRx_CGn(0));
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* SCI Clock driver for keystone based devices
|
||||
*
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Tero Kristo <t-kristo@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
@ -3981,6 +3981,113 @@ static struct clk_regmap g12a_spicc1_sclk = {
|
||||
},
|
||||
};
|
||||
|
||||
/* Neural Network Accelerator source clock */
|
||||
|
||||
static const struct clk_parent_data nna_clk_parent_data[] = {
|
||||
{ .fw_name = "xtal", },
|
||||
{ .hw = &g12a_gp0_pll.hw, },
|
||||
{ .hw = &g12a_hifi_pll.hw, },
|
||||
{ .hw = &g12a_fclk_div2p5.hw, },
|
||||
{ .hw = &g12a_fclk_div3.hw, },
|
||||
{ .hw = &g12a_fclk_div4.hw, },
|
||||
{ .hw = &g12a_fclk_div5.hw, },
|
||||
{ .hw = &g12a_fclk_div7.hw },
|
||||
};
|
||||
|
||||
static struct clk_regmap sm1_nna_axi_clk_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_NNA_CLK_CNTL,
|
||||
.mask = 7,
|
||||
.shift = 9,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "nna_axi_clk_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_data = nna_clk_parent_data,
|
||||
.num_parents = ARRAY_SIZE(nna_clk_parent_data),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap sm1_nna_axi_clk_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_NNA_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "nna_axi_clk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&sm1_nna_axi_clk_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap sm1_nna_axi_clk = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_NNA_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "nna_axi_clk",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&sm1_nna_axi_clk_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap sm1_nna_core_clk_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_NNA_CLK_CNTL,
|
||||
.mask = 7,
|
||||
.shift = 25,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "nna_core_clk_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_data = nna_clk_parent_data,
|
||||
.num_parents = ARRAY_SIZE(nna_clk_parent_data),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap sm1_nna_core_clk_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_NNA_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "nna_core_clk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&sm1_nna_core_clk_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap sm1_nna_core_clk = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_NNA_CLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "nna_core_clk",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&sm1_nna_core_clk_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
#define MESON_GATE(_name, _reg, _bit) \
|
||||
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
|
||||
|
||||
@ -4779,6 +4886,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
|
||||
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
|
||||
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
|
||||
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
|
||||
[CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
|
||||
[CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
|
||||
[CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
|
||||
[CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
|
||||
[CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
|
||||
[CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
@ -5020,6 +5133,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
|
||||
&g12a_spicc1_sclk_sel,
|
||||
&g12a_spicc1_sclk_div,
|
||||
&g12a_spicc1_sclk,
|
||||
&sm1_nna_axi_clk_sel,
|
||||
&sm1_nna_axi_clk_div,
|
||||
&sm1_nna_axi_clk,
|
||||
&sm1_nna_core_clk_sel,
|
||||
&sm1_nna_core_clk_div,
|
||||
&sm1_nna_core_clk,
|
||||
};
|
||||
|
||||
static const struct reg_sequence g12a_init_regs[] = {
|
||||
|
||||
@ -70,6 +70,7 @@
|
||||
#define HHI_MALI_CLK_CNTL 0x1b0
|
||||
#define HHI_VPU_CLKC_CNTL 0x1b4
|
||||
#define HHI_VPU_CLK_CNTL 0x1bC
|
||||
#define HHI_NNA_CLK_CNTL 0x1C8
|
||||
#define HHI_HDMI_CLK_CNTL 0x1CC
|
||||
#define HHI_VDEC_CLK_CNTL 0x1E0
|
||||
#define HHI_VDEC2_CLK_CNTL 0x1E4
|
||||
@ -259,8 +260,12 @@
|
||||
#define CLKID_SPICC0_SCLK_DIV 257
|
||||
#define CLKID_SPICC1_SCLK_SEL 259
|
||||
#define CLKID_SPICC1_SCLK_DIV 260
|
||||
#define CLKID_NNA_AXI_CLK_SEL 262
|
||||
#define CLKID_NNA_AXI_CLK_DIV 263
|
||||
#define CLKID_NNA_CORE_CLK_SEL 265
|
||||
#define CLKID_NNA_CORE_CLK_DIV 266
|
||||
|
||||
#define NR_CLKS 262
|
||||
#define NR_CLKS 268
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/g12a-clkc.h>
|
||||
|
||||
@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = {
|
||||
&meson8b_fclk_div2_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* FIXME: Ethernet with a RGMII PHYs is not working if
|
||||
* fclk_div2 is disabled. it is currently unclear why this
|
||||
* is. keep it enabled until the Ethernet driver knows how
|
||||
* to manage this clock.
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1211,6 +1204,22 @@ static struct clk_regmap meson8b_vclk_in_en = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vclk_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 19,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vclk_div1_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
@ -1220,7 +1229,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
|
||||
.name = "vclk_div1_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1234,7 +1243,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
|
||||
.name = "vclk_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1264,7 +1273,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
|
||||
.name = "vclk_div4",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1294,7 +1303,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
|
||||
.name = "vclk_div6",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1324,7 +1333,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
|
||||
.name = "vclk_div12",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk_in_en.hw
|
||||
&meson8b_vclk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1378,6 +1387,22 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vclk2_clk_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_DIV,
|
||||
.bit_idx = 19,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vclk2_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_in_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vclk2_div1_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VIID_CLK_DIV,
|
||||
@ -1387,7 +1412,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
|
||||
.name = "vclk2_div1_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_in_en.hw
|
||||
&meson8b_vclk2_clk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1401,7 +1426,7 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = {
|
||||
.name = "vclk2_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_in_en.hw
|
||||
&meson8b_vclk2_clk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1431,7 +1456,7 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = {
|
||||
.name = "vclk2_div4",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_in_en.hw
|
||||
&meson8b_vclk2_clk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1461,7 +1486,7 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = {
|
||||
.name = "vclk2_div6",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_in_en.hw
|
||||
&meson8b_vclk2_clk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -1491,7 +1516,7 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = {
|
||||
.name = "vclk2_div12",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_vclk2_clk_in_en.hw
|
||||
&meson8b_vclk2_clk_en.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -2827,6 +2852,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
||||
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
|
||||
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
|
||||
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
|
||||
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
|
||||
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
|
||||
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
|
||||
@ -2838,6 +2864,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
||||
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
|
||||
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
|
||||
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
|
||||
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
|
||||
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
|
||||
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
|
||||
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
|
||||
@ -3032,6 +3059,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
|
||||
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
|
||||
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
|
||||
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
|
||||
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
|
||||
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
|
||||
@ -3043,6 +3071,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
|
||||
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
|
||||
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
|
||||
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
|
||||
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
|
||||
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
|
||||
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
|
||||
@ -3248,6 +3277,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
||||
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
|
||||
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
|
||||
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
|
||||
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
|
||||
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
|
||||
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
|
||||
@ -3259,6 +3289,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
||||
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
|
||||
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
|
||||
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
|
||||
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
|
||||
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
|
||||
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
|
||||
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
|
||||
@ -3450,6 +3481,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
||||
&meson8b_vid_pll_final_div,
|
||||
&meson8b_vclk_in_sel,
|
||||
&meson8b_vclk_in_en,
|
||||
&meson8b_vclk_en,
|
||||
&meson8b_vclk_div1_gate,
|
||||
&meson8b_vclk_div2_div_gate,
|
||||
&meson8b_vclk_div4_div_gate,
|
||||
@ -3457,6 +3489,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
||||
&meson8b_vclk_div12_div_gate,
|
||||
&meson8b_vclk2_in_sel,
|
||||
&meson8b_vclk2_clk_in_en,
|
||||
&meson8b_vclk2_clk_en,
|
||||
&meson8b_vclk2_div1_gate,
|
||||
&meson8b_vclk2_div2_div_gate,
|
||||
&meson8b_vclk2_div4_div_gate,
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
* blocks below. Those offsets must be multiplied by 4 before adding them to
|
||||
* the base address to get the right value
|
||||
*
|
||||
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
|
||||
* [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
|
||||
*/
|
||||
#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
|
||||
#define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
|
||||
@ -180,8 +180,10 @@
|
||||
#define CLKID_CTS_AMCLK_DIV 208
|
||||
#define CLKID_CTS_MCLK_I958_SEL 210
|
||||
#define CLKID_CTS_MCLK_I958_DIV 211
|
||||
#define CLKID_VCLK_EN 214
|
||||
#define CLKID_VCLK2_EN 215
|
||||
|
||||
#define CLK_NR_CLKS 214
|
||||
#define CLK_NR_CLKS 216
|
||||
|
||||
/*
|
||||
* include the CLKID and RESETID that have
|
||||
|
||||
@ -42,6 +42,7 @@ config ARMADA_AP806_SYSCON
|
||||
|
||||
config ARMADA_AP_CPU_CLK
|
||||
bool
|
||||
select ARMADA_AP_CP_HELPER
|
||||
|
||||
config ARMADA_CP110_SYSCON
|
||||
bool
|
||||
|
||||
@ -15,6 +15,7 @@ config CLK_RENESAS
|
||||
select CLK_R8A774A1 if ARCH_R8A774A1
|
||||
select CLK_R8A774B1 if ARCH_R8A774B1
|
||||
select CLK_R8A774C0 if ARCH_R8A774C0
|
||||
select CLK_R8A774E1 if ARCH_R8A774E1
|
||||
select CLK_R8A7778 if ARCH_R8A7778
|
||||
select CLK_R8A7779 if ARCH_R8A7779
|
||||
select CLK_R8A7790 if ARCH_R8A7790
|
||||
@ -84,6 +85,10 @@ config CLK_R8A774C0
|
||||
bool "RZ/G2E clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
||||
config CLK_R8A774E1
|
||||
bool "RZ/G2H clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
||||
config CLK_R8A7778
|
||||
bool "R-Car M1A clock support" if COMPILE_TEST
|
||||
select CLK_RENESAS_CPG_MSTP
|
||||
|
||||
@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
|
||||
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
|
||||
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
|
||||
|
||||
@ -237,6 +237,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a774a1_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
@ -233,6 +233,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a774b1_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
@ -238,6 +238,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a774c0_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
349
drivers/clk/renesas/r8a774e1-cpg-mssr.c
Normal file
349
drivers/clk/renesas/r8a774e1-cpg-mssr.c
Normal file
@ -0,0 +1,349 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a774e1 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A774E1_CLK_CANFD,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A774E1_CLK_RPC),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
|
||||
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
|
||||
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A774E1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A774E1_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A774E1_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A774E1_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A774E1_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A774E1_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A774E1_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A774E1_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d2", R8A774E1_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A774E1_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A774E1_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A774E1_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A774E1_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A774E1_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A774E1_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A774E1_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
|
||||
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("tmu2", 123, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("tmu1", 124, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("tmu0", 125, R8A774E1_CLK_CP),
|
||||
DEF_MOD("vcplf", 130, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("vdpb", 131, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("scif5", 202, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A774E1_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A774E1_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A774E1_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A774E1_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A774E1_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif2", 310, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A774E1_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A774E1_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A774E1_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A774E1_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A774E1_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A774E1_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A774E1_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A774E1_CLK_S1D2),
|
||||
DEF_MOD("audmac0", 502, R8A774E1_CLK_S1D2),
|
||||
DEF_MOD("hscif4", 516, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A774E1_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A774E1_CLK_S0D12),
|
||||
DEF_MOD("fcpvd1", 602, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("fcpvb1", 606, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpvb0", 607, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpvi1", 610, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpf1", 614, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vspbc", 624, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspbd", 626, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspi1", 630, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("ehci1", 702, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("ehci0", 703, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("csi20", 714, R8A774E1_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A774E1_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A774E1_CLK_S0D4),
|
||||
DEF_MOD("hdmi0", 729, R8A774E1_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("gpio7", 905, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("adg", 922, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774E1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a774e1_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a774e1_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
if (!cpg_pll_config->extal_div) {
|
||||
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a774e1_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a774e1_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a774e1_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a774e1_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a774e1_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a774e1_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a774e1_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a774e1_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
@ -287,10 +287,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
@ -262,10 +262,10 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
@ -263,6 +263,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
@ -165,10 +165,10 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
@ -180,10 +180,10 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
@ -245,6 +245,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
@ -183,10 +183,10 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
@ -416,14 +416,6 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
|
||||
init.name = mod->name;
|
||||
init.ops = &cpg_mstp_clock_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
for (i = 0; i < info->num_crit_mod_clks; i++)
|
||||
if (id == info->crit_mod_clks[i]) {
|
||||
dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
|
||||
mod->name);
|
||||
init.flags |= CLK_IS_CRITICAL;
|
||||
break;
|
||||
}
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
@ -432,6 +424,15 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
|
||||
clock->priv = priv;
|
||||
clock->hw.init = &init;
|
||||
|
||||
for (i = 0; i < info->num_crit_mod_clks; i++)
|
||||
if (id == info->crit_mod_clks[i] &&
|
||||
cpg_mstp_clock_is_enabled(&clock->hw)) {
|
||||
dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
|
||||
mod->name);
|
||||
init.flags |= CLK_IS_CRITICAL;
|
||||
break;
|
||||
}
|
||||
|
||||
clk = clk_register(NULL, &clock->hw);
|
||||
if (IS_ERR(clk))
|
||||
goto fail;
|
||||
@ -720,6 +721,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
||||
.data = &r8a774c0_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A774E1
|
||||
{
|
||||
.compatible = "renesas,r8a774e1-cpg-mssr",
|
||||
.data = &r8a774e1_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7790
|
||||
{
|
||||
.compatible = "renesas,r8a7790-cpg-mssr",
|
||||
|
||||
@ -162,6 +162,7 @@ extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
|
||||
*
|
||||
* Support functions for calculating clocks/divisors for the ICST307
|
||||
* clock generators. See http://www.idt.com/ for more information
|
||||
* clock generators. See https://www.idt.com/ for more information
|
||||
* on these devices.
|
||||
*
|
||||
* This is an almost identical implementation to the ICST525 clock generator.
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
|
||||
*
|
||||
* Support functions for calculating clocks/divisors for the ICST
|
||||
* clock generators. See http://www.idt.com/ for more information
|
||||
* clock generators. See https://www.idt.com/ for more information
|
||||
* on these devices.
|
||||
*/
|
||||
#ifndef ICST_H
|
||||
|
||||
@ -145,5 +145,7 @@
|
||||
#define CLKID_CPU3_CLK 255
|
||||
#define CLKID_SPICC0_SCLK 258
|
||||
#define CLKID_SPICC1_SCLK 261
|
||||
#define CLKID_NNA_AXI_CLK 264
|
||||
#define CLKID_NNA_CORE_CLK 267
|
||||
|
||||
#endif /* __G12A_CLKC_H */
|
||||
|
||||
59
include/dt-bindings/clock/r8a774e1-cpg-mssr.h
Normal file
59
include/dt-bindings/clock/r8a774e1-cpg-mssr.h
Normal file
@ -0,0 +1,59 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R8A774E1 CPG Core Clocks */
|
||||
#define R8A774E1_CLK_Z 0
|
||||
#define R8A774E1_CLK_Z2 1
|
||||
#define R8A774E1_CLK_ZG 2
|
||||
#define R8A774E1_CLK_ZTR 3
|
||||
#define R8A774E1_CLK_ZTRD2 4
|
||||
#define R8A774E1_CLK_ZT 5
|
||||
#define R8A774E1_CLK_ZX 6
|
||||
#define R8A774E1_CLK_S0D1 7
|
||||
#define R8A774E1_CLK_S0D2 8
|
||||
#define R8A774E1_CLK_S0D3 9
|
||||
#define R8A774E1_CLK_S0D4 10
|
||||
#define R8A774E1_CLK_S0D6 11
|
||||
#define R8A774E1_CLK_S0D8 12
|
||||
#define R8A774E1_CLK_S0D12 13
|
||||
#define R8A774E1_CLK_S1D2 14
|
||||
#define R8A774E1_CLK_S1D4 15
|
||||
#define R8A774E1_CLK_S2D1 16
|
||||
#define R8A774E1_CLK_S2D2 17
|
||||
#define R8A774E1_CLK_S2D4 18
|
||||
#define R8A774E1_CLK_S3D1 19
|
||||
#define R8A774E1_CLK_S3D2 20
|
||||
#define R8A774E1_CLK_S3D4 21
|
||||
#define R8A774E1_CLK_LB 22
|
||||
#define R8A774E1_CLK_CL 23
|
||||
#define R8A774E1_CLK_ZB3 24
|
||||
#define R8A774E1_CLK_ZB3D2 25
|
||||
#define R8A774E1_CLK_ZB3D4 26
|
||||
#define R8A774E1_CLK_CR 27
|
||||
#define R8A774E1_CLK_CRD2 28
|
||||
#define R8A774E1_CLK_SD0H 29
|
||||
#define R8A774E1_CLK_SD0 30
|
||||
#define R8A774E1_CLK_SD1H 31
|
||||
#define R8A774E1_CLK_SD1 32
|
||||
#define R8A774E1_CLK_SD2H 33
|
||||
#define R8A774E1_CLK_SD2 34
|
||||
#define R8A774E1_CLK_SD3H 35
|
||||
#define R8A774E1_CLK_SD3 36
|
||||
#define R8A774E1_CLK_RPC 37
|
||||
#define R8A774E1_CLK_RPCD2 38
|
||||
#define R8A774E1_CLK_MSO 39
|
||||
#define R8A774E1_CLK_HDMI 40
|
||||
#define R8A774E1_CLK_CSI0 41
|
||||
#define R8A774E1_CLK_CP 42
|
||||
#define R8A774E1_CLK_CPEX 43
|
||||
#define R8A774E1_CLK_R 44
|
||||
#define R8A774E1_CLK_OSC 45
|
||||
#define R8A774E1_CLK_CANFD 46
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */
|
||||
@ -195,6 +195,7 @@
|
||||
#define VF610_CLK_WKPU 186
|
||||
#define VF610_CLK_TCON0 187
|
||||
#define VF610_CLK_TCON1 188
|
||||
#define VF610_CLK_END 189
|
||||
#define VF610_CLK_CAAM 189
|
||||
#define VF610_CLK_END 190
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
|
||||
|
||||
36
include/dt-bindings/power/r8a774e1-sysc.h
Normal file
36
include/dt-bindings/power/r8a774e1-sysc.h
Normal file
@ -0,0 +1,36 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A774E1_PD_CA57_CPU0 0
|
||||
#define R8A774E1_PD_CA57_CPU1 1
|
||||
#define R8A774E1_PD_CA57_CPU2 2
|
||||
#define R8A774E1_PD_CA57_CPU3 3
|
||||
#define R8A774E1_PD_CA53_CPU0 5
|
||||
#define R8A774E1_PD_CA53_CPU1 6
|
||||
#define R8A774E1_PD_CA53_CPU2 7
|
||||
#define R8A774E1_PD_CA53_CPU3 8
|
||||
#define R8A774E1_PD_A3VP 9
|
||||
#define R8A774E1_PD_CA57_SCU 12
|
||||
#define R8A774E1_PD_A3VC 14
|
||||
#define R8A774E1_PD_3DG_A 17
|
||||
#define R8A774E1_PD_3DG_B 18
|
||||
#define R8A774E1_PD_3DG_C 19
|
||||
#define R8A774E1_PD_3DG_D 20
|
||||
#define R8A774E1_PD_CA53_SCU 21
|
||||
#define R8A774E1_PD_3DG_E 22
|
||||
#define R8A774E1_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A774E1_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */
|
||||
Loading…
Reference in New Issue
Block a user