pinctrl: renesas: Updates for v5.15 (take two)
- Add pin control and GPIO support for the new RZ/G2L SoC. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYRZFUQAKCRCKwlD9ZEnx cCRjAP0U1x4/IFI9ht4WL2t2FKMy4TreYcOxeLVSivXC91r19wD/WpjASyA/Dnlj Y4hJRyW0dFv7Uab0dqzLAO+WtABM0gg= =3MMW -----END PGP SIGNATURE----- Merge tag 'renesas-pinctrl-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.15 (take two) - Add pin control and GPIO support for the new RZ/G2L SoC.
This commit is contained in:
Linus Walleij
commit
8cd99e3e22
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L combined Pin and GPIO controller
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
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controller.
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Pin multiplexing and GPIO configuration is performed on a per-pin basis.
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Each port features up to 8 pins, each of them configurable for GPIO function
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(port mode) or in alternate function mode.
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Up to 8 different alternate function modes exist for each single pin.
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properties:
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compatible:
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enum:
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- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
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reg:
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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const: 2
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description:
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The first cell contains the global GPIO port index, constructed using the
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RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
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second cell represents consumer flag as mentioned in ../gpio/gpio.txt
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E.g. "RZG2L_GPIO(39, 1)" for P39_1.
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gpio-ranges:
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maxItems: 1
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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items:
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- description: GPIO_RSTN signal
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- description: GPIO_PORT_RESETN signal
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- description: GPIO_SPARE_RESETN signal
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additionalProperties:
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anyOf:
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- type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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description:
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Pin controller client devices use pin configuration subnodes (children
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and grandchildren) for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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phandle: true
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pinmux:
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description:
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Values are constructed from GPIO port number, pin number, and
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alternate function configuration number using the RZG2L_PORT_PINMUX()
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helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
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pins: true
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drive-strength:
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enum: [ 2, 4, 8, 12 ]
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power-source:
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enum: [ 1800, 2500, 3300 ]
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slew-rate: true
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gpio-hog: true
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gpios: true
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input-enable: true
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output-high: true
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output-low: true
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line-name: true
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- type: object
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properties:
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phandle: true
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additionalProperties:
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$ref: "#/additionalProperties/anyOf/0"
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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- clocks
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- power-domains
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- resets
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examples:
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- |
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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pinctrl: pinctrl@11030000 {
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compatible = "renesas,r9a07g044-pinctrl";
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reg = <0x11030000 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 392>;
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clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
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resets = <&cpg R9A07G044_GPIO_RSTN>,
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<&cpg R9A07G044_GPIO_PORT_RESETN>,
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<&cpg R9A07G044_GPIO_SPARE_RESETN>;
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power-domains = <&cpg>;
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scif0_pins: serial0 {
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pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
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<RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
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};
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i2c1_pins: i2c1 {
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pins = "RIIC1_SDA", "RIIC1_SCL";
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input-enable;
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};
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sd1-pwr-en-hog {
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gpio-hog;
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gpios = <RZG2L_GPIO(39, 2) 0>;
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output-high;
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line-name = "sd1_pwr_en";
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};
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sdhi1_pins: sd1 {
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sd1_mux {
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pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
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<RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
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power-source = <3300>;
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};
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sd1_data {
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pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
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power-source = <3300>;
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};
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sd1_ctrl {
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pins = "SD1_CLK", "SD1_CMD";
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power-source = <3300>;
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};
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};
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};
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@ -37,6 +37,7 @@ config PINCTRL_RENESAS
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select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
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select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
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select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
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select PINCTRL_RZG2L if ARCH_R9A07G044
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select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
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select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
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select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
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@ -176,6 +177,16 @@ config PINCTRL_RZA2
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help
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This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
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config PINCTRL_RZG2L
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bool "pin control support for RZ/G2L" if COMPILE_TEST
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depends on OF
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select GPIOLIB
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select GENERIC_PINCTRL_GROUPS
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select GENERIC_PINMUX_FUNCTIONS
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select GENERIC_PINCONF
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help
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This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.
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config PINCTRL_PFC_R8A77470
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bool "pin control support for RZ/G1C" if COMPILE_TEST
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select PINCTRL_SH_PFC
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@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
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obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
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obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
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obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o
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obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
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ifeq ($(CONFIG_COMPILE_TEST),y)
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1175
drivers/pinctrl/renesas/pinctrl-rzg2l.c
Normal file
1175
drivers/pinctrl/renesas/pinctrl-rzg2l.c
Normal file
File diff suppressed because it is too large
Load Diff
23
include/dt-bindings/pinctrl/rzg2l-pinctrl.h
Normal file
23
include/dt-bindings/pinctrl/rzg2l-pinctrl.h
Normal file
@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* This header provides constants for Renesas RZ/G2L family pinctrl bindings.
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*
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*/
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#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H
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#define __DT_BINDINGS_RZG2L_PINCTRL_H
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#define RZG2L_PINS_PER_PORT 8
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/*
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* Create the pin index from its bank and position numbers and store in
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* the upper 16 bits the alternate function identifier
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*/
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#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16))
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/* Convert a port and pin label to its global pin index */
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#define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */
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