riscv: dts: add initial support for the SiFive FU740-C000 SoC
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built around the SiFIve U7 Core Complex and a TileLink interconnect. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Yash Shah
Palmer Dabbelt
parent
42cf244c8f
commit
5798578815
293
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
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293
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 SiFive, Inc */
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/dts-v1/;
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,fu740-c000", "sifive,fu740";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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ethernet0 = ð0;
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};
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "sifive,bullet0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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next-level-cache = <&ccache>;
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reg = <0x0>;
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riscv,isa = "rv64imac";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <0x1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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compatible = "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <0x2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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compatible = "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <0x3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu4: cpu@4 {
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compatible = "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <0x4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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plic0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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riscv,ndev = <69>;
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 0xffffffff
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&cpu1_intc 0xffffffff &cpu1_intc 9
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&cpu2_intc 0xffffffff &cpu2_intc 9
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&cpu3_intc 0xffffffff &cpu3_intc 9
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&cpu4_intc 0xffffffff &cpu4_intc 9>;
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};
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prci: clock-controller@10000000 {
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compatible = "sifive,fu740-c000-prci";
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reg = <0x0 0x10000000 0x0 0x1000>;
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clocks = <&hfclk>, <&rtcclk>;
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#clock-cells = <1>;
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};
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uart0: serial@10010000 {
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compatible = "sifive,fu740-c000-uart", "sifive,uart0";
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reg = <0x0 0x10010000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <39>;
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clocks = <&prci PRCI_CLK_PCLK>;
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status = "disabled";
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};
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uart1: serial@10011000 {
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compatible = "sifive,fu740-c000-uart", "sifive,uart0";
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reg = <0x0 0x10011000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <40>;
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clocks = <&prci PRCI_CLK_PCLK>;
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status = "disabled";
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};
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i2c0: i2c@10030000 {
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compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
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reg = <0x0 0x10030000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <52>;
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clocks = <&prci PRCI_CLK_PCLK>;
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reg-shift = <2>;
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reg-io-width = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@10031000 {
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compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
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reg = <0x0 0x10031000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <53>;
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clocks = <&prci PRCI_CLK_PCLK>;
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reg-shift = <2>;
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reg-io-width = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi0: spi@10040000 {
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compatible = "sifive,fu740-c000-spi", "sifive,spi0";
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reg = <0x0 0x10040000 0x0 0x1000>,
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<0x0 0x20000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <41>;
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clocks = <&prci PRCI_CLK_PCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi1: spi@10041000 {
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compatible = "sifive,fu740-c000-spi", "sifive,spi0";
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reg = <0x0 0x10041000 0x0 0x1000>,
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<0x0 0x30000000 0x0 0x10000000>;
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interrupt-parent = <&plic0>;
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interrupts = <42>;
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clocks = <&prci PRCI_CLK_PCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@10050000 {
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compatible = "sifive,fu740-c000-spi", "sifive,spi0";
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reg = <0x0 0x10050000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <43>;
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clocks = <&prci PRCI_CLK_PCLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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eth0: ethernet@10090000 {
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compatible = "sifive,fu540-c000-gem";
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interrupt-parent = <&plic0>;
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interrupts = <55>;
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reg = <0x0 0x10090000 0x0 0x2000>,
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<0x0 0x100a0000 0x0 0x1000>;
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local-mac-address = [00 00 00 00 00 00];
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clock-names = "pclk", "hclk";
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clocks = <&prci PRCI_CLK_GEMGXLPLL>,
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<&prci PRCI_CLK_GEMGXLPLL>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pwm0: pwm@10020000 {
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compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
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reg = <0x0 0x10020000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <44>, <45>, <46>, <47>;
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clocks = <&prci PRCI_CLK_PCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm1: pwm@10021000 {
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compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
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reg = <0x0 0x10021000 0x0 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <48>, <49>, <50>, <51>;
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clocks = <&prci PRCI_CLK_PCLK>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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ccache: cache-controller@2010000 {
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compatible = "sifive,fu740-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <2048>;
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic0>;
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interrupts = <19 20 21 22>;
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reg = <0x0 0x2010000 0x0 0x1000>;
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};
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gpio: gpio@10060000 {
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compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
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interrupt-parent = <&plic0>;
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interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
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<30>, <31>, <32>, <33>, <34>, <35>, <36>,
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<37>, <38>;
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reg = <0x0 0x10060000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&prci PRCI_CLK_PCLK>;
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status = "disabled";
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};
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};
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};
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