iommu/arm-smmu: Consolidate stream map entry state
In order to consider SMR masking, we really want to be able to validate ID/mask pairs against existing SMR contents to prevent stream match conflicts, which at best would cause transactions to fault unexpectedly, and at worst lead to silent unpredictable behaviour. With our SMMU instance data holding only an allocator bitmap, and the SMR values themselves scattered across master configs hanging off devices which we may have no way of finding, there's essentially no way short of digging everything back out of the hardware. Similarly, the thought of power management ops to support suspend/resume faces the exact same problem. By massaging the software state into a closer shape to the underlying hardware, everything comes together quite nicely; the allocator and the high-level view of the data become a single centralised state which we can easily keep track of, and to which any updates can be validated in full before being synchronised to the hardware itself. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
21174240e4
commit
1f3d5ca430
@ -28,6 +28,7 @@
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#define pr_fmt(fmt) "arm-smmu: " fmt
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#include <linux/atomic.h>
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#include <linux/delay.h>
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#include <linux/dma-iommu.h>
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#include <linux/dma-mapping.h>
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@ -55,9 +56,6 @@
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/* Maximum number of context banks per SMMU */
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#define ARM_SMMU_MAX_CBS 128
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/* Maximum number of mapping groups per SMMU */
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#define ARM_SMMU_MAX_SMRS 128
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/* SMMU global address space */
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#define ARM_SMMU_GR0(smmu) ((smmu)->base)
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#define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
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@ -295,16 +293,17 @@ enum arm_smmu_implementation {
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};
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struct arm_smmu_smr {
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u8 idx;
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u16 mask;
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u16 id;
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bool valid;
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};
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struct arm_smmu_master_cfg {
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int num_streamids;
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u16 streamids[MAX_MASTER_STREAMIDS];
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struct arm_smmu_smr *smrs;
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s16 smendx[MAX_MASTER_STREAMIDS];
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};
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#define INVALID_SMENDX -1
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struct arm_smmu_master {
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struct device_node *of_node;
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@ -346,7 +345,7 @@ struct arm_smmu_device {
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u32 num_mapping_groups;
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u16 streamid_mask;
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u16 smr_mask_mask;
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DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
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struct arm_smmu_smr *smrs;
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unsigned long va_size;
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unsigned long ipa_size;
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@ -550,6 +549,7 @@ static int register_smmu_master(struct arm_smmu_device *smmu,
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return -ERANGE;
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}
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master->cfg.streamids[i] = streamid;
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master->cfg.smendx[i] = INVALID_SMENDX;
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}
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return insert_smmu_master(smmu, master);
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}
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@ -1080,79 +1080,91 @@ static void arm_smmu_domain_free(struct iommu_domain *domain)
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kfree(smmu_domain);
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}
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static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
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struct arm_smmu_master_cfg *cfg)
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static int arm_smmu_alloc_smr(struct arm_smmu_device *smmu)
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{
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int i;
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struct arm_smmu_smr *smrs;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
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return 0;
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for (i = 0; i < smmu->num_mapping_groups; i++)
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if (!cmpxchg(&smmu->smrs[i].valid, false, true))
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return i;
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if (cfg->smrs)
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return -EEXIST;
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return INVALID_SMENDX;
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}
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smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
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if (!smrs) {
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dev_err(smmu->dev, "failed to allocate %d SMRs\n",
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cfg->num_streamids);
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return -ENOMEM;
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}
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static void arm_smmu_free_smr(struct arm_smmu_device *smmu, int idx)
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{
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writel_relaxed(~SMR_VALID, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
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WRITE_ONCE(smmu->smrs[idx].valid, false);
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}
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static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx)
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{
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struct arm_smmu_smr *smr = smmu->smrs + idx;
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u32 reg = (smr->id & smmu->streamid_mask) << SMR_ID_SHIFT |
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(smr->mask & smmu->smr_mask_mask) << SMR_MASK_SHIFT;
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if (smr->valid)
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reg |= SMR_VALID;
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writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
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}
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static int arm_smmu_master_alloc_smes(struct arm_smmu_device *smmu,
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struct arm_smmu_master_cfg *cfg)
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{
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struct arm_smmu_smr *smrs = smmu->smrs;
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int i, idx;
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/* Allocate the SMRs on the SMMU */
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for (i = 0; i < cfg->num_streamids; ++i) {
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int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
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smmu->num_mapping_groups);
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if (cfg->smendx[i] != INVALID_SMENDX)
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return -EEXIST;
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/* ...except on stream indexing hardware, of course */
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if (!smrs) {
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cfg->smendx[i] = cfg->streamids[i];
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continue;
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}
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idx = arm_smmu_alloc_smr(smmu);
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if (idx < 0) {
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dev_err(smmu->dev, "failed to allocate free SMR\n");
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goto err_free_smrs;
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}
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cfg->smendx[i] = idx;
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smrs[i] = (struct arm_smmu_smr) {
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.idx = idx,
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.mask = 0, /* We don't currently share SMRs */
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.id = cfg->streamids[i],
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};
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smrs[idx].id = cfg->streamids[i];
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smrs[idx].mask = 0; /* We don't currently share SMRs */
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}
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if (!smrs)
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return 0;
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/* It worked! Now, poke the actual hardware */
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for (i = 0; i < cfg->num_streamids; ++i) {
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u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
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smrs[i].mask << SMR_MASK_SHIFT;
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writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
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}
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for (i = 0; i < cfg->num_streamids; ++i)
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arm_smmu_write_smr(smmu, cfg->smendx[i]);
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cfg->smrs = smrs;
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return 0;
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err_free_smrs:
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while (--i >= 0)
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__arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
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kfree(smrs);
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while (i--) {
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arm_smmu_free_smr(smmu, cfg->smendx[i]);
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cfg->smendx[i] = INVALID_SMENDX;
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}
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return -ENOSPC;
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}
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static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
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static void arm_smmu_master_free_smes(struct arm_smmu_device *smmu,
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struct arm_smmu_master_cfg *cfg)
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{
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int i;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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struct arm_smmu_smr *smrs = cfg->smrs;
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if (!smrs)
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return;
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/* Invalidate the SMRs before freeing back to the allocator */
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for (i = 0; i < cfg->num_streamids; ++i) {
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u8 idx = smrs[i].idx;
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if (smmu->smrs)
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arm_smmu_free_smr(smmu, cfg->smendx[i]);
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writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
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__arm_smmu_free_bitmap(smmu->smr_map, idx);
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cfg->smendx[i] = INVALID_SMENDX;
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}
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cfg->smrs = NULL;
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kfree(smrs);
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}
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static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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@ -1172,14 +1184,14 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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return 0;
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/* Devices in an IOMMU group may already be configured */
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ret = arm_smmu_master_configure_smrs(smmu, cfg);
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ret = arm_smmu_master_alloc_smes(smmu, cfg);
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if (ret)
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return ret == -EEXIST ? 0 : ret;
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for (i = 0; i < cfg->num_streamids; ++i) {
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u32 idx, s2cr;
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idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
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idx = cfg->smendx[i];
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s2cr = S2CR_TYPE_TRANS | S2CR_PRIVCFG_UNPRIV |
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(smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
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writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
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@ -1195,22 +1207,22 @@ static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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/* An IOMMU group is torn down by the first device to be removed */
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if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
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return;
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/*
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* We *must* clear the S2CR first, because freeing the SMR means
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* that it can be re-allocated immediately.
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*/
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for (i = 0; i < cfg->num_streamids; ++i) {
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u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
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int idx = cfg->smendx[i];
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u32 reg = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS;
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/* An IOMMU group is torn down by the first device to be removed */
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if (idx == INVALID_SMENDX)
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return;
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writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(idx));
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}
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arm_smmu_master_free_smrs(smmu, cfg);
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arm_smmu_master_free_smes(smmu, cfg);
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}
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static void arm_smmu_detach_dev(struct device *dev,
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@ -1424,8 +1436,11 @@ static int arm_smmu_init_pci_device(struct pci_dev *pdev,
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break;
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/* Avoid duplicate SIDs, as this can lead to SMR conflicts */
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if (i == cfg->num_streamids)
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cfg->streamids[cfg->num_streamids++] = sid;
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if (i == cfg->num_streamids) {
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cfg->streamids[i] = sid;
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cfg->smendx[i] = INVALID_SMENDX;
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cfg->num_streamids++;
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}
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return 0;
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}
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@ -1556,17 +1571,21 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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{
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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void __iomem *cb_base;
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int i = 0;
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int i;
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u32 reg, major;
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/* clear global FSR */
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reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
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writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
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/* Mark all SMRn as invalid and all S2CRn as bypass unless overridden */
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/*
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* Reset stream mapping groups: Initial values mark all SMRn as
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* invalid and all S2CRn as bypass unless overridden.
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*/
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reg = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS;
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
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if (smmu->smrs)
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arm_smmu_write_smr(smmu, i);
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writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
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}
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@ -1744,6 +1763,12 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
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smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT;
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/* Zero-initialised to mark as invalid */
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smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs),
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GFP_KERNEL);
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if (!smmu->smrs)
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return -ENOMEM;
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dev_notice(smmu->dev,
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"\tstream matching with %lu register groups, mask 0x%x",
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size, smmu->smr_mask_mask);
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