arm64: Implement archrandom.h for ARMv8.5-RNG
Expose the ID_AA64ISAR0.RNDR field to userspace, as the RNG system registers are always available at EL0. Implement arch_get_random_seed_long using RNDR. Given that the TRNG is likely to be a shared resource between cores, and VMs, do not explicitly force re-seeding with RNDRRS. In order to avoid code complexity and potential issues with hetrogenous systems only provide values after cpufeature has finalized the system capabilities. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [Modified to only function after cpufeature has finalized the system capabilities and move all the code into the header -- broonie] Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> [will: Advertise HWCAP via /proc/cpuinfo] Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Richard Henderson
Will Deacon
parent
46cf053efe
commit
1a50ec0b3b
@ -117,6 +117,8 @@ infrastructure:
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| RNDR | [63-60] | y |
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+------------------------------+---------+---------+
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| TS | [55-52] | y |
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+------------------------------+---------+---------+
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| FHM | [51-48] | y |
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@ -204,6 +204,10 @@ HWCAP2_FRINT
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Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
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HWCAP2_RNG
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Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
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4. Unused AT_HWCAP bits
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-----------------------
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@ -1484,6 +1484,18 @@ config ARM64_PTR_AUTH
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endmenu
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menu "ARMv8.5 architectural features"
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config ARCH_RANDOM
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bool "Enable support for random number generation"
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default y
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help
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Random number generation (part of the ARMv8.5 Extensions)
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provides a high bandwidth, cryptographically secure
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hardware random number generator.
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endmenu
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config ARM64_SVE
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bool "ARM Scalable Vector Extension support"
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default y
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67
arch/arm64/include/asm/archrandom.h
Normal file
67
arch/arm64/include/asm/archrandom.h
Normal file
@ -0,0 +1,67 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ARCHRANDOM_H
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#define _ASM_ARCHRANDOM_H
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#ifdef CONFIG_ARCH_RANDOM
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#include <linux/random.h>
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#include <asm/cpufeature.h>
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static inline bool __arm64_rndr(unsigned long *v)
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{
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bool ok;
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/*
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* Reads of RNDR set PSTATE.NZCV to 0b0000 on success,
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* and set PSTATE.NZCV to 0b0100 otherwise.
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*/
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asm volatile(
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__mrs_s("%0", SYS_RNDR_EL0) "\n"
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" cset %w1, ne\n"
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: "=r" (*v), "=r" (ok)
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:
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: "cc");
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return ok;
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}
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static inline bool __must_check arch_get_random_long(unsigned long *v)
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{
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return false;
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}
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static inline bool __must_check arch_get_random_int(unsigned int *v)
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{
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return false;
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}
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static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
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{
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/*
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* Only support the generic interface after we have detected
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* the system wide capability, avoiding complexity with the
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* cpufeature code and with potential scheduling between CPUs
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* with and without the feature.
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*/
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if (!cpus_have_const_cap(ARM64_HAS_RNG))
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return false;
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return __arm64_rndr(v);
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}
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static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
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{
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unsigned long val;
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bool ok = arch_get_random_seed_long(&val);
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*v = val;
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return ok;
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}
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#else
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static inline bool __arm64_rndr(unsigned long *v) { return false; }
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#endif /* CONFIG_ARCH_RANDOM */
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#endif /* _ASM_ARCHRANDOM_H */
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@ -56,7 +56,8 @@
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
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#define ARM64_WORKAROUND_1542419 47
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#define ARM64_WORKAROUND_1319367 48
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#define ARM64_HAS_RNG 49
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#define ARM64_NCAPS 49
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#define ARM64_NCAPS 50
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#endif /* __ASM_CPUCAPS_H */
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@ -86,6 +86,7 @@
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#define KERNEL_HWCAP_SVESM4 __khwcap2_feature(SVESM4)
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#define KERNEL_HWCAP_FLAGM2 __khwcap2_feature(FLAGM2)
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#define KERNEL_HWCAP_FRINT __khwcap2_feature(FRINT)
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#define KERNEL_HWCAP_RNG __khwcap2_feature(RNG)
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/*
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* This yields a mask that user programs can use to figure out what
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@ -365,6 +365,9 @@
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#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
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#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
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#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
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#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
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#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
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#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
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#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
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@ -539,6 +542,7 @@
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ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
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/* id_aa64isar0 */
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#define ID_AA64ISAR0_RNDR_SHIFT 60
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#define ID_AA64ISAR0_TS_SHIFT 52
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#define ID_AA64ISAR0_FHM_SHIFT 48
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#define ID_AA64ISAR0_DP_SHIFT 44
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@ -65,5 +65,6 @@
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#define HWCAP2_SVESM4 (1 << 6)
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#define HWCAP2_FLAGM2 (1 << 7)
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#define HWCAP2_FRINT (1 << 8)
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#define HWCAP2_RNG (1 << 9)
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#endif /* _UAPI__ASM_HWCAP_H */
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@ -119,6 +119,7 @@ static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
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* sync with the documentation of the CPU feature register ABI.
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*/
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static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
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@ -1566,6 +1567,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.sign = FTR_UNSIGNED,
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.min_field_value = 1,
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},
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#endif
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#ifdef CONFIG_ARCH_RANDOM
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{
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.desc = "Random Number Generator",
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.capability = ARM64_HAS_RNG,
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_RNDR_SHIFT,
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.sign = FTR_UNSIGNED,
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.min_field_value = 1,
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},
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#endif
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{},
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};
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@ -1638,6 +1651,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
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@ -84,6 +84,7 @@ static const char *const hwcap_str[] = {
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"svesm4",
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"flagm2",
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"frint",
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"rng",
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NULL
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};
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