davidlt/kernel-ark
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

MIPS: refactor the runtime coherent vs noncoherent DMA indicators

Browse Source 
Replace the global coherentio enum, and the hw_coherentio (fake) boolean
variables with a single boolean dma_default_coherent flag.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Christoph Hellwig 2021-02-10 10:56:38 +01:00 committed by Thomas Bogendoerfer
parent 3440caf5f2
commit 14ac09a65e
6 changed files with 16 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/mips/alchemy/common/setup.c
View File

@ -65,8 +65,7 @@ void __init plat_mem_setup(void)
/* Clear to obtain best system bus performance */ /* Clear to obtain best system bus performance */
clear_c0_config(1 << 19); /* Clear Config[OD] */ clear_c0_config(1 << 19); /* Clear Config[OD] */
coherentio = alchemy_dma_coherent() ? dma_default_coherent = alchemy_dma_coherent();
IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED;
board_setup(); /* board specific setup */ board_setup(); /* board specific setup */

24
arch/mips/include/asm/dma-coherence.h
View File

@ -9,30 +9,14 @@
#ifndef __ASM_DMA_COHERENCE_H #ifndef __ASM_DMA_COHERENCE_H
#define __ASM_DMA_COHERENCE_H #define __ASM_DMA_COHERENCE_H
enum coherent_io_user_state { #ifdef CONFIG_DMA_MAYBE_COHERENT
IO_COHERENCE_DEFAULT, extern bool dma_default_coherent;
IO_COHERENCE_ENABLED,
IO_COHERENCE_DISABLED,
};
#if defined(CONFIG_DMA_PERDEV_COHERENT)
/* Don't provide (hw_)coherentio to avoid misuse */
#elif defined(CONFIG_DMA_MAYBE_COHERENT)
extern enum coherent_io_user_state coherentio;
extern int hw_coherentio;
static inline bool dev_is_dma_coherent(struct device *dev) static inline bool dev_is_dma_coherent(struct device *dev)
{ {
return coherentio == IO_COHERENCE_ENABLED || return dma_default_coherent;
(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
} }
#else #else
#ifdef CONFIG_DMA_NONCOHERENT #define dma_default_coherent (!IS_ENABLED(CONFIG_DMA_NONCOHERENT))
#define coherentio IO_COHERENCE_DISABLED
#else
#define coherentio IO_COHERENCE_ENABLED
#endif #endif
#define hw_coherentio 0
#endif /* CONFIG_DMA_MAYBE_COHERENT */
#endif #endif

10
arch/mips/kernel/setup.c
View File

@ -803,14 +803,12 @@ arch_initcall(debugfs_mips);
#endif #endif
#ifdef CONFIG_DMA_MAYBE_COHERENT #ifdef CONFIG_DMA_MAYBE_COHERENT
/* User defined DMA coherency from command line. */ bool dma_default_coherent;
enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT; EXPORT_SYMBOL_GPL(dma_default_coherent);
EXPORT_SYMBOL_GPL(coherentio);
int hw_coherentio; /* Actual hardware supported DMA coherency setting. */
static int __init setcoherentio(char *str) static int __init setcoherentio(char *str)
{ {
coherentio = IO_COHERENCE_ENABLED; dma_default_coherent = true;
pr_info("Hardware DMA cache coherency (command line)\n"); pr_info("Hardware DMA cache coherency (command line)\n");
return 0; return 0;
} }
@ -818,7 +816,7 @@ early_param("coherentio", setcoherentio);
static int __init setnocoherentio(char *str) static int __init setnocoherentio(char *str)
{ {
coherentio = IO_COHERENCE_DISABLED; dma_default_coherent = true;
pr_info("Software DMA cache coherency (command line)\n"); pr_info("Software DMA cache coherency (command line)\n");
return 0; return 0;
} }

8
arch/mips/mm/c-r4k.c
View File

@ -1914,15 +1914,11 @@ void r4k_cache_init(void)
__local_flush_icache_user_range = local_r4k_flush_icache_user_range; __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
#ifdef CONFIG_DMA_NONCOHERENT #ifdef CONFIG_DMA_NONCOHERENT
#ifdef CONFIG_DMA_MAYBE_COHERENT if (dma_default_coherent) {
if (coherentio == IO_COHERENCE_ENABLED ||
(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
_dma_cache_wback_inv = (void *)cache_noop; _dma_cache_wback_inv = (void *)cache_noop;
_dma_cache_wback = (void *)cache_noop; _dma_cache_wback = (void *)cache_noop;
_dma_cache_inv = (void *)cache_noop; _dma_cache_inv = (void *)cache_noop;
} else } else {
#endif /* CONFIG_DMA_MAYBE_COHERENT */
{
_dma_cache_wback_inv = r4k_dma_cache_wback_inv; _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
_dma_cache_wback = r4k_dma_cache_wback_inv; _dma_cache_wback = r4k_dma_cache_wback_inv;
_dma_cache_inv = r4k_dma_cache_inv; _dma_cache_inv = r4k_dma_cache_inv;

6
arch/mips/mti-malta/malta-setup.c
View File

@ -98,7 +98,7 @@ static void __init plat_setup_iocoherency(void)
if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
pr_info("Enabled Bonito CPU coherency\n"); pr_info("Enabled Bonito CPU coherency\n");
hw_coherentio = 1; dma_default_coherent = true;
} }
if (strstr(fw_getcmdline(), "iobcuncached")) { if (strstr(fw_getcmdline(), "iobcuncached")) {
BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
@ -118,12 +118,12 @@ static void __init plat_setup_iocoherency(void)
pr_info("CMP IOCU detected\n"); pr_info("CMP IOCU detected\n");
cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU) if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
hw_coherentio = 1; dma_default_coherent = true;
else else
pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
} }
if (hw_coherentio) if (dma_default_coherent)
pr_info("Hardware DMA cache coherency enabled\n"); pr_info("Hardware DMA cache coherency enabled\n");
else else
pr_info("Software DMA cache coherency enabled\n"); pr_info("Software DMA cache coherency enabled\n");

5
arch/mips/pci/pci-alchemy.c
View File

@ -429,9 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev)
ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
/* Au1500 revisions older than AD have borked coherent PCI */ /* Au1500 revisions older than AD have borked coherent PCI */
if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && if (alchemy_get_cputype() == ALCHEMY_CPU_AU1500 &&
(read_c0_prid() < 0x01030202) && read_c0_prid() < 0x01030202 && !dma_default_coherent) {
(coherentio == IO_COHERENCE_DISABLED)) {
val = __raw_readl(ctx->regs + PCI_REG_CONFIG); val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
val |= PCI_CONFIG_NC; val |= PCI_CONFIG_NC;
__raw_writel(val, ctx->regs + PCI_REG_CONFIG); __raw_writel(val, ctx->regs + PCI_REG_CONFIG);