cxl/core: Move register mapping infrastructure
The register mapping infrastructure is large enough to move to its own compilation unit. This also cleans up an unnecessary include of <mem.h> core/bus.c. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162800068975.665205.12895551621746585289.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
06737cd0d2
commit
0f06157e01
@ -42,6 +42,9 @@ CXL Core
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.. kernel-doc:: drivers/cxl/core/pmem.c
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:internal:
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.. kernel-doc:: drivers/cxl/core/regs.c
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:internal:
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External Interfaces
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===================
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@ -4,3 +4,4 @@ obj-$(CONFIG_CXL_BUS) += cxl_core.o
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ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL -I$(srctree)/drivers/cxl
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cxl_core-y := bus.o
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cxl_core-y += pmem.o
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cxl_core-y += regs.o
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@ -550,234 +550,6 @@ err:
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}
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EXPORT_SYMBOL_GPL(devm_cxl_add_decoder);
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/**
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* cxl_probe_component_regs() - Detect CXL Component register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping containing the HDM Decoder Capability Header
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* @map: Map object describing the register block information found
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*
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* See CXL 2.0 8.2.4 Component Register Layout and Definition
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* See CXL 2.0 8.2.5.5 CXL Device Register Interface
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*
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* Probe for component register information and return it in map object.
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*/
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void cxl_probe_component_regs(struct device *dev, void __iomem *base,
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struct cxl_component_reg_map *map)
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{
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int cap, cap_count;
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u64 cap_array;
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*map = (struct cxl_component_reg_map) { 0 };
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/*
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* CXL.cache and CXL.mem registers are at offset 0x1000 as defined in
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* CXL 2.0 8.2.4 Table 141.
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*/
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base += CXL_CM_OFFSET;
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cap_array = readq(base + CXL_CM_CAP_HDR_OFFSET);
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if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) {
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dev_err(dev,
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"Couldn't locate the CXL.cache and CXL.mem capability array header./n");
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return;
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}
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/* It's assumed that future versions will be backward compatible */
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cap_count = FIELD_GET(CXL_CM_CAP_HDR_ARRAY_SIZE_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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void __iomem *register_block;
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u32 hdr;
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int decoder_cnt;
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u16 cap_id, offset;
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u32 length;
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hdr = readl(base + cap * 0x4);
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cap_id = FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, hdr);
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offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr);
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register_block = base + offset;
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switch (cap_id) {
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case CXL_CM_CAP_CAP_ID_HDM:
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dev_dbg(dev, "found HDM decoder capability (0x%x)\n",
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offset);
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hdr = readl(register_block);
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decoder_cnt = cxl_hdm_decoder_count(hdr);
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length = 0x20 * decoder_cnt + 0x10;
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map->hdm_decoder.valid = true;
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map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
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map->hdm_decoder.size = length;
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break;
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default:
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dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
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offset);
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break;
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}
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}
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}
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EXPORT_SYMBOL_GPL(cxl_probe_component_regs);
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/**
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* cxl_probe_device_regs() - Detect CXL Device register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
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* @map: Map object describing the register block information found
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*
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* Probe for device register information and return it in map object.
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*/
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void cxl_probe_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_reg_map *map)
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{
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int cap, cap_count;
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u64 cap_array;
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*map = (struct cxl_device_reg_map){ 0 };
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cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET);
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if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) !=
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CXLDEV_CAP_ARRAY_CAP_ID)
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return;
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cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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u32 offset, length;
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u16 cap_id;
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cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
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readl(base + cap * 0x10));
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offset = readl(base + cap * 0x10 + 0x4);
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length = readl(base + cap * 0x10 + 0x8);
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switch (cap_id) {
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case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
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dev_dbg(dev, "found Status capability (0x%x)\n", offset);
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map->status.valid = true;
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map->status.offset = offset;
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map->status.size = length;
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break;
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case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
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dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
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map->mbox.valid = true;
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map->mbox.offset = offset;
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map->mbox.size = length;
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break;
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case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
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dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
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break;
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case CXLDEV_CAP_CAP_ID_MEMDEV:
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dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
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map->memdev.valid = true;
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map->memdev.offset = offset;
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map->memdev.size = length;
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break;
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default:
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if (cap_id >= 0x8000)
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dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset);
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else
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dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset);
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break;
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}
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}
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}
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EXPORT_SYMBOL_GPL(cxl_probe_device_regs);
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static void __iomem *devm_cxl_iomap_block(struct device *dev,
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resource_size_t addr,
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resource_size_t length)
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{
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void __iomem *ret_val;
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struct resource *res;
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res = devm_request_mem_region(dev, addr, length, dev_name(dev));
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if (!res) {
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resource_size_t end = addr + length - 1;
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dev_err(dev, "Failed to request region %pa-%pa\n", &addr, &end);
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return NULL;
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}
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ret_val = devm_ioremap(dev, addr, length);
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if (!ret_val)
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dev_err(dev, "Failed to map region %pr\n", res);
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return ret_val;
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}
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int cxl_map_component_regs(struct pci_dev *pdev,
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struct cxl_component_regs *regs,
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struct cxl_register_map *map)
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{
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struct device *dev = &pdev->dev;
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resource_size_t phys_addr;
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resource_size_t length;
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phys_addr = pci_resource_start(pdev, map->barno);
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phys_addr += map->block_offset;
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phys_addr += map->component_map.hdm_decoder.offset;
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length = map->component_map.hdm_decoder.size;
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regs->hdm_decoder = devm_cxl_iomap_block(dev, phys_addr, length);
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if (!regs->hdm_decoder)
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return -ENOMEM;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cxl_map_component_regs);
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int cxl_map_device_regs(struct pci_dev *pdev,
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struct cxl_device_regs *regs,
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struct cxl_register_map *map)
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{
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struct device *dev = &pdev->dev;
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resource_size_t phys_addr;
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phys_addr = pci_resource_start(pdev, map->barno);
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phys_addr += map->block_offset;
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if (map->device_map.status.valid) {
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resource_size_t addr;
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resource_size_t length;
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addr = phys_addr + map->device_map.status.offset;
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length = map->device_map.status.size;
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regs->status = devm_cxl_iomap_block(dev, addr, length);
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if (!regs->status)
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return -ENOMEM;
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}
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if (map->device_map.mbox.valid) {
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resource_size_t addr;
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resource_size_t length;
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addr = phys_addr + map->device_map.mbox.offset;
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length = map->device_map.mbox.size;
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regs->mbox = devm_cxl_iomap_block(dev, addr, length);
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if (!regs->mbox)
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return -ENOMEM;
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}
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if (map->device_map.memdev.valid) {
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resource_size_t addr;
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resource_size_t length;
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addr = phys_addr + map->device_map.memdev.offset;
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length = map->device_map.memdev.size;
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regs->memdev = devm_cxl_iomap_block(dev, addr, length);
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if (!regs->memdev)
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return -ENOMEM;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(cxl_map_device_regs);
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/**
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* __cxl_driver_register - register a driver for the cxl bus
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* @cxl_drv: cxl driver structure to attach
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236
drivers/cxl/core/regs.c
Normal file
236
drivers/cxl/core/regs.c
Normal file
@ -0,0 +1,236 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. */
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <cxlmem.h>
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/**
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* cxl_probe_component_regs() - Detect CXL Component register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping containing the HDM Decoder Capability Header
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* @map: Map object describing the register block information found
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*
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* See CXL 2.0 8.2.4 Component Register Layout and Definition
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* See CXL 2.0 8.2.5.5 CXL Device Register Interface
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*
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* Probe for component register information and return it in map object.
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*/
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void cxl_probe_component_regs(struct device *dev, void __iomem *base,
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struct cxl_component_reg_map *map)
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{
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int cap, cap_count;
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u64 cap_array;
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*map = (struct cxl_component_reg_map) { 0 };
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/*
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* CXL.cache and CXL.mem registers are at offset 0x1000 as defined in
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* CXL 2.0 8.2.4 Table 141.
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*/
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base += CXL_CM_OFFSET;
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cap_array = readq(base + CXL_CM_CAP_HDR_OFFSET);
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if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) {
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dev_err(dev,
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"Couldn't locate the CXL.cache and CXL.mem capability array header./n");
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return;
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}
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/* It's assumed that future versions will be backward compatible */
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cap_count = FIELD_GET(CXL_CM_CAP_HDR_ARRAY_SIZE_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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void __iomem *register_block;
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u32 hdr;
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int decoder_cnt;
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u16 cap_id, offset;
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u32 length;
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hdr = readl(base + cap * 0x4);
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cap_id = FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, hdr);
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offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr);
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register_block = base + offset;
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switch (cap_id) {
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case CXL_CM_CAP_CAP_ID_HDM:
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dev_dbg(dev, "found HDM decoder capability (0x%x)\n",
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offset);
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hdr = readl(register_block);
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decoder_cnt = cxl_hdm_decoder_count(hdr);
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length = 0x20 * decoder_cnt + 0x10;
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map->hdm_decoder.valid = true;
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map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
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map->hdm_decoder.size = length;
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break;
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default:
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dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
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offset);
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break;
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}
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}
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}
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EXPORT_SYMBOL_GPL(cxl_probe_component_regs);
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/**
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* cxl_probe_device_regs() - Detect CXL Device register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
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* @map: Map object describing the register block information found
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*
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* Probe for device register information and return it in map object.
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*/
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void cxl_probe_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_reg_map *map)
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{
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int cap, cap_count;
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u64 cap_array;
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*map = (struct cxl_device_reg_map){ 0 };
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cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET);
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if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) !=
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CXLDEV_CAP_ARRAY_CAP_ID)
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return;
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cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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u32 offset, length;
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u16 cap_id;
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cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
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readl(base + cap * 0x10));
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offset = readl(base + cap * 0x10 + 0x4);
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length = readl(base + cap * 0x10 + 0x8);
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switch (cap_id) {
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case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
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dev_dbg(dev, "found Status capability (0x%x)\n", offset);
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map->status.valid = true;
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map->status.offset = offset;
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map->status.size = length;
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break;
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case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
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dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
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map->mbox.valid = true;
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map->mbox.offset = offset;
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map->mbox.size = length;
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break;
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case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
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dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
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break;
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case CXLDEV_CAP_CAP_ID_MEMDEV:
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dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
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map->memdev.valid = true;
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map->memdev.offset = offset;
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map->memdev.size = length;
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break;
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default:
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if (cap_id >= 0x8000)
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dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset);
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else
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dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset);
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break;
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}
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}
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}
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EXPORT_SYMBOL_GPL(cxl_probe_device_regs);
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static void __iomem *devm_cxl_iomap_block(struct device *dev,
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resource_size_t addr,
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resource_size_t length)
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{
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void __iomem *ret_val;
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struct resource *res;
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res = devm_request_mem_region(dev, addr, length, dev_name(dev));
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if (!res) {
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resource_size_t end = addr + length - 1;
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dev_err(dev, "Failed to request region %pa-%pa\n", &addr, &end);
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return NULL;
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}
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ret_val = devm_ioremap(dev, addr, length);
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if (!ret_val)
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dev_err(dev, "Failed to map region %pr\n", res);
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return ret_val;
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}
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int cxl_map_component_regs(struct pci_dev *pdev,
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struct cxl_component_regs *regs,
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struct cxl_register_map *map)
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{
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struct device *dev = &pdev->dev;
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resource_size_t phys_addr;
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resource_size_t length;
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phys_addr = pci_resource_start(pdev, map->barno);
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phys_addr += map->block_offset;
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phys_addr += map->component_map.hdm_decoder.offset;
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length = map->component_map.hdm_decoder.size;
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regs->hdm_decoder = devm_cxl_iomap_block(dev, phys_addr, length);
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if (!regs->hdm_decoder)
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return -ENOMEM;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cxl_map_component_regs);
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int cxl_map_device_regs(struct pci_dev *pdev,
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struct cxl_device_regs *regs,
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struct cxl_register_map *map)
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{
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struct device *dev = &pdev->dev;
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resource_size_t phys_addr;
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phys_addr = pci_resource_start(pdev, map->barno);
|
||||
phys_addr += map->block_offset;
|
||||
|
||||
if (map->device_map.status.valid) {
|
||||
resource_size_t addr;
|
||||
resource_size_t length;
|
||||
|
||||
addr = phys_addr + map->device_map.status.offset;
|
||||
length = map->device_map.status.size;
|
||||
regs->status = devm_cxl_iomap_block(dev, addr, length);
|
||||
if (!regs->status)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (map->device_map.mbox.valid) {
|
||||
resource_size_t addr;
|
||||
resource_size_t length;
|
||||
|
||||
addr = phys_addr + map->device_map.mbox.offset;
|
||||
length = map->device_map.mbox.size;
|
||||
regs->mbox = devm_cxl_iomap_block(dev, addr, length);
|
||||
if (!regs->mbox)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (map->device_map.memdev.valid) {
|
||||
resource_size_t addr;
|
||||
resource_size_t length;
|
||||
|
||||
addr = phys_addr + map->device_map.memdev.offset;
|
||||
length = map->device_map.memdev.size;
|
||||
regs->memdev = devm_cxl_iomap_block(dev, addr, length);
|
||||
if (!regs->memdev)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cxl_map_device_regs);
|
||||
Loading…
Reference in New Issue
Block a user