From 70115558ab02fe8d28a6634350b3491a542aaa02 Mon Sep 17 00:00:00 2001 From: Jaehyoung Choi Date: Fri, 30 Jul 2021 22:29:05 +0300 Subject: [PATCH 1/3] pinctrl: samsung: Fix pinctrl bank pin count Commit 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") changes the order of GPIO and pinctrl registration: now pinctrl is registered before GPIO. That means gpio_chip->ngpio is not set when samsung_pinctrl_register() called, and one cannot rely on that value anymore. Use `pin_bank->nr_pins' instead of `pin_bank->gpio_chip.ngpio' to fix mentioned inconsistency. Fixes: 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") Signed-off-by: Jaehyoung Choi Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20210730192905.7173-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 376876bd6605..2975b4369f32 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -918,7 +918,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev, pin_bank->grange.pin_base = drvdata->pin_base + pin_bank->pin_base; pin_bank->grange.base = pin_bank->grange.pin_base; - pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; + pin_bank->grange.npins = pin_bank->nr_pins; pin_bank->grange.gc = &pin_bank->gpio_chip; pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); } From 71b833b329d65236285cc73f4528f08c7d3c274c Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 11 Aug 2021 14:48:21 +0300 Subject: [PATCH 2/3] dt-bindings: pinctrl: samsung: Add Exynos850 doc Document compatible string for Exynos850 SoC. Nothing else is changed, as Exynos850 SoC uses already existing samsung pinctrl driver. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20210811114827.27322-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 38a1416fd2cd..e7a1b1880375 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -22,6 +22,7 @@ Required Properties: - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. + - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of the address space it occupies. From cdd3d945dcec0d0dab845175dc9400ab54512aa6 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 11 Aug 2021 14:48:22 +0300 Subject: [PATCH 3/3] pinctrl: samsung: Add Exynos850 SoC specific data Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20210811114827.27322-3-semen.protsenko@linaro.org [krzysztof: lower-case the hex-numbers] Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 116 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 29 +++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 148 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b6e56422a700..fe5f6046fbd5 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), + EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), + EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), + EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), + EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { + .ctrl = exynos850_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index da1ec13697e7..bfad1ced8017 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -108,6 +108,35 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2975b4369f32..2a0fc63516f1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos850-pinctrl", + .data = &exynos850_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index de44f8ec330b..4c2149e9c544 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;