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kernel-ark/arch/powerpc/boot/dts/p1020rdb.dts

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powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
/*
* P1020 RDB Device Tree Source
*
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 04:47:45 +00:00
* Copyright 2009-2011 Freescale Semiconductor Inc.
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
powerpc/85xx: Rework P1020RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 07:21:09 +00:00
/include/ "fsl/p1020si-pre.dtsi"
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
/ {
powerpc/85xx: P1020 DTS : re-organize dts files Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts files for P1020 based systems to use dtsi file Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Grant Likely <grant.likelY@secretlab.ca> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-07 09:10:55 +00:00
model = "fsl,P1020RDB";
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
compatible = "fsl,P1020RDB";
memory {
device_type = "memory";
};
powerpc/85xx: Rework P1020RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 07:21:09 +00:00
board_lbc: lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xffa00000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000>;
};
powerpc/85xx: Rework P1020RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 07:21:09 +00:00
board_soc: soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 04:47:45 +00:00
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
powerpc/85xx: Rework PCI nodes on P1020RDB * Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-19 15:58:05 +00:00
reg = <0 0xffe09000 0 0x1000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
powerpc/85xx: Rework PCI nodes on P1020RDB * Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-19 15:58:05 +00:00
reg = <0 0xffe0a000 0 0x1000>;
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 04:47:45 +00:00
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
pcie@0 {
powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-25 04:47:45 +00:00
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
powerpc/85xx: Added P1020RDB Platform support. P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-25 04:20:28 +00:00
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
powerpc/85xx: Rework P1020RDB device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 07:21:09 +00:00
/include/ "p1020rdb.dtsi"
/include/ "fsl/p1020si-post.dtsi"
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