kernel-ark/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 L2-cache Control Block

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description: |
  By means of the System Controller Baikal-T1 SoC exposes a few settings to
  tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
  to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
  L2-cache controller block is responsible for the tuning. Its DT node is
  supposed to be a child of the system controller.

properties:
  compatible:
    const: baikal,bt1-l2-ctl

  reg:
    maxItems: 1

  baikal,l2-ws-latency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Cycles of latency for Way-select RAM accesses
    default: 0
    minimum: 0
    maximum: 3

  baikal,l2-tag-latency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Cycles of latency for Tag RAM accesses
    default: 0
    minimum: 0
    maximum: 3

  baikal,l2-data-latency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Cycles of latency for Data RAM accesses
    default: 1
    minimum: 0
    maximum: 3

additionalProperties: false

required:
  - compatible

examples:
  - |
    l2@1f04d028 {
      compatible = "baikal,bt1-l2-ctl";
      reg = <0x1f04d028 0x004>;

      baikal,l2-ws-latency = <1>;
      baikal,l2-tag-latency = <1>;
      baikal,l2-data-latency = <2>;
    };
...