2005-04-16 22:20:36 +00:00
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/*
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* Intel IO-APIC support for multi-Pentium hosts.
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*
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* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
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*
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* Many thanks to Stig Venaas for trying out countless experimental
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* patches and reporting/debugging problems patiently!
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*
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* (c) 1999, Multiple IO-APIC support, developed by
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* Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
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* Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
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* further tested and cleaned up by Zach Brown <zab@redhat.com>
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* and Ingo Molnar <mingo@redhat.com>
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*
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* Fixes
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* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
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* thanks to Eric Gilmore
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* and Rolf G. Tews
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* for testing these extensively
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* Paul Diefenbaugh : Added full ACPI support
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*/
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/smp_lock.h>
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2006-10-04 09:16:42 +00:00
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#include <linux/pci.h>
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2005-04-16 22:20:36 +00:00
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#include <linux/mc146818rtc.h>
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#include <linux/acpi.h>
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#include <linux/sysdev.h>
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2006-10-04 09:16:59 +00:00
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#include <linux/msi.h>
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2006-10-04 09:17:01 +00:00
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#include <linux/htirq.h>
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2006-02-16 22:42:04 +00:00
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#ifdef CONFIG_ACPI
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#include <acpi/acpi_bus.h>
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#endif
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2005-04-16 22:20:36 +00:00
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/desc.h>
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#include <asm/proto.h>
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#include <asm/mach_apic.h>
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2005-05-31 21:39:26 +00:00
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#include <asm/acpi.h>
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2006-01-11 21:44:27 +00:00
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#include <asm/dma.h>
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2006-06-26 11:57:01 +00:00
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#include <asm/nmi.h>
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2006-10-04 09:16:42 +00:00
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#include <asm/msidef.h>
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2006-10-04 09:16:55 +00:00
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#include <asm/hypertransport.h>
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2005-04-16 22:20:36 +00:00
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2006-10-08 13:47:55 +00:00
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static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
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2006-10-04 09:16:46 +00:00
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2005-04-16 22:20:36 +00:00
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#define __apicdebuginit __init
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int sis_apic_bug; /* not actually supported, dummy for compile */
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2005-05-20 21:27:59 +00:00
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static int no_timer_check;
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2006-09-26 08:52:32 +00:00
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static int disable_timer_pin_1 __initdata;
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2005-09-12 16:49:25 +00:00
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2006-03-25 15:30:46 +00:00
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int timer_over_8254 __initdata = 0;
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2006-02-26 03:18:52 +00:00
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2006-01-11 21:46:06 +00:00
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/* Where if anywhere is the i8259 connect in external int mode */
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static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
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2005-04-16 22:20:36 +00:00
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static DEFINE_SPINLOCK(ioapic_lock);
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2006-06-26 11:56:43 +00:00
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static DEFINE_SPINLOCK(vector_lock);
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2005-04-16 22:20:36 +00:00
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/*
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* # of IRQ routing registers
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*/
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int nr_ioapic_registers[MAX_IO_APICS];
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/*
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* Rough estimation of how many shared IRQs there are, can
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* be changed anytime.
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*/
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2005-11-05 16:25:53 +00:00
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#define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
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2005-04-16 22:20:36 +00:00
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#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
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/*
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* This is performance-critical, we want to do it O(1)
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*
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* the indexing order of this array favors 1:1 mappings
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* between pins and IRQs.
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*/
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static struct irq_pin_list {
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short apic, pin, next;
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} irq_2_pin[PIN_MAP_SIZE];
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|
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
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#define __DO_ACTION(R, ACTION, FINAL) \
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\
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{ \
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int pin; \
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struct irq_pin_list *entry = irq_2_pin + irq; \
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\
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2005-11-05 16:25:53 +00:00
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BUG_ON(irq >= NR_IRQS); \
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
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for (;;) { \
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unsigned int reg; \
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pin = entry->pin; \
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if (pin == -1) \
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break; \
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reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
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reg ACTION; \
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io_apic_modify(entry->apic, reg); \
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if (!entry->next) \
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break; \
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entry = irq_2_pin + entry->next; \
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} \
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FINAL; \
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}
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|
2006-09-26 08:52:30 +00:00
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union entry_union {
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struct { u32 w1, w2; };
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struct IO_APIC_route_entry entry;
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};
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static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
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{
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union entry_union eu;
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unsigned long flags;
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spin_lock_irqsave(&ioapic_lock, flags);
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eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
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eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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return eu.entry;
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}
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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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|
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{
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unsigned long flags;
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union entry_union eu;
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eu.entry = e;
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spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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io_apic_write(apic, 0x11 + 2*pin, eu.w2);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
|
|
|
|
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2006-10-04 09:16:51 +00:00
|
|
|
static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
|
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|
|
{
|
|
|
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int apic, pin;
|
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struct irq_pin_list *entry = irq_2_pin + irq;
|
|
|
|
|
|
|
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BUG_ON(irq >= NR_IRQS);
|
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|
|
for (;;) {
|
|
|
|
unsigned int reg;
|
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|
|
apic = entry->apic;
|
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|
|
pin = entry->pin;
|
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|
|
if (pin == -1)
|
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|
|
break;
|
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|
|
io_apic_write(apic, 0x11 + pin*2, dest);
|
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|
|
reg = io_apic_read(apic, 0x10 + pin*2);
|
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|
|
reg &= ~0x000000ff;
|
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|
|
reg |= vector;
|
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io_apic_modify(apic, reg);
|
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|
|
if (!entry->next)
|
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|
|
break;
|
|
|
|
entry = irq_2_pin + entry->next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
unsigned int dest;
|
|
|
|
cpumask_t tmp;
|
2006-10-04 09:16:51 +00:00
|
|
|
int vector;
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
|
|
|
|
cpus_and(tmp, mask, cpu_online_map);
|
|
|
|
if (cpus_empty(tmp))
|
|
|
|
tmp = TARGET_CPUS;
|
|
|
|
|
|
|
|
cpus_and(mask, tmp, CPU_MASK_ALL);
|
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(irq, mask, &tmp);
|
2006-10-04 09:16:51 +00:00
|
|
|
if (vector < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dest = cpu_mask_to_apicid(tmp);
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Only the high 8 bits are valid.
|
|
|
|
*/
|
|
|
|
dest = SET_APIC_LOGICAL_ID(dest);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
2006-10-08 13:47:55 +00:00
|
|
|
__target_IO_APIC_irq(irq, dest, vector);
|
2006-10-04 09:16:46 +00:00
|
|
|
set_native_irq_info(irq, mask);
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* The common case is 1:1 IRQ<->pin mappings. Sometimes there are
|
|
|
|
* shared ISA-space IRQs, so we have to support them. We are super
|
|
|
|
* fast in the common case, and fast for shared ISA-space IRQs.
|
|
|
|
*/
|
|
|
|
static void add_pin_to_irq(unsigned int irq, int apic, int pin)
|
|
|
|
{
|
|
|
|
static int first_free_entry = NR_IRQS;
|
|
|
|
struct irq_pin_list *entry = irq_2_pin + irq;
|
|
|
|
|
2005-11-05 16:25:53 +00:00
|
|
|
BUG_ON(irq >= NR_IRQS);
|
2005-04-16 22:20:36 +00:00
|
|
|
while (entry->next)
|
|
|
|
entry = irq_2_pin + entry->next;
|
|
|
|
|
|
|
|
if (entry->pin != -1) {
|
|
|
|
entry->next = first_free_entry;
|
|
|
|
entry = irq_2_pin + entry->next;
|
|
|
|
if (++first_free_entry >= PIN_MAP_SIZE)
|
2005-11-05 16:25:53 +00:00
|
|
|
panic("io_apic.c: ran out of irq_2_pin entries!");
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
entry->apic = apic;
|
|
|
|
entry->pin = pin;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#define DO_ACTION(name,R,ACTION, FINAL) \
|
|
|
|
\
|
|
|
|
static void name##_IO_APIC_irq (unsigned int irq) \
|
|
|
|
__DO_ACTION(R, ACTION, FINAL)
|
|
|
|
|
|
|
|
DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
|
|
|
|
/* mask = 1 */
|
|
|
|
DO_ACTION( __unmask, 0, &= 0xfffeffff, )
|
|
|
|
/* mask = 0 */
|
|
|
|
|
|
|
|
static void mask_IO_APIC_irq (unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
|
__mask_IO_APIC_irq(irq);
|
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void unmask_IO_APIC_irq (unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
|
__unmask_IO_APIC_irq(irq);
|
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
|
|
|
|
{
|
|
|
|
struct IO_APIC_route_entry entry;
|
|
|
|
|
|
|
|
/* Check delivery_mode to be sure we're not clearing an SMI pin */
|
2006-09-26 08:52:30 +00:00
|
|
|
entry = ioapic_read_entry(apic, pin);
|
2005-04-16 22:20:36 +00:00
|
|
|
if (entry.delivery_mode == dest_SMI)
|
|
|
|
return;
|
|
|
|
/*
|
|
|
|
* Disable it in the IO-APIC irq-routing table:
|
|
|
|
*/
|
|
|
|
memset(&entry, 0, sizeof(entry));
|
|
|
|
entry.mask = 1;
|
2006-09-26 08:52:30 +00:00
|
|
|
ioapic_write_entry(apic, pin, entry);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void clear_IO_APIC (void)
|
|
|
|
{
|
|
|
|
int apic, pin;
|
|
|
|
|
|
|
|
for (apic = 0; apic < nr_ioapics; apic++)
|
|
|
|
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
|
|
|
|
clear_IO_APIC_pin(apic, pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
int skip_ioapic_setup;
|
|
|
|
int ioapic_force;
|
|
|
|
|
|
|
|
/* dummy parsing: see setup.c */
|
|
|
|
|
|
|
|
static int __init disable_ioapic_setup(char *str)
|
|
|
|
{
|
|
|
|
skip_ioapic_setup = 1;
|
2006-09-26 08:52:32 +00:00
|
|
|
return 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2006-09-26 08:52:32 +00:00
|
|
|
early_param("noapic", disable_ioapic_setup);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-09-26 08:52:32 +00:00
|
|
|
/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
|
|
|
|
static int __init disable_timer_pin_setup(char *arg)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2006-09-26 08:52:32 +00:00
|
|
|
disable_timer_pin_1 = 1;
|
2005-04-16 22:20:36 +00:00
|
|
|
return 1;
|
|
|
|
}
|
2006-09-26 08:52:32 +00:00
|
|
|
__setup("disable_timer_pin_1", disable_timer_pin_setup);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-02-26 03:18:52 +00:00
|
|
|
static int __init setup_disable_8254_timer(char *s)
|
|
|
|
{
|
|
|
|
timer_over_8254 = -1;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
static int __init setup_enable_8254_timer(char *s)
|
|
|
|
{
|
|
|
|
timer_over_8254 = 2;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
__setup("disable_8254_timer", setup_disable_8254_timer);
|
|
|
|
__setup("enable_8254_timer", setup_enable_8254_timer);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Find the IRQ entry number of a certain pin.
|
|
|
|
*/
|
|
|
|
static int find_irq_entry(int apic, int pin, int type)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < mp_irq_entries; i++)
|
|
|
|
if (mp_irqs[i].mpc_irqtype == type &&
|
|
|
|
(mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
|
|
|
|
mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
|
|
|
|
mp_irqs[i].mpc_dstirq == pin)
|
|
|
|
return i;
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Find the pin to which IRQ[irq] (ISA) is connected
|
|
|
|
*/
|
2006-01-11 21:46:06 +00:00
|
|
|
static int __init find_isa_irq_pin(int irq, int type)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < mp_irq_entries; i++) {
|
|
|
|
int lbus = mp_irqs[i].mpc_srcbus;
|
|
|
|
|
2006-09-26 08:52:30 +00:00
|
|
|
if (test_bit(lbus, mp_bus_not_pci) &&
|
2005-04-16 22:20:36 +00:00
|
|
|
(mp_irqs[i].mpc_irqtype == type) &&
|
|
|
|
(mp_irqs[i].mpc_srcbusirq == irq))
|
|
|
|
|
|
|
|
return mp_irqs[i].mpc_dstirq;
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2006-01-11 21:46:06 +00:00
|
|
|
static int __init find_isa_irq_apic(int irq, int type)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < mp_irq_entries; i++) {
|
|
|
|
int lbus = mp_irqs[i].mpc_srcbus;
|
|
|
|
|
2006-09-26 08:52:30 +00:00
|
|
|
if (test_bit(lbus, mp_bus_not_pci) &&
|
2006-01-11 21:46:06 +00:00
|
|
|
(mp_irqs[i].mpc_irqtype == type) &&
|
|
|
|
(mp_irqs[i].mpc_srcbusirq == irq))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (i < mp_irq_entries) {
|
|
|
|
int apic;
|
|
|
|
for(apic = 0; apic < nr_ioapics; apic++) {
|
|
|
|
if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
|
|
|
|
return apic;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Find a specific PCI IRQ entry.
|
|
|
|
* Not an __init, possibly needed by modules
|
|
|
|
*/
|
|
|
|
static int pin_2_irq(int idx, int apic, int pin);
|
|
|
|
|
|
|
|
int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
|
|
|
|
{
|
|
|
|
int apic, i, best_guess = -1;
|
|
|
|
|
|
|
|
apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
|
|
|
|
bus, slot, pin);
|
|
|
|
if (mp_bus_id_to_pci_bus[bus] == -1) {
|
|
|
|
apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
for (i = 0; i < mp_irq_entries; i++) {
|
|
|
|
int lbus = mp_irqs[i].mpc_srcbus;
|
|
|
|
|
|
|
|
for (apic = 0; apic < nr_ioapics; apic++)
|
|
|
|
if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
|
|
|
|
mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
|
|
|
|
break;
|
|
|
|
|
2006-09-26 08:52:30 +00:00
|
|
|
if (!test_bit(lbus, mp_bus_not_pci) &&
|
2005-04-16 22:20:36 +00:00
|
|
|
!mp_irqs[i].mpc_irqtype &&
|
|
|
|
(bus == lbus) &&
|
|
|
|
(slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
|
|
|
|
int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
|
|
|
|
|
|
|
|
if (!(apic || IO_APIC_IRQ(irq)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
|
|
|
|
return irq;
|
|
|
|
/*
|
|
|
|
* Use the first all-but-pin matching entry as a
|
|
|
|
* best-guess fuzzy result for broken mptables.
|
|
|
|
*/
|
|
|
|
if (best_guess < 0)
|
|
|
|
best_guess = irq;
|
|
|
|
}
|
|
|
|
}
|
2005-11-05 16:25:53 +00:00
|
|
|
BUG_ON(best_guess >= NR_IRQS);
|
2005-04-16 22:20:36 +00:00
|
|
|
return best_guess;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ISA interrupts are always polarity zero edge triggered,
|
|
|
|
* when listed as conforming in the MP table. */
|
|
|
|
|
|
|
|
#define default_ISA_trigger(idx) (0)
|
|
|
|
#define default_ISA_polarity(idx) (0)
|
|
|
|
|
|
|
|
/* PCI interrupts are always polarity one level triggered,
|
|
|
|
* when listed as conforming in the MP table. */
|
|
|
|
|
|
|
|
#define default_PCI_trigger(idx) (1)
|
|
|
|
#define default_PCI_polarity(idx) (1)
|
|
|
|
|
|
|
|
static int __init MPBIOS_polarity(int idx)
|
|
|
|
{
|
|
|
|
int bus = mp_irqs[idx].mpc_srcbus;
|
|
|
|
int polarity;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Determine IRQ line polarity (high active or low active):
|
|
|
|
*/
|
|
|
|
switch (mp_irqs[idx].mpc_irqflag & 3)
|
|
|
|
{
|
|
|
|
case 0: /* conforms, ie. bus-type dependent polarity */
|
2006-09-26 08:52:30 +00:00
|
|
|
if (test_bit(bus, mp_bus_not_pci))
|
|
|
|
polarity = default_ISA_polarity(idx);
|
|
|
|
else
|
|
|
|
polarity = default_PCI_polarity(idx);
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
|
|
|
case 1: /* high active */
|
|
|
|
{
|
|
|
|
polarity = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: /* reserved */
|
|
|
|
{
|
|
|
|
printk(KERN_WARNING "broken BIOS!!\n");
|
|
|
|
polarity = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3: /* low active */
|
|
|
|
{
|
|
|
|
polarity = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: /* invalid */
|
|
|
|
{
|
|
|
|
printk(KERN_WARNING "broken BIOS!!\n");
|
|
|
|
polarity = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return polarity;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int MPBIOS_trigger(int idx)
|
|
|
|
{
|
|
|
|
int bus = mp_irqs[idx].mpc_srcbus;
|
|
|
|
int trigger;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Determine IRQ trigger mode (edge or level sensitive):
|
|
|
|
*/
|
|
|
|
switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
|
|
|
|
{
|
|
|
|
case 0: /* conforms, ie. bus-type dependent */
|
2006-09-26 08:52:30 +00:00
|
|
|
if (test_bit(bus, mp_bus_not_pci))
|
|
|
|
trigger = default_ISA_trigger(idx);
|
|
|
|
else
|
|
|
|
trigger = default_PCI_trigger(idx);
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
|
|
|
case 1: /* edge */
|
|
|
|
{
|
|
|
|
trigger = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: /* reserved */
|
|
|
|
{
|
|
|
|
printk(KERN_WARNING "broken BIOS!!\n");
|
|
|
|
trigger = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 3: /* level */
|
|
|
|
{
|
|
|
|
trigger = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default: /* invalid */
|
|
|
|
{
|
|
|
|
printk(KERN_WARNING "broken BIOS!!\n");
|
|
|
|
trigger = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return trigger;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int irq_polarity(int idx)
|
|
|
|
{
|
|
|
|
return MPBIOS_polarity(idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int irq_trigger(int idx)
|
|
|
|
{
|
|
|
|
return MPBIOS_trigger(idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pin_2_irq(int idx, int apic, int pin)
|
|
|
|
{
|
|
|
|
int irq, i;
|
|
|
|
int bus = mp_irqs[idx].mpc_srcbus;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Debugging check, we are in big trouble if this message pops up!
|
|
|
|
*/
|
|
|
|
if (mp_irqs[idx].mpc_dstirq != pin)
|
|
|
|
printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
|
|
|
|
|
2006-09-26 08:52:30 +00:00
|
|
|
if (test_bit(bus, mp_bus_not_pci)) {
|
|
|
|
irq = mp_irqs[idx].mpc_srcbusirq;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* PCI IRQs are mapped in order
|
|
|
|
*/
|
|
|
|
i = irq = 0;
|
|
|
|
while (i < apic)
|
|
|
|
irq += nr_ioapic_registers[i++];
|
|
|
|
irq += pin;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2005-11-05 16:25:53 +00:00
|
|
|
BUG_ON(irq >= NR_IRQS);
|
2005-04-16 22:20:36 +00:00
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int IO_APIC_irq_trigger(int irq)
|
|
|
|
{
|
|
|
|
int apic, idx, pin;
|
|
|
|
|
|
|
|
for (apic = 0; apic < nr_ioapics; apic++) {
|
|
|
|
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
|
|
|
|
idx = find_irq_entry(apic,pin,mp_INT);
|
|
|
|
if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
|
|
|
|
return irq_trigger(idx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* nonexistent IRQs are edge default
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
|
2006-10-08 13:47:55 +00:00
|
|
|
static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
|
|
|
|
[0] = FIRST_EXTERNAL_VECTOR + 0,
|
|
|
|
[1] = FIRST_EXTERNAL_VECTOR + 1,
|
|
|
|
[2] = FIRST_EXTERNAL_VECTOR + 2,
|
|
|
|
[3] = FIRST_EXTERNAL_VECTOR + 3,
|
|
|
|
[4] = FIRST_EXTERNAL_VECTOR + 4,
|
|
|
|
[5] = FIRST_EXTERNAL_VECTOR + 5,
|
|
|
|
[6] = FIRST_EXTERNAL_VECTOR + 6,
|
|
|
|
[7] = FIRST_EXTERNAL_VECTOR + 7,
|
|
|
|
[8] = FIRST_EXTERNAL_VECTOR + 8,
|
|
|
|
[9] = FIRST_EXTERNAL_VECTOR + 9,
|
|
|
|
[10] = FIRST_EXTERNAL_VECTOR + 10,
|
|
|
|
[11] = FIRST_EXTERNAL_VECTOR + 11,
|
|
|
|
[12] = FIRST_EXTERNAL_VECTOR + 12,
|
|
|
|
[13] = FIRST_EXTERNAL_VECTOR + 13,
|
|
|
|
[14] = FIRST_EXTERNAL_VECTOR + 14,
|
|
|
|
[15] = FIRST_EXTERNAL_VECTOR + 15,
|
|
|
|
};
|
|
|
|
|
|
|
|
static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
|
|
|
|
[0] = CPU_MASK_ALL,
|
|
|
|
[1] = CPU_MASK_ALL,
|
|
|
|
[2] = CPU_MASK_ALL,
|
|
|
|
[3] = CPU_MASK_ALL,
|
|
|
|
[4] = CPU_MASK_ALL,
|
|
|
|
[5] = CPU_MASK_ALL,
|
|
|
|
[6] = CPU_MASK_ALL,
|
|
|
|
[7] = CPU_MASK_ALL,
|
|
|
|
[8] = CPU_MASK_ALL,
|
|
|
|
[9] = CPU_MASK_ALL,
|
|
|
|
[10] = CPU_MASK_ALL,
|
|
|
|
[11] = CPU_MASK_ALL,
|
|
|
|
[12] = CPU_MASK_ALL,
|
|
|
|
[13] = CPU_MASK_ALL,
|
|
|
|
[14] = CPU_MASK_ALL,
|
|
|
|
[15] = CPU_MASK_ALL,
|
|
|
|
};
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2006-10-04 09:16:51 +00:00
|
|
|
/*
|
|
|
|
* NOTE! The local APIC isn't very good at handling
|
|
|
|
* multiple interrupts at the same interrupt level.
|
|
|
|
* As the interrupt level is determined by taking the
|
|
|
|
* vector number and shifting that right by 4, we
|
|
|
|
* want to spread these out a bit so that they don't
|
|
|
|
* all fall in the same interrupt level.
|
|
|
|
*
|
|
|
|
* Also, we've got to be careful not to trash gate
|
|
|
|
* 0x80, because int 0x80 is hm, kind of importantish. ;)
|
|
|
|
*/
|
|
|
|
static struct {
|
|
|
|
int vector;
|
|
|
|
int offset;
|
|
|
|
} pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
|
|
|
|
int old_vector = -1;
|
|
|
|
int cpu;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-10-04 09:16:46 +00:00
|
|
|
BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
|
2006-06-26 11:56:43 +00:00
|
|
|
|
2006-10-08 13:43:46 +00:00
|
|
|
if (irq_vector[irq] > 0)
|
|
|
|
old_vector = irq_vector[irq];
|
2006-10-08 13:47:55 +00:00
|
|
|
if (old_vector > 0) {
|
|
|
|
cpus_and(*result, irq_domain[irq], mask);
|
|
|
|
if (!cpus_empty(*result))
|
|
|
|
return old_vector;
|
2006-06-26 11:56:43 +00:00
|
|
|
}
|
2006-10-04 09:16:51 +00:00
|
|
|
|
|
|
|
for_each_cpu_mask(cpu, mask) {
|
2006-10-08 13:47:55 +00:00
|
|
|
cpumask_t domain;
|
|
|
|
int first, new_cpu;
|
2006-10-04 09:16:51 +00:00
|
|
|
int vector, offset;
|
2006-10-08 13:47:55 +00:00
|
|
|
|
|
|
|
domain = vector_allocation_domain(cpu);
|
|
|
|
first = first_cpu(domain);
|
|
|
|
|
|
|
|
vector = pos[first].vector;
|
|
|
|
offset = pos[first].offset;
|
2005-04-16 22:20:36 +00:00
|
|
|
next:
|
2006-10-04 09:16:51 +00:00
|
|
|
vector += 8;
|
|
|
|
if (vector >= FIRST_SYSTEM_VECTOR) {
|
|
|
|
/* If we run out of vectors on large boxen, must share them. */
|
|
|
|
offset = (offset + 1) % 8;
|
|
|
|
vector = FIRST_DEVICE_VECTOR + offset;
|
|
|
|
}
|
2006-10-08 13:47:55 +00:00
|
|
|
if (unlikely(pos[first].vector == vector))
|
2006-10-04 09:16:51 +00:00
|
|
|
continue;
|
|
|
|
if (vector == IA32_SYSCALL_VECTOR)
|
|
|
|
goto next;
|
2006-10-08 13:47:55 +00:00
|
|
|
for_each_cpu_mask(new_cpu, domain)
|
2006-10-21 16:37:01 +00:00
|
|
|
if (per_cpu(vector_irq, new_cpu)[vector] != -1)
|
2006-10-08 13:47:55 +00:00
|
|
|
goto next;
|
2006-10-04 09:16:51 +00:00
|
|
|
/* Found one! */
|
2006-10-08 13:47:55 +00:00
|
|
|
for_each_cpu_mask(new_cpu, domain) {
|
2006-10-21 16:37:01 +00:00
|
|
|
pos[new_cpu].vector = vector;
|
|
|
|
pos[new_cpu].offset = offset;
|
2006-10-08 13:47:55 +00:00
|
|
|
}
|
2006-10-04 09:16:51 +00:00
|
|
|
if (old_vector >= 0) {
|
2006-10-08 13:47:55 +00:00
|
|
|
int old_cpu;
|
2006-10-12 04:44:46 +00:00
|
|
|
for_each_cpu_mask(old_cpu, irq_domain[irq])
|
2006-10-08 13:47:55 +00:00
|
|
|
per_cpu(vector_irq, old_cpu)[old_vector] = -1;
|
2006-10-04 09:16:51 +00:00
|
|
|
}
|
2006-10-08 13:47:55 +00:00
|
|
|
for_each_cpu_mask(new_cpu, domain)
|
|
|
|
per_cpu(vector_irq, new_cpu)[vector] = irq;
|
2006-10-08 13:43:46 +00:00
|
|
|
irq_vector[irq] = vector;
|
2006-10-08 13:47:55 +00:00
|
|
|
irq_domain[irq] = domain;
|
|
|
|
cpus_and(*result, domain, mask);
|
2006-10-04 09:16:51 +00:00
|
|
|
return vector;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2006-10-04 09:16:51 +00:00
|
|
|
return -ENOSPC;
|
2006-10-04 09:16:46 +00:00
|
|
|
}
|
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
|
2006-10-04 09:16:46 +00:00
|
|
|
{
|
|
|
|
int vector;
|
|
|
|
unsigned long flags;
|
2006-06-26 11:56:43 +00:00
|
|
|
|
2006-10-04 09:16:46 +00:00
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = __assign_irq_vector(irq, mask, result);
|
2006-06-26 11:57:16 +00:00
|
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
2006-06-26 11:56:43 +00:00
|
|
|
return vector;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
extern void (*interrupt[NR_IRQS])(void);
|
2006-10-04 09:16:25 +00:00
|
|
|
|
|
|
|
static struct irq_chip ioapic_chip;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
#define IOAPIC_AUTO -1
|
|
|
|
#define IOAPIC_EDGE 0
|
|
|
|
#define IOAPIC_LEVEL 1
|
|
|
|
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 09:24:36 +00:00
|
|
|
static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2006-06-26 11:56:46 +00:00
|
|
|
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
|
|
|
|
trigger == IOAPIC_LEVEL)
|
2006-10-17 07:10:03 +00:00
|
|
|
set_irq_chip_and_handler_name(irq, &ioapic_chip,
|
|
|
|
handle_fasteoi_irq, "fasteoi");
|
2006-06-26 11:56:46 +00:00
|
|
|
else
|
2006-10-17 07:10:03 +00:00
|
|
|
set_irq_chip_and_handler_name(irq, &ioapic_chip,
|
|
|
|
handle_edge_irq, "edge");
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init setup_IO_APIC_irqs(void)
|
|
|
|
{
|
|
|
|
struct IO_APIC_route_entry entry;
|
|
|
|
int apic, pin, idx, irq, first_notcon = 1, vector;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
|
|
|
|
|
|
|
|
for (apic = 0; apic < nr_ioapics; apic++) {
|
|
|
|
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
|
|
|
|
|
|
|
|
/*
|
|
|
|
* add it to the IO-APIC irq-routing table:
|
|
|
|
*/
|
|
|
|
memset(&entry,0,sizeof(entry));
|
|
|
|
|
|
|
|
entry.delivery_mode = INT_DELIVERY_MODE;
|
|
|
|
entry.dest_mode = INT_DEST_MODE;
|
|
|
|
entry.mask = 0; /* enable IRQ */
|
|
|
|
entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
|
|
|
|
|
|
|
|
idx = find_irq_entry(apic,pin,mp_INT);
|
|
|
|
if (idx == -1) {
|
|
|
|
if (first_notcon) {
|
|
|
|
apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
|
|
|
|
first_notcon = 0;
|
|
|
|
} else
|
|
|
|
apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
entry.trigger = irq_trigger(idx);
|
|
|
|
entry.polarity = irq_polarity(idx);
|
|
|
|
|
|
|
|
if (irq_trigger(idx)) {
|
|
|
|
entry.trigger = 1;
|
|
|
|
entry.mask = 1;
|
|
|
|
entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
|
|
|
|
}
|
|
|
|
|
|
|
|
irq = pin_2_irq(idx, apic, pin);
|
|
|
|
add_pin_to_irq(irq, apic, pin);
|
|
|
|
|
|
|
|
if (!apic && !IO_APIC_IRQ(irq))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (IO_APIC_IRQ(irq)) {
|
2006-10-04 09:16:51 +00:00
|
|
|
cpumask_t mask;
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
|
2006-10-04 09:16:51 +00:00
|
|
|
if (vector < 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
|
2006-10-08 13:47:55 +00:00
|
|
|
entry.vector = vector;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
ioapic_register_intr(irq, vector, IOAPIC_AUTO);
|
|
|
|
if (!apic && (irq < 16))
|
|
|
|
disable_8259A_irq(irq);
|
|
|
|
}
|
2006-09-26 08:52:30 +00:00
|
|
|
ioapic_write_entry(apic, pin, entry);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
set_native_irq_info(irq, TARGET_CPUS);
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!first_notcon)
|
|
|
|
apic_printk(APIC_VERBOSE," not connected.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set up the 8259A-master output pin as broadcast to all
|
|
|
|
* CPUs.
|
|
|
|
*/
|
2006-01-11 21:46:06 +00:00
|
|
|
static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
struct IO_APIC_route_entry entry;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
memset(&entry,0,sizeof(entry));
|
|
|
|
|
|
|
|
disable_8259A_irq(0);
|
|
|
|
|
|
|
|
/* mask LVT0 */
|
2006-01-11 21:46:51 +00:00
|
|
|
apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We use logical delivery to get the timer IRQ
|
|
|
|
* to the first CPU.
|
|
|
|
*/
|
|
|
|
entry.dest_mode = INT_DEST_MODE;
|
|
|
|
entry.mask = 0; /* unmask IRQ now */
|
|
|
|
entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
|
|
|
|
entry.delivery_mode = INT_DELIVERY_MODE;
|
|
|
|
entry.polarity = 0;
|
|
|
|
entry.trigger = 0;
|
|
|
|
entry.vector = vector;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The timer IRQ doesn't have to know that behind the
|
|
|
|
* scene we have a 8259A-master in AEOI mode ...
|
|
|
|
*/
|
2006-10-17 07:10:03 +00:00
|
|
|
set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Add it to the IO-APIC irq-routing table:
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
2006-01-11 21:46:06 +00:00
|
|
|
io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
|
|
|
|
io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
|
|
|
|
enable_8259A_irq(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init UNEXPECTED_IO_APIC(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void __apicdebuginit print_IO_APIC(void)
|
|
|
|
{
|
|
|
|
int apic, i;
|
|
|
|
union IO_APIC_reg_00 reg_00;
|
|
|
|
union IO_APIC_reg_01 reg_01;
|
|
|
|
union IO_APIC_reg_02 reg_02;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (apic_verbosity == APIC_QUIET)
|
|
|
|
return;
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
|
|
|
|
for (i = 0; i < nr_ioapics; i++)
|
|
|
|
printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
|
|
|
|
mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We are a bit conservative about what we expect. We have to
|
|
|
|
* know about every hardware change ASAP.
|
|
|
|
*/
|
|
|
|
printk(KERN_INFO "testing the IO APIC.......................\n");
|
|
|
|
|
|
|
|
for (apic = 0; apic < nr_ioapics; apic++) {
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
|
reg_00.raw = io_apic_read(apic, 0);
|
|
|
|
reg_01.raw = io_apic_read(apic, 1);
|
|
|
|
if (reg_01.bits.version >= 0x10)
|
|
|
|
reg_02.raw = io_apic_read(apic, 2);
|
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
|
|
|
|
printk("\n");
|
|
|
|
printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
|
|
|
|
printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
|
|
|
|
printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
|
|
|
|
if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
|
|
|
|
UNEXPECTED_IO_APIC();
|
|
|
|
|
|
|
|
printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
|
|
|
|
printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
|
|
|
|
if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
|
|
|
|
(reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
|
|
|
|
(reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
|
|
|
|
(reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
|
|
|
|
(reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
|
|
|
|
(reg_01.bits.entries != 0x2E) &&
|
|
|
|
(reg_01.bits.entries != 0x3F) &&
|
|
|
|
(reg_01.bits.entries != 0x03)
|
|
|
|
)
|
|
|
|
UNEXPECTED_IO_APIC();
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
|
|
|
|
printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
|
|
|
|
if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
|
|
|
|
(reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
|
|
|
|
(reg_01.bits.version != 0x10) && /* oldest IO-APICs */
|
|
|
|
(reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
|
|
|
|
(reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
|
|
|
|
(reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
|
|
|
|
)
|
|
|
|
UNEXPECTED_IO_APIC();
|
|
|
|
if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
|
|
|
|
UNEXPECTED_IO_APIC();
|
|
|
|
|
|
|
|
if (reg_01.bits.version >= 0x10) {
|
|
|
|
printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
|
|
|
|
printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
|
|
|
|
if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
|
|
|
|
UNEXPECTED_IO_APIC();
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_DEBUG ".... IRQ redirection table:\n");
|
|
|
|
|
|
|
|
printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
|
|
|
|
" Stat Dest Deli Vect: \n");
|
|
|
|
|
|
|
|
for (i = 0; i <= reg_01.bits.entries; i++) {
|
|
|
|
struct IO_APIC_route_entry entry;
|
|
|
|
|
2006-09-26 08:52:30 +00:00
|
|
|
entry = ioapic_read_entry(apic, i);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
printk(KERN_DEBUG " %02x %03X %02X ",
|
|
|
|
i,
|
|
|
|
entry.dest.logical.logical_dest,
|
|
|
|
entry.dest.physical.physical_dest
|
|
|
|
);
|
|
|
|
|
|
|
|
printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
|
|
|
|
entry.mask,
|
|
|
|
entry.trigger,
|
|
|
|
entry.irr,
|
|
|
|
entry.polarity,
|
|
|
|
entry.delivery_status,
|
|
|
|
entry.dest_mode,
|
|
|
|
entry.delivery_mode,
|
|
|
|
entry.vector
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
printk(KERN_DEBUG "IRQ to pin mappings:\n");
|
|
|
|
for (i = 0; i < NR_IRQS; i++) {
|
|
|
|
struct irq_pin_list *entry = irq_2_pin + i;
|
|
|
|
if (entry->pin < 0)
|
|
|
|
continue;
|
2006-10-04 09:16:46 +00:00
|
|
|
printk(KERN_DEBUG "IRQ%d ", i);
|
2005-04-16 22:20:36 +00:00
|
|
|
for (;;) {
|
|
|
|
printk("-> %d:%d", entry->apic, entry->pin);
|
|
|
|
if (!entry->next)
|
|
|
|
break;
|
|
|
|
entry = irq_2_pin + entry->next;
|
|
|
|
}
|
|
|
|
printk("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_INFO ".................................... done.\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
|
|
|
static __apicdebuginit void print_APIC_bitfield (int base)
|
|
|
|
{
|
|
|
|
unsigned int v;
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
if (apic_verbosity == APIC_QUIET)
|
|
|
|
return;
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
v = apic_read(base + i*0x10);
|
|
|
|
for (j = 0; j < 32; j++) {
|
|
|
|
if (v & (1<<j))
|
|
|
|
printk("1");
|
|
|
|
else
|
|
|
|
printk("0");
|
|
|
|
}
|
|
|
|
printk("\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void __apicdebuginit print_local_APIC(void * dummy)
|
|
|
|
{
|
|
|
|
unsigned int v, ver, maxlvt;
|
|
|
|
|
|
|
|
if (apic_verbosity == APIC_QUIET)
|
|
|
|
return;
|
|
|
|
|
|
|
|
printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
|
|
|
|
smp_processor_id(), hard_smp_processor_id());
|
|
|
|
v = apic_read(APIC_ID);
|
|
|
|
printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
|
|
|
|
v = apic_read(APIC_LVR);
|
|
|
|
printk(KERN_INFO "... APIC VERSION: %08x\n", v);
|
|
|
|
ver = GET_APIC_VERSION(v);
|
|
|
|
maxlvt = get_maxlvt();
|
|
|
|
|
|
|
|
v = apic_read(APIC_TASKPRI);
|
|
|
|
printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
|
|
|
|
|
2005-09-12 16:49:24 +00:00
|
|
|
v = apic_read(APIC_ARBPRI);
|
|
|
|
printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
|
|
|
|
v & APIC_ARBPRI_MASK);
|
|
|
|
v = apic_read(APIC_PROCPRI);
|
|
|
|
printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
v = apic_read(APIC_EOI);
|
|
|
|
printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
|
|
|
|
v = apic_read(APIC_RRR);
|
|
|
|
printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
|
|
|
|
v = apic_read(APIC_LDR);
|
|
|
|
printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
|
|
|
|
v = apic_read(APIC_DFR);
|
|
|
|
printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
|
|
|
|
v = apic_read(APIC_SPIV);
|
|
|
|
printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "... APIC ISR field:\n");
|
|
|
|
print_APIC_bitfield(APIC_ISR);
|
|
|
|
printk(KERN_DEBUG "... APIC TMR field:\n");
|
|
|
|
print_APIC_bitfield(APIC_TMR);
|
|
|
|
printk(KERN_DEBUG "... APIC IRR field:\n");
|
|
|
|
print_APIC_bitfield(APIC_IRR);
|
|
|
|
|
2005-09-12 16:49:24 +00:00
|
|
|
v = apic_read(APIC_ESR);
|
|
|
|
printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
v = apic_read(APIC_ICR);
|
|
|
|
printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
|
|
|
|
v = apic_read(APIC_ICR2);
|
|
|
|
printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
|
|
|
|
|
|
|
|
v = apic_read(APIC_LVTT);
|
|
|
|
printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
|
|
|
|
|
|
|
|
if (maxlvt > 3) { /* PC is LVT#4. */
|
|
|
|
v = apic_read(APIC_LVTPC);
|
|
|
|
printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
|
|
|
|
}
|
|
|
|
v = apic_read(APIC_LVT0);
|
|
|
|
printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
|
|
|
|
v = apic_read(APIC_LVT1);
|
|
|
|
printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
|
|
|
|
|
|
|
|
if (maxlvt > 2) { /* ERR is LVT#3. */
|
|
|
|
v = apic_read(APIC_LVTERR);
|
|
|
|
printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
|
|
|
|
}
|
|
|
|
|
|
|
|
v = apic_read(APIC_TMICT);
|
|
|
|
printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
|
|
|
|
v = apic_read(APIC_TMCCT);
|
|
|
|
printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
|
|
|
|
v = apic_read(APIC_TDCR);
|
|
|
|
printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
|
|
|
|
printk("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
void print_all_local_APICs (void)
|
|
|
|
{
|
|
|
|
on_each_cpu(print_local_APIC, NULL, 1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void __apicdebuginit print_PIC(void)
|
|
|
|
{
|
|
|
|
unsigned int v;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (apic_verbosity == APIC_QUIET)
|
|
|
|
return;
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "\nprinting PIC contents\n");
|
|
|
|
|
|
|
|
spin_lock_irqsave(&i8259A_lock, flags);
|
|
|
|
|
|
|
|
v = inb(0xa1) << 8 | inb(0x21);
|
|
|
|
printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
|
|
|
|
|
|
|
|
v = inb(0xa0) << 8 | inb(0x20);
|
|
|
|
printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
|
|
|
|
|
|
|
|
outb(0x0b,0xa0);
|
|
|
|
outb(0x0b,0x20);
|
|
|
|
v = inb(0xa0) << 8 | inb(0x20);
|
|
|
|
outb(0x0a,0xa0);
|
|
|
|
outb(0x0a,0x20);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&i8259A_lock, flags);
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
|
|
|
|
|
|
|
|
v = inb(0x4d1) << 8 | inb(0x4d0);
|
|
|
|
printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* 0 */
|
|
|
|
|
|
|
|
static void __init enable_IO_APIC(void)
|
|
|
|
{
|
|
|
|
union IO_APIC_reg_01 reg_01;
|
2006-01-11 21:46:06 +00:00
|
|
|
int i8259_apic, i8259_pin;
|
|
|
|
int i, apic;
|
2005-04-16 22:20:36 +00:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
for (i = 0; i < PIN_MAP_SIZE; i++) {
|
|
|
|
irq_2_pin[i].pin = -1;
|
|
|
|
irq_2_pin[i].next = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The number of IO-APIC IRQ registers (== #pins):
|
|
|
|
*/
|
2006-01-11 21:46:06 +00:00
|
|
|
for (apic = 0; apic < nr_ioapics; apic++) {
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
2006-01-11 21:46:06 +00:00
|
|
|
reg_01.raw = io_apic_read(apic, 1);
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
2006-01-11 21:46:06 +00:00
|
|
|
nr_ioapic_registers[apic] = reg_01.bits.entries+1;
|
|
|
|
}
|
|
|
|
for(apic = 0; apic < nr_ioapics; apic++) {
|
|
|
|
int pin;
|
|
|
|
/* See if any of the pins is in ExtINT mode */
|
|
|
|
for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
|
|
|
|
struct IO_APIC_route_entry entry;
|
2006-09-26 08:52:30 +00:00
|
|
|
entry = ioapic_read_entry(apic, pin);
|
2006-01-11 21:46:06 +00:00
|
|
|
|
|
|
|
/* If the interrupt line is enabled and in ExtInt mode
|
|
|
|
* I have found the pin where the i8259 is connected.
|
|
|
|
*/
|
|
|
|
if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
|
|
|
|
ioapic_i8259.apic = apic;
|
|
|
|
ioapic_i8259.pin = pin;
|
|
|
|
goto found_i8259;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
found_i8259:
|
|
|
|
/* Look to see what if the MP table has reported the ExtINT */
|
|
|
|
i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
|
|
|
|
i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
|
|
|
|
/* Trust the MP table if nothing is setup in the hardware */
|
|
|
|
if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
|
|
|
|
printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
|
|
|
|
ioapic_i8259.pin = i8259_pin;
|
|
|
|
ioapic_i8259.apic = i8259_apic;
|
|
|
|
}
|
|
|
|
/* Complain if the MP table and the hardware disagree */
|
|
|
|
if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
|
|
|
|
(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
|
|
|
|
{
|
|
|
|
printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do not trust the IO-APIC being empty at bootup
|
|
|
|
*/
|
|
|
|
clear_IO_APIC();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Not an __init, needed by the reboot code
|
|
|
|
*/
|
|
|
|
void disable_IO_APIC(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Clear the IO-APIC before rebooting:
|
|
|
|
*/
|
|
|
|
clear_IO_APIC();
|
|
|
|
|
2005-06-25 21:57:45 +00:00
|
|
|
/*
|
2005-09-09 10:59:04 +00:00
|
|
|
* If the i8259 is routed through an IOAPIC
|
2005-06-25 21:57:45 +00:00
|
|
|
* Put that IOAPIC in virtual wire mode
|
2005-09-09 10:59:04 +00:00
|
|
|
* so legacy interrupts can be delivered.
|
2005-06-25 21:57:45 +00:00
|
|
|
*/
|
2006-01-11 21:46:06 +00:00
|
|
|
if (ioapic_i8259.pin != -1) {
|
2005-06-25 21:57:45 +00:00
|
|
|
struct IO_APIC_route_entry entry;
|
|
|
|
|
|
|
|
memset(&entry, 0, sizeof(entry));
|
|
|
|
entry.mask = 0; /* Enabled */
|
|
|
|
entry.trigger = 0; /* Edge */
|
|
|
|
entry.irr = 0;
|
|
|
|
entry.polarity = 0; /* High */
|
|
|
|
entry.delivery_status = 0;
|
|
|
|
entry.dest_mode = 0; /* Physical */
|
2006-01-11 21:46:06 +00:00
|
|
|
entry.delivery_mode = dest_ExtINT; /* ExtInt */
|
2005-06-25 21:57:45 +00:00
|
|
|
entry.vector = 0;
|
2006-01-11 21:46:21 +00:00
|
|
|
entry.dest.physical.physical_dest =
|
|
|
|
GET_APIC_ID(apic_read(APIC_ID));
|
2005-06-25 21:57:45 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Add it to the IO-APIC irq-routing table:
|
|
|
|
*/
|
2006-09-26 08:52:30 +00:00
|
|
|
ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
|
2005-06-25 21:57:45 +00:00
|
|
|
}
|
|
|
|
|
2006-01-11 21:46:06 +00:00
|
|
|
disconnect_bsp_APIC(ioapic_i8259.pin != -1);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There is a nasty bug in some older SMP boards, their mptable lies
|
|
|
|
* about the timer IRQ. We do the following to work around the situation:
|
|
|
|
*
|
|
|
|
* - timer IRQ defaults to IO-APIC IRQ
|
|
|
|
* - if this function detects that timer IRQs are defunct, then we fall
|
|
|
|
* back to ISA timer IRQs
|
|
|
|
*/
|
|
|
|
static int __init timer_irq_works(void)
|
|
|
|
{
|
|
|
|
unsigned long t1 = jiffies;
|
|
|
|
|
|
|
|
local_irq_enable();
|
|
|
|
/* Let ten ticks pass... */
|
|
|
|
mdelay((10 * 1000) / HZ);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Expect a few ticks at least, to be sure some possible
|
|
|
|
* glue logic does not lock up after one or two first
|
|
|
|
* ticks in a non-ExtINT mode. Also the local APIC
|
|
|
|
* might have cached one ExtINT interrupt. Finally, at
|
|
|
|
* least one tick may be lost due to delays.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* jiffies wrap? */
|
|
|
|
if (jiffies - t1 > 4)
|
|
|
|
return 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In the SMP+IOAPIC case it might happen that there are an unspecified
|
|
|
|
* number of pending IRQ events unhandled. These cases are very rare,
|
|
|
|
* so we 'resend' these IRQs via IPIs, to the same CPU. It's much
|
|
|
|
* better to do it this way as thus we do not have to be aware of
|
|
|
|
* 'pending' interrupts in the IRQ path, except at this point.
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* Edge triggered needs to resend any interrupt
|
|
|
|
* that was delayed but this is now handled in the device
|
|
|
|
* independent code.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Starting up a edge-triggered IO-APIC interrupt is
|
|
|
|
* nasty - we need to make sure that we get the edge.
|
|
|
|
* If it is already asserted for some reason, we need
|
|
|
|
* return 1 to indicate that is was pending.
|
|
|
|
*
|
|
|
|
* This is not complete - we should be able to fake
|
|
|
|
* an edge even if it isn't on the 8259A...
|
|
|
|
*/
|
|
|
|
|
2006-10-04 09:16:25 +00:00
|
|
|
static unsigned int startup_ioapic_irq(unsigned int irq)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
int was_pending = 0;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
|
if (irq < 16) {
|
|
|
|
disable_8259A_irq(irq);
|
|
|
|
if (i8259A_irq_pending(irq))
|
|
|
|
was_pending = 1;
|
|
|
|
}
|
|
|
|
__unmask_IO_APIC_irq(irq);
|
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
|
|
|
|
return was_pending;
|
|
|
|
}
|
|
|
|
|
2006-10-04 09:16:46 +00:00
|
|
|
static int ioapic_retrigger_irq(unsigned int irq)
|
2006-06-29 09:24:44 +00:00
|
|
|
{
|
2006-10-04 09:16:51 +00:00
|
|
|
cpumask_t mask;
|
|
|
|
unsigned vector;
|
2006-10-21 16:37:02 +00:00
|
|
|
unsigned long flags;
|
2006-10-04 09:16:51 +00:00
|
|
|
|
2006-10-21 16:37:02 +00:00
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
2006-10-04 09:16:51 +00:00
|
|
|
vector = irq_vector[irq];
|
|
|
|
cpus_clear(mask);
|
2006-10-21 16:37:02 +00:00
|
|
|
cpu_set(first_cpu(irq_domain[irq]), mask);
|
2006-10-04 09:16:51 +00:00
|
|
|
|
2006-10-21 16:37:02 +00:00
|
|
|
send_IPI_mask(mask, vector);
|
|
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
2006-06-29 09:24:44 +00:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Level and edge triggered IO-APIC interrupts need different handling,
|
|
|
|
* so we use two separate IRQ descriptors. Edge triggered IRQs can be
|
|
|
|
* handled with the level-triggered descriptor, but that one has slightly
|
|
|
|
* more overhead. Level-triggered interrupts cannot be handled with the
|
|
|
|
* edge-triggered handler, without risking IRQ storms and other ugly
|
|
|
|
* races.
|
|
|
|
*/
|
|
|
|
|
2006-10-04 09:16:30 +00:00
|
|
|
static void ack_apic_edge(unsigned int irq)
|
|
|
|
{
|
|
|
|
move_native_irq(irq);
|
|
|
|
ack_APIC_irq();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ack_apic_level(unsigned int irq)
|
|
|
|
{
|
|
|
|
int do_unmask_irq = 0;
|
|
|
|
|
|
|
|
#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
|
|
|
|
/* If we are moving the irq we need to mask it */
|
|
|
|
if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
|
|
|
|
do_unmask_irq = 1;
|
|
|
|
mask_IO_APIC_irq(irq);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We must acknowledge the irq before we move it or the acknowledge will
|
|
|
|
* not propogate properly.
|
|
|
|
*/
|
|
|
|
ack_APIC_irq();
|
|
|
|
|
|
|
|
/* Now we can move and renable the irq */
|
|
|
|
move_masked_irq(irq);
|
|
|
|
if (unlikely(do_unmask_irq))
|
|
|
|
unmask_IO_APIC_irq(irq);
|
|
|
|
}
|
|
|
|
|
2006-10-04 09:16:25 +00:00
|
|
|
static struct irq_chip ioapic_chip __read_mostly = {
|
|
|
|
.name = "IO-APIC",
|
2006-10-04 09:16:46 +00:00
|
|
|
.startup = startup_ioapic_irq,
|
|
|
|
.mask = mask_IO_APIC_irq,
|
|
|
|
.unmask = unmask_IO_APIC_irq,
|
2006-10-04 09:16:30 +00:00
|
|
|
.ack = ack_apic_edge,
|
|
|
|
.eoi = ack_apic_level,
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2006-10-04 09:16:46 +00:00
|
|
|
.set_affinity = set_ioapic_affinity_irq,
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
#endif
|
2006-10-04 09:16:46 +00:00
|
|
|
.retrigger = ioapic_retrigger_irq,
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static inline void init_IO_APIC_traps(void)
|
|
|
|
{
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* NOTE! The local APIC isn't very good at handling
|
|
|
|
* multiple interrupts at the same interrupt level.
|
|
|
|
* As the interrupt level is determined by taking the
|
|
|
|
* vector number and shifting that right by 4, we
|
|
|
|
* want to spread these out a bit so that they don't
|
|
|
|
* all fall in the same interrupt level.
|
|
|
|
*
|
|
|
|
* Also, we've got to be careful not to trash gate
|
|
|
|
* 0x80, because int 0x80 is hm, kind of importantish. ;)
|
|
|
|
*/
|
|
|
|
for (irq = 0; irq < NR_IRQS ; irq++) {
|
|
|
|
int tmp = irq;
|
2006-10-08 13:43:46 +00:00
|
|
|
if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Hmm.. We don't have an entry for this,
|
|
|
|
* so default to an old-fashioned 8259
|
|
|
|
* interrupt if we can..
|
|
|
|
*/
|
|
|
|
if (irq < 16)
|
|
|
|
make_8259A_irq(irq);
|
|
|
|
else
|
|
|
|
/* Strange. Oh, well.. */
|
2006-10-04 09:16:25 +00:00
|
|
|
irq_desc[irq].chip = &no_irq_chip;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enable_lapic_irq (unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned long v;
|
|
|
|
|
|
|
|
v = apic_read(APIC_LVT0);
|
2006-01-11 21:46:51 +00:00
|
|
|
apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void disable_lapic_irq (unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned long v;
|
|
|
|
|
|
|
|
v = apic_read(APIC_LVT0);
|
2006-01-11 21:46:51 +00:00
|
|
|
apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ack_lapic_irq (unsigned int irq)
|
|
|
|
{
|
|
|
|
ack_APIC_irq();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void end_lapic_irq (unsigned int i) { /* nothing */ }
|
|
|
|
|
2005-09-06 22:17:45 +00:00
|
|
|
static struct hw_interrupt_type lapic_irq_type __read_mostly = {
|
2005-04-16 22:20:36 +00:00
|
|
|
.typename = "local-APIC-edge",
|
|
|
|
.startup = NULL, /* startup_irq() not used for IRQ0 */
|
|
|
|
.shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
|
|
|
|
.enable = enable_lapic_irq,
|
|
|
|
.disable = disable_lapic_irq,
|
|
|
|
.ack = ack_lapic_irq,
|
|
|
|
.end = end_lapic_irq,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void setup_nmi (void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Dirty trick to enable the NMI watchdog ...
|
|
|
|
* We put the 8259A master into AEOI mode and
|
|
|
|
* unmask on all local APICs LVT0 as NMI.
|
|
|
|
*
|
|
|
|
* The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
|
|
|
|
* is from Maciej W. Rozycki - so we do not have to EOI from
|
|
|
|
* the NMI handler or the timer interrupt.
|
|
|
|
*/
|
|
|
|
printk(KERN_INFO "activating NMI Watchdog ...");
|
|
|
|
|
|
|
|
enable_NMI_through_LVT0(NULL);
|
|
|
|
|
|
|
|
printk(" done.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This looks a bit hackish but it's about the only one way of sending
|
|
|
|
* a few INTA cycles to 8259As and any associated glue logic. ICR does
|
|
|
|
* not support the ExtINT mode, unfortunately. We need to send these
|
|
|
|
* cycles as some i82489DX-based boards have glue logic that keeps the
|
|
|
|
* 8259A interrupt line asserted until INTA. --macro
|
|
|
|
*/
|
|
|
|
static inline void unlock_ExtINT_logic(void)
|
|
|
|
{
|
2006-01-11 21:46:06 +00:00
|
|
|
int apic, pin, i;
|
2005-04-16 22:20:36 +00:00
|
|
|
struct IO_APIC_route_entry entry0, entry1;
|
|
|
|
unsigned char save_control, save_freq_select;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2006-01-11 21:46:06 +00:00
|
|
|
pin = find_isa_irq_pin(8, mp_INT);
|
|
|
|
apic = find_isa_irq_apic(8, mp_INT);
|
2005-04-16 22:20:36 +00:00
|
|
|
if (pin == -1)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
2006-01-11 21:46:06 +00:00
|
|
|
*(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
|
|
|
|
*(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
2006-01-11 21:46:06 +00:00
|
|
|
clear_IO_APIC_pin(apic, pin);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
memset(&entry1, 0, sizeof(entry1));
|
|
|
|
|
|
|
|
entry1.dest_mode = 0; /* physical delivery */
|
|
|
|
entry1.mask = 0; /* unmask IRQ now */
|
|
|
|
entry1.dest.physical.physical_dest = hard_smp_processor_id();
|
|
|
|
entry1.delivery_mode = dest_ExtINT;
|
|
|
|
entry1.polarity = entry0.polarity;
|
|
|
|
entry1.trigger = 0;
|
|
|
|
entry1.vector = 0;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
2006-01-11 21:46:06 +00:00
|
|
|
io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
|
|
|
|
io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
|
|
|
|
save_control = CMOS_READ(RTC_CONTROL);
|
|
|
|
save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
|
|
|
|
CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
|
|
|
|
RTC_FREQ_SELECT);
|
|
|
|
CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
|
|
|
|
|
|
|
|
i = 100;
|
|
|
|
while (i-- > 0) {
|
|
|
|
mdelay(10);
|
|
|
|
if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
|
|
|
|
i -= 10;
|
|
|
|
}
|
|
|
|
|
|
|
|
CMOS_WRITE(save_control, RTC_CONTROL);
|
|
|
|
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
|
2006-01-11 21:46:06 +00:00
|
|
|
clear_IO_APIC_pin(apic, pin);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
2006-01-11 21:46:06 +00:00
|
|
|
io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
|
|
|
|
io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This code may look a bit paranoid, but it's supposed to cooperate with
|
|
|
|
* a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
|
|
|
|
* is so screwy. Thanks to Brian Perkins for testing/hacking this beast
|
|
|
|
* fanatically on his truly buggy board.
|
2006-02-26 03:18:52 +00:00
|
|
|
*
|
|
|
|
* FIXME: really need to revamp this for modern platforms only.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
static inline void check_timer(void)
|
|
|
|
{
|
2006-01-11 21:46:06 +00:00
|
|
|
int apic1, pin1, apic2, pin2;
|
2005-04-16 22:20:36 +00:00
|
|
|
int vector;
|
2006-10-08 13:47:55 +00:00
|
|
|
cpumask_t mask;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* get/set the timer IRQ vector:
|
|
|
|
*/
|
|
|
|
disable_8259A_irq(0);
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(0, TARGET_CPUS, &mask);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Subtle, code in do_timer_interrupt() expects an AEOI
|
|
|
|
* mode for the 8259A whenever interrupts are routed
|
|
|
|
* through I/O APICs. Also IRQ0 has to be enabled in
|
|
|
|
* the 8259A which implies the virtual wire has to be
|
|
|
|
* disabled in the local APIC.
|
|
|
|
*/
|
2006-01-11 21:46:51 +00:00
|
|
|
apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
|
2005-04-16 22:20:36 +00:00
|
|
|
init_8259A(1);
|
2006-02-26 03:18:52 +00:00
|
|
|
if (timer_over_8254 > 0)
|
|
|
|
enable_8259A_irq(0);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-01-11 21:46:06 +00:00
|
|
|
pin1 = find_isa_irq_pin(0, mp_INT);
|
|
|
|
apic1 = find_isa_irq_apic(0, mp_INT);
|
|
|
|
pin2 = ioapic_i8259.pin;
|
|
|
|
apic2 = ioapic_i8259.apic;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-01-11 21:46:06 +00:00
|
|
|
apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
|
|
|
|
vector, apic1, pin1, apic2, pin2);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
if (pin1 != -1) {
|
|
|
|
/*
|
|
|
|
* Ok, does IRQ0 through the IOAPIC work?
|
|
|
|
*/
|
|
|
|
unmask_IO_APIC_irq(0);
|
2005-05-20 21:27:59 +00:00
|
|
|
if (!no_timer_check && timer_irq_works()) {
|
2005-04-16 22:20:36 +00:00
|
|
|
nmi_watchdog_default();
|
|
|
|
if (nmi_watchdog == NMI_IO_APIC) {
|
|
|
|
disable_8259A_irq(0);
|
|
|
|
setup_nmi();
|
|
|
|
enable_8259A_irq(0);
|
|
|
|
}
|
2005-09-12 16:49:25 +00:00
|
|
|
if (disable_timer_pin_1 > 0)
|
|
|
|
clear_IO_APIC_pin(0, pin1);
|
2005-04-16 22:20:36 +00:00
|
|
|
return;
|
|
|
|
}
|
2006-01-11 21:46:06 +00:00
|
|
|
clear_IO_APIC_pin(apic1, pin1);
|
|
|
|
apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
|
|
|
|
"connected to IO-APIC\n");
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2006-01-11 21:46:06 +00:00
|
|
|
apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
|
|
|
|
"through the 8259A ... ");
|
2005-04-16 22:20:36 +00:00
|
|
|
if (pin2 != -1) {
|
2006-01-11 21:46:06 +00:00
|
|
|
apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
|
|
|
|
apic2, pin2);
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* legacy devices should be connected to IO APIC #0
|
|
|
|
*/
|
2006-01-11 21:46:06 +00:00
|
|
|
setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
|
2005-04-16 22:20:36 +00:00
|
|
|
if (timer_irq_works()) {
|
2006-03-25 15:30:55 +00:00
|
|
|
apic_printk(APIC_VERBOSE," works.\n");
|
2005-04-16 22:20:36 +00:00
|
|
|
nmi_watchdog_default();
|
|
|
|
if (nmi_watchdog == NMI_IO_APIC) {
|
|
|
|
setup_nmi();
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Cleanup, just in case ...
|
|
|
|
*/
|
2006-01-11 21:46:06 +00:00
|
|
|
clear_IO_APIC_pin(apic2, pin2);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2006-03-25 15:30:55 +00:00
|
|
|
apic_printk(APIC_VERBOSE," failed.\n");
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-02-26 03:18:40 +00:00
|
|
|
if (nmi_watchdog == NMI_IO_APIC) {
|
2005-04-16 22:20:36 +00:00
|
|
|
printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
|
|
|
|
nmi_watchdog = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
|
|
|
|
|
|
|
|
disable_8259A_irq(0);
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 09:24:36 +00:00
|
|
|
irq_desc[0].chip = &lapic_irq_type;
|
2006-01-11 21:46:51 +00:00
|
|
|
apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
|
2005-04-16 22:20:36 +00:00
|
|
|
enable_8259A_irq(0);
|
|
|
|
|
|
|
|
if (timer_irq_works()) {
|
2006-03-25 15:30:55 +00:00
|
|
|
apic_printk(APIC_VERBOSE," works.\n");
|
2005-04-16 22:20:36 +00:00
|
|
|
return;
|
|
|
|
}
|
2006-01-11 21:46:51 +00:00
|
|
|
apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
|
2005-04-16 22:20:36 +00:00
|
|
|
apic_printk(APIC_VERBOSE," failed.\n");
|
|
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
|
|
|
|
|
|
|
|
init_8259A(0);
|
|
|
|
make_8259A_irq(0);
|
2006-01-11 21:46:51 +00:00
|
|
|
apic_write(APIC_LVT0, APIC_DM_EXTINT);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
unlock_ExtINT_logic();
|
|
|
|
|
|
|
|
if (timer_irq_works()) {
|
|
|
|
apic_printk(APIC_VERBOSE," works.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
apic_printk(APIC_VERBOSE," failed :(.\n");
|
|
|
|
panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
|
|
|
|
}
|
|
|
|
|
2005-05-20 21:27:59 +00:00
|
|
|
static int __init notimercheck(char *s)
|
|
|
|
{
|
|
|
|
no_timer_check = 1;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
__setup("no_timer_check", notimercheck);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
*
|
|
|
|
* IRQ's that are handled by the PIC in the MPS IOAPIC case.
|
|
|
|
* - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
|
|
|
|
* Linux doesn't really care, as it's not actually used
|
|
|
|
* for any interrupt handling anyway.
|
|
|
|
*/
|
|
|
|
#define PIC_IRQS (1<<2)
|
|
|
|
|
|
|
|
void __init setup_IO_APIC(void)
|
|
|
|
{
|
|
|
|
enable_IO_APIC();
|
|
|
|
|
|
|
|
if (acpi_ioapic)
|
|
|
|
io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
|
|
|
|
else
|
|
|
|
io_apic_irqs = ~PIC_IRQS;
|
|
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
|
|
|
|
|
|
|
|
sync_Arb_IDs();
|
|
|
|
setup_IO_APIC_irqs();
|
|
|
|
init_IO_APIC_traps();
|
|
|
|
check_timer();
|
|
|
|
if (!acpi_ioapic)
|
|
|
|
print_IO_APIC();
|
|
|
|
}
|
|
|
|
|
|
|
|
struct sysfs_ioapic_data {
|
|
|
|
struct sys_device dev;
|
|
|
|
struct IO_APIC_route_entry entry[0];
|
|
|
|
};
|
|
|
|
static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
|
|
|
|
|
2005-04-16 22:25:31 +00:00
|
|
|
static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
struct IO_APIC_route_entry *entry;
|
|
|
|
struct sysfs_ioapic_data *data;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
data = container_of(dev, struct sysfs_ioapic_data, dev);
|
|
|
|
entry = data->entry;
|
2006-09-26 08:52:30 +00:00
|
|
|
for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
|
|
|
|
*entry = ioapic_read_entry(dev->id, i);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ioapic_resume(struct sys_device *dev)
|
|
|
|
{
|
|
|
|
struct IO_APIC_route_entry *entry;
|
|
|
|
struct sysfs_ioapic_data *data;
|
|
|
|
unsigned long flags;
|
|
|
|
union IO_APIC_reg_00 reg_00;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
data = container_of(dev, struct sysfs_ioapic_data, dev);
|
|
|
|
entry = data->entry;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
|
reg_00.raw = io_apic_read(dev->id, 0);
|
|
|
|
if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
|
|
|
|
reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
|
|
|
|
io_apic_write(dev->id, 0, reg_00.raw);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
2006-09-26 08:52:30 +00:00
|
|
|
for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
|
|
|
|
ioapic_write_entry(dev->id, i, entry[i]);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct sysdev_class ioapic_sysdev_class = {
|
|
|
|
set_kset_name("ioapic"),
|
|
|
|
.suspend = ioapic_suspend,
|
|
|
|
.resume = ioapic_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init ioapic_init_sysfs(void)
|
|
|
|
{
|
|
|
|
struct sys_device * dev;
|
|
|
|
int i, size, error = 0;
|
|
|
|
|
|
|
|
error = sysdev_class_register(&ioapic_sysdev_class);
|
|
|
|
if (error)
|
|
|
|
return error;
|
|
|
|
|
|
|
|
for (i = 0; i < nr_ioapics; i++ ) {
|
|
|
|
size = sizeof(struct sys_device) + nr_ioapic_registers[i]
|
|
|
|
* sizeof(struct IO_APIC_route_entry);
|
|
|
|
mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
|
|
|
|
if (!mp_ioapic_data[i]) {
|
|
|
|
printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
memset(mp_ioapic_data[i], 0, size);
|
|
|
|
dev = &mp_ioapic_data[i]->dev;
|
|
|
|
dev->id = i;
|
|
|
|
dev->cls = &ioapic_sysdev_class;
|
|
|
|
error = sysdev_register(dev);
|
|
|
|
if (error) {
|
|
|
|
kfree(mp_ioapic_data[i]);
|
|
|
|
mp_ioapic_data[i] = NULL;
|
|
|
|
printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
device_initcall(ioapic_init_sysfs);
|
|
|
|
|
2006-10-04 09:16:40 +00:00
|
|
|
/*
|
2006-10-04 09:16:46 +00:00
|
|
|
* Dynamic irq allocate and deallocation
|
2006-10-04 09:16:40 +00:00
|
|
|
*/
|
|
|
|
int create_irq(void)
|
|
|
|
{
|
2006-10-04 09:16:46 +00:00
|
|
|
/* Allocate an unused irq */
|
|
|
|
int irq;
|
|
|
|
int new;
|
|
|
|
int vector = 0;
|
2006-10-04 09:16:40 +00:00
|
|
|
unsigned long flags;
|
2006-10-08 13:47:55 +00:00
|
|
|
cpumask_t mask;
|
2006-10-04 09:16:40 +00:00
|
|
|
|
2006-10-04 09:16:46 +00:00
|
|
|
irq = -ENOSPC;
|
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
|
|
|
for (new = (NR_IRQS - 1); new >= 0; new--) {
|
|
|
|
if (platform_legacy_irq(new))
|
|
|
|
continue;
|
|
|
|
if (irq_vector[new] != 0)
|
|
|
|
continue;
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
|
2006-10-04 09:16:46 +00:00
|
|
|
if (likely(vector > 0))
|
|
|
|
irq = new;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
2006-10-04 09:16:40 +00:00
|
|
|
|
2006-10-04 09:16:46 +00:00
|
|
|
if (irq >= 0) {
|
2006-10-04 09:16:40 +00:00
|
|
|
dynamic_irq_init(irq);
|
|
|
|
}
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
void destroy_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
dynamic_irq_cleanup(irq);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vector_lock, flags);
|
|
|
|
irq_vector[irq] = 0;
|
|
|
|
spin_unlock_irqrestore(&vector_lock, flags);
|
|
|
|
}
|
|
|
|
|
2006-10-04 09:16:42 +00:00
|
|
|
/*
|
|
|
|
* MSI mesage composition
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
2006-10-04 09:16:59 +00:00
|
|
|
static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
|
2006-10-04 09:16:42 +00:00
|
|
|
{
|
|
|
|
int vector;
|
|
|
|
unsigned dest;
|
2006-10-08 13:47:55 +00:00
|
|
|
cpumask_t tmp;
|
2006-10-04 09:16:42 +00:00
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
|
2006-10-04 09:16:42 +00:00
|
|
|
if (vector >= 0) {
|
|
|
|
dest = cpu_mask_to_apicid(tmp);
|
|
|
|
|
|
|
|
msg->address_hi = MSI_ADDR_BASE_HI;
|
|
|
|
msg->address_lo =
|
|
|
|
MSI_ADDR_BASE_LO |
|
|
|
|
((INT_DEST_MODE == 0) ?
|
|
|
|
MSI_ADDR_DEST_MODE_PHYSICAL:
|
|
|
|
MSI_ADDR_DEST_MODE_LOGICAL) |
|
|
|
|
((INT_DELIVERY_MODE != dest_LowestPrio) ?
|
|
|
|
MSI_ADDR_REDIRECTION_CPU:
|
|
|
|
MSI_ADDR_REDIRECTION_LOWPRI) |
|
|
|
|
MSI_ADDR_DEST_ID(dest);
|
|
|
|
|
|
|
|
msg->data =
|
|
|
|
MSI_DATA_TRIGGER_EDGE |
|
|
|
|
MSI_DATA_LEVEL_ASSERT |
|
|
|
|
((INT_DELIVERY_MODE != dest_LowestPrio) ?
|
|
|
|
MSI_DATA_DELIVERY_FIXED:
|
|
|
|
MSI_DATA_DELIVERY_LOWPRI) |
|
|
|
|
MSI_DATA_VECTOR(vector);
|
|
|
|
}
|
|
|
|
return vector;
|
|
|
|
}
|
|
|
|
|
2006-10-04 09:16:59 +00:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
|
2006-10-04 09:16:42 +00:00
|
|
|
{
|
2006-10-04 09:16:59 +00:00
|
|
|
struct msi_msg msg;
|
|
|
|
unsigned int dest;
|
|
|
|
cpumask_t tmp;
|
2006-10-04 09:16:42 +00:00
|
|
|
int vector;
|
2006-10-04 09:16:59 +00:00
|
|
|
|
|
|
|
cpus_and(tmp, mask, cpu_online_map);
|
|
|
|
if (cpus_empty(tmp))
|
|
|
|
tmp = TARGET_CPUS;
|
|
|
|
|
|
|
|
cpus_and(mask, tmp, CPU_MASK_ALL);
|
2006-10-04 09:16:42 +00:00
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(irq, mask, &tmp);
|
2006-10-04 09:16:59 +00:00
|
|
|
if (vector < 0)
|
|
|
|
return;
|
2006-10-04 09:16:51 +00:00
|
|
|
|
2006-10-04 09:16:59 +00:00
|
|
|
dest = cpu_mask_to_apicid(tmp);
|
2006-10-04 09:16:42 +00:00
|
|
|
|
2006-10-04 09:16:59 +00:00
|
|
|
read_msi_msg(irq, &msg);
|
|
|
|
|
|
|
|
msg.data &= ~MSI_DATA_VECTOR_MASK;
|
|
|
|
msg.data |= MSI_DATA_VECTOR(vector);
|
|
|
|
msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
|
|
|
|
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
|
|
|
|
|
|
|
|
write_msi_msg(irq, &msg);
|
|
|
|
set_native_irq_info(irq, mask);
|
2006-10-04 09:16:42 +00:00
|
|
|
}
|
2006-10-04 09:16:59 +00:00
|
|
|
#endif /* CONFIG_SMP */
|
2006-10-04 09:16:42 +00:00
|
|
|
|
2006-10-04 09:16:59 +00:00
|
|
|
/*
|
|
|
|
* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
|
|
|
|
* which implement the MSI or MSI-X Capability Structure.
|
|
|
|
*/
|
|
|
|
static struct irq_chip msi_chip = {
|
|
|
|
.name = "PCI-MSI",
|
|
|
|
.unmask = unmask_msi_irq,
|
|
|
|
.mask = mask_msi_irq,
|
|
|
|
.ack = ack_apic_edge,
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
.set_affinity = set_msi_irq_affinity,
|
|
|
|
#endif
|
|
|
|
.retrigger = ioapic_retrigger_irq,
|
2006-10-04 09:16:42 +00:00
|
|
|
};
|
|
|
|
|
2006-10-04 09:16:59 +00:00
|
|
|
int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct msi_msg msg;
|
|
|
|
int ret;
|
|
|
|
ret = msi_compose_msg(dev, irq, &msg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
write_msi_msg(irq, &msg);
|
|
|
|
|
2006-10-17 07:10:03 +00:00
|
|
|
set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
|
2006-10-04 09:16:59 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void arch_teardown_msi_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_PCI_MSI */
|
2006-10-04 09:16:42 +00:00
|
|
|
|
2006-10-04 09:16:55 +00:00
|
|
|
/*
|
|
|
|
* Hypertransport interrupt support
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_HT_IRQ
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
|
|
|
static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
|
|
|
|
{
|
|
|
|
u32 low, high;
|
|
|
|
low = read_ht_irq_low(irq);
|
|
|
|
high = read_ht_irq_high(irq);
|
|
|
|
|
|
|
|
low &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
|
|
|
|
high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
|
|
|
|
|
|
|
|
low |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
|
|
|
|
high |= HT_IRQ_HIGH_DEST_ID(dest);
|
|
|
|
|
|
|
|
write_ht_irq_low(irq, low);
|
|
|
|
write_ht_irq_high(irq, high);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
|
|
|
|
{
|
|
|
|
unsigned int dest;
|
|
|
|
cpumask_t tmp;
|
|
|
|
int vector;
|
|
|
|
|
|
|
|
cpus_and(tmp, mask, cpu_online_map);
|
|
|
|
if (cpus_empty(tmp))
|
|
|
|
tmp = TARGET_CPUS;
|
|
|
|
|
|
|
|
cpus_and(mask, tmp, CPU_MASK_ALL);
|
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(irq, mask, &tmp);
|
2006-10-04 09:16:55 +00:00
|
|
|
if (vector < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dest = cpu_mask_to_apicid(tmp);
|
|
|
|
|
|
|
|
target_ht_irq(irq, dest, vector & 0xff);
|
|
|
|
set_native_irq_info(irq, mask);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2006-10-11 08:20:43 +00:00
|
|
|
static struct irq_chip ht_irq_chip = {
|
2006-10-04 09:16:55 +00:00
|
|
|
.name = "PCI-HT",
|
|
|
|
.mask = mask_ht_irq,
|
|
|
|
.unmask = unmask_ht_irq,
|
|
|
|
.ack = ack_apic_edge,
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
.set_affinity = set_ht_irq_affinity,
|
|
|
|
#endif
|
|
|
|
.retrigger = ioapic_retrigger_irq,
|
|
|
|
};
|
|
|
|
|
|
|
|
int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int vector;
|
2006-10-08 13:47:55 +00:00
|
|
|
cpumask_t tmp;
|
2006-10-04 09:16:55 +00:00
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
|
2006-10-04 09:16:55 +00:00
|
|
|
if (vector >= 0) {
|
|
|
|
u32 low, high;
|
|
|
|
unsigned dest;
|
|
|
|
|
|
|
|
dest = cpu_mask_to_apicid(tmp);
|
|
|
|
|
|
|
|
high = HT_IRQ_HIGH_DEST_ID(dest);
|
|
|
|
|
|
|
|
low = HT_IRQ_LOW_BASE |
|
|
|
|
HT_IRQ_LOW_DEST_ID(dest) |
|
|
|
|
HT_IRQ_LOW_VECTOR(vector) |
|
|
|
|
((INT_DEST_MODE == 0) ?
|
|
|
|
HT_IRQ_LOW_DM_PHYSICAL :
|
|
|
|
HT_IRQ_LOW_DM_LOGICAL) |
|
|
|
|
HT_IRQ_LOW_RQEOI_EDGE |
|
|
|
|
((INT_DELIVERY_MODE != dest_LowestPrio) ?
|
|
|
|
HT_IRQ_LOW_MT_FIXED :
|
|
|
|
HT_IRQ_LOW_MT_ARBITRATED);
|
|
|
|
|
|
|
|
write_ht_irq_low(irq, low);
|
|
|
|
write_ht_irq_high(irq, high);
|
|
|
|
|
2006-10-17 07:10:03 +00:00
|
|
|
set_irq_chip_and_handler_name(irq, &ht_irq_chip,
|
|
|
|
handle_edge_irq, "edge");
|
2006-10-04 09:16:55 +00:00
|
|
|
}
|
|
|
|
return vector;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_HT_IRQ */
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* --------------------------------------------------------------------------
|
|
|
|
ACPI-based IOAPIC Configuration
|
|
|
|
-------------------------------------------------------------------------- */
|
|
|
|
|
2005-08-24 16:07:20 +00:00
|
|
|
#ifdef CONFIG_ACPI
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
#define IO_APIC_MAX_ID 0xFE
|
|
|
|
|
|
|
|
int __init io_apic_get_redir_entries (int ioapic)
|
|
|
|
{
|
|
|
|
union IO_APIC_reg_01 reg_01;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
|
reg_01.raw = io_apic_read(ioapic, 1);
|
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
|
|
|
|
return reg_01.bits.entries;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
[ACPI] ACPICA 20050930
Completed a major overhaul of the Resource Manager code -
specifically, optimizations in the area of the AML/internal
resource conversion code. The code has been optimized to
simplify and eliminate duplicated code, CPU stack use has
been decreased by optimizing function parameters and local
variables, and naming conventions across the manager have
been standardized for clarity and ease of maintenance (this
includes function, parameter, variable, and struct/typedef
names.)
All Resource Manager dispatch and information tables have
been moved to a single location for clarity and ease of
maintenance. One new file was created, named "rsinfo.c".
The ACPI return macros (return_ACPI_STATUS, etc.) have
been modified to guarantee that the argument is
not evaluated twice, making them less prone to macro
side-effects. However, since there exists the possibility
of additional stack use if a particular compiler cannot
optimize them (such as in the debug generation case),
the original macros are optionally available. Note that
some invocations of the return_VALUE macro may now cause
size mismatch warnings; the return_UINT8 and return_UINT32
macros are provided to eliminate these. (From Randy Dunlap)
Implemented a new mechanism to enable debug tracing for
individual control methods. A new external interface,
acpi_debug_trace(), is provided to enable this mechanism. The
intent is to allow the host OS to easily enable and disable
tracing for problematic control methods. This interface
can be easily exposed to a user or debugger interface if
desired. See the file psxface.c for details.
acpi_ut_callocate() will now return a valid pointer if a
length of zero is specified - a length of one is used
and a warning is issued. This matches the behavior of
acpi_ut_allocate().
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2005-09-30 23:03:00 +00:00
|
|
|
int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
struct IO_APIC_route_entry entry;
|
|
|
|
unsigned long flags;
|
2006-10-04 09:16:51 +00:00
|
|
|
int vector;
|
|
|
|
cpumask_t mask;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
if (!IO_APIC_IRQ(irq)) {
|
|
|
|
apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
|
|
|
|
ioapic);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2006-10-04 09:16:51 +00:00
|
|
|
/*
|
|
|
|
* IRQs < 16 are already in the irq_2_pin[] map
|
|
|
|
*/
|
|
|
|
if (irq >= 16)
|
|
|
|
add_pin_to_irq(irq, ioapic, pin);
|
|
|
|
|
|
|
|
|
2006-10-08 13:47:55 +00:00
|
|
|
vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
|
2006-10-04 09:16:51 +00:00
|
|
|
if (vector < 0)
|
|
|
|
return vector;
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
|
|
|
|
* Note that we mask (disable) IRQs now -- these get enabled when the
|
|
|
|
* corresponding device driver registers for this IRQ.
|
|
|
|
*/
|
|
|
|
|
|
|
|
memset(&entry,0,sizeof(entry));
|
|
|
|
|
|
|
|
entry.delivery_mode = INT_DELIVERY_MODE;
|
|
|
|
entry.dest_mode = INT_DEST_MODE;
|
2006-10-04 09:16:51 +00:00
|
|
|
entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
|
[ACPI] ACPICA 20050930
Completed a major overhaul of the Resource Manager code -
specifically, optimizations in the area of the AML/internal
resource conversion code. The code has been optimized to
simplify and eliminate duplicated code, CPU stack use has
been decreased by optimizing function parameters and local
variables, and naming conventions across the manager have
been standardized for clarity and ease of maintenance (this
includes function, parameter, variable, and struct/typedef
names.)
All Resource Manager dispatch and information tables have
been moved to a single location for clarity and ease of
maintenance. One new file was created, named "rsinfo.c".
The ACPI return macros (return_ACPI_STATUS, etc.) have
been modified to guarantee that the argument is
not evaluated twice, making them less prone to macro
side-effects. However, since there exists the possibility
of additional stack use if a particular compiler cannot
optimize them (such as in the debug generation case),
the original macros are optionally available. Note that
some invocations of the return_VALUE macro may now cause
size mismatch warnings; the return_UINT8 and return_UINT32
macros are provided to eliminate these. (From Randy Dunlap)
Implemented a new mechanism to enable debug tracing for
individual control methods. A new external interface,
acpi_debug_trace(), is provided to enable this mechanism. The
intent is to allow the host OS to easily enable and disable
tracing for problematic control methods. This interface
can be easily exposed to a user or debugger interface if
desired. See the file psxface.c for details.
acpi_ut_callocate() will now return a valid pointer if a
length of zero is specified - a length of one is used
and a warning is issued. This matches the behavior of
acpi_ut_allocate().
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2005-09-30 23:03:00 +00:00
|
|
|
entry.trigger = triggering;
|
|
|
|
entry.polarity = polarity;
|
2005-04-16 22:20:36 +00:00
|
|
|
entry.mask = 1; /* Disabled (masked) */
|
2006-10-04 09:16:51 +00:00
|
|
|
entry.vector = vector & 0xff;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
|
|
|
|
"IRQ %d Mode:%i Active:%i)\n", ioapic,
|
|
|
|
mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
|
[ACPI] ACPICA 20050930
Completed a major overhaul of the Resource Manager code -
specifically, optimizations in the area of the AML/internal
resource conversion code. The code has been optimized to
simplify and eliminate duplicated code, CPU stack use has
been decreased by optimizing function parameters and local
variables, and naming conventions across the manager have
been standardized for clarity and ease of maintenance (this
includes function, parameter, variable, and struct/typedef
names.)
All Resource Manager dispatch and information tables have
been moved to a single location for clarity and ease of
maintenance. One new file was created, named "rsinfo.c".
The ACPI return macros (return_ACPI_STATUS, etc.) have
been modified to guarantee that the argument is
not evaluated twice, making them less prone to macro
side-effects. However, since there exists the possibility
of additional stack use if a particular compiler cannot
optimize them (such as in the debug generation case),
the original macros are optionally available. Note that
some invocations of the return_VALUE macro may now cause
size mismatch warnings; the return_UINT8 and return_UINT32
macros are provided to eliminate these. (From Randy Dunlap)
Implemented a new mechanism to enable debug tracing for
individual control methods. A new external interface,
acpi_debug_trace(), is provided to enable this mechanism. The
intent is to allow the host OS to easily enable and disable
tracing for problematic control methods. This interface
can be easily exposed to a user or debugger interface if
desired. See the file psxface.c for details.
acpi_ut_callocate() will now return a valid pointer if a
length of zero is specified - a length of one is used
and a warning is issued. This matches the behavior of
acpi_ut_allocate().
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2005-09-30 23:03:00 +00:00
|
|
|
triggering, polarity);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
[ACPI] ACPICA 20050930
Completed a major overhaul of the Resource Manager code -
specifically, optimizations in the area of the AML/internal
resource conversion code. The code has been optimized to
simplify and eliminate duplicated code, CPU stack use has
been decreased by optimizing function parameters and local
variables, and naming conventions across the manager have
been standardized for clarity and ease of maintenance (this
includes function, parameter, variable, and struct/typedef
names.)
All Resource Manager dispatch and information tables have
been moved to a single location for clarity and ease of
maintenance. One new file was created, named "rsinfo.c".
The ACPI return macros (return_ACPI_STATUS, etc.) have
been modified to guarantee that the argument is
not evaluated twice, making them less prone to macro
side-effects. However, since there exists the possibility
of additional stack use if a particular compiler cannot
optimize them (such as in the debug generation case),
the original macros are optionally available. Note that
some invocations of the return_VALUE macro may now cause
size mismatch warnings; the return_UINT8 and return_UINT32
macros are provided to eliminate these. (From Randy Dunlap)
Implemented a new mechanism to enable debug tracing for
individual control methods. A new external interface,
acpi_debug_trace(), is provided to enable this mechanism. The
intent is to allow the host OS to easily enable and disable
tracing for problematic control methods. This interface
can be easily exposed to a user or debugger interface if
desired. See the file psxface.c for details.
acpi_ut_callocate() will now return a valid pointer if a
length of zero is specified - a length of one is used
and a warning is issued. This matches the behavior of
acpi_ut_allocate().
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2005-09-30 23:03:00 +00:00
|
|
|
ioapic_register_intr(irq, entry.vector, triggering);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
if (!ioapic && (irq < 16))
|
|
|
|
disable_8259A_irq(irq);
|
|
|
|
|
2006-09-26 08:52:30 +00:00
|
|
|
ioapic_write_entry(ioapic, pin, entry);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_lock_irqsave(&ioapic_lock, flags);
|
2006-10-04 09:16:46 +00:00
|
|
|
set_native_irq_info(irq, TARGET_CPUS);
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_unlock_irqrestore(&ioapic_lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-08-24 16:07:20 +00:00
|
|
|
#endif /* CONFIG_ACPI */
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function currently is only a helper for the i386 smp boot process where
|
|
|
|
* we need to reprogram the ioredtbls to cater for the cpus which have come online
|
|
|
|
* so mask in all cases should simply be TARGET_CPUS
|
|
|
|
*/
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2005-04-16 22:20:36 +00:00
|
|
|
void __init setup_ioapic_dest(void)
|
|
|
|
{
|
|
|
|
int pin, ioapic, irq, irq_entry;
|
|
|
|
|
|
|
|
if (skip_ioapic_setup == 1)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
|
|
|
|
for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
|
|
|
|
irq_entry = find_irq_entry(ioapic, pin, mp_INT);
|
|
|
|
if (irq_entry == -1)
|
|
|
|
continue;
|
|
|
|
irq = pin_2_irq(irq_entry, ioapic, pin);
|
|
|
|
set_ioapic_affinity_irq(irq, TARGET_CPUS);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
[PATCH] x86/x86_64: deferred handling of writes to /proc/irqxx/smp_affinity
When handling writes to /proc/irq, current code is re-programming rte
entries directly. This is not recommended and could potentially cause
chipset's to lockup, or cause missing interrupts.
CONFIG_IRQ_BALANCE does this correctly, where it re-programs only when the
interrupt is pending. The same needs to be done for /proc/irq handling as well.
Otherwise user space irq balancers are really not doing the right thing.
- Changed pending_irq_balance_cpumask to pending_irq_migrate_cpumask for
lack of a generic name.
- added move_irq out of IRQ_BALANCE, and added this same to X86_64
- Added new proc handler for write, so we can do deferred write at irq
handling time.
- Display of /proc/irq/XX/smp_affinity used to display CPU_MASKALL, instead
it now shows only active cpu masks, or exactly what was set.
- Provided a common move_irq implementation, instead of duplicating
when using generic irq framework.
Tested on i386/x86_64 and ia64 with CONFIG_PCI_MSI turned on and off.
Tested UP builds as well.
MSI testing: tbd: I have cards, need to look for a x-over cable, although I
did test an earlier version of this patch. Will test in a couple days.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Zwane Mwaikambo <zwane@holomorphy.com>
Grudgingly-acked-by: Andi Kleen <ak@muc.de>
Signed-off-by: Coywolf Qi Hunt <coywolf@lovecn.org>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-06 22:16:15 +00:00
|
|
|
#endif
|