340 lines
9.4 KiB
C
340 lines
9.4 KiB
C
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/* $Id: irq_ipr.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $
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*
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* linux/arch/sh/kernel/irq_ipr.c
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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*
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* Interrupt handling for IPR-based IRQ.
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*
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* Supported system:
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* On-chip supporting modules (TMU, RTC, etc.).
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* On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
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* Hitachi SolutionEngine external I/O:
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* MS7709SE01, MS7709ASE01, and MS7750SE01
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*
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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struct ipr_data {
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unsigned int addr; /* Address of Interrupt Priority Register */
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int shift; /* Shifts of the 16-bit data */
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int priority; /* The priority */
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};
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static struct ipr_data ipr_data[NR_IRQS];
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static void enable_ipr_irq(unsigned int irq);
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static void disable_ipr_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_ipr_irq disable_ipr_irq
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static void mask_and_ack_ipr(unsigned int);
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static void end_ipr_irq(unsigned int irq);
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static unsigned int startup_ipr_irq(unsigned int irq)
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{
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enable_ipr_irq(irq);
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return 0; /* never anything pending */
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}
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static struct hw_interrupt_type ipr_irq_type = {
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"IPR-IRQ",
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startup_ipr_irq,
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shutdown_ipr_irq,
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enable_ipr_irq,
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disable_ipr_irq,
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mask_and_ack_ipr,
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end_ipr_irq
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};
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static void disable_ipr_irq(unsigned int irq)
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{
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unsigned long val, flags;
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unsigned int addr = ipr_data[irq].addr;
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unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
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/* Set the priority in IPR to 0 */
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local_irq_save(flags);
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val = ctrl_inw(addr);
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val &= mask;
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ctrl_outw(val, addr);
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local_irq_restore(flags);
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}
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static void enable_ipr_irq(unsigned int irq)
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{
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unsigned long val, flags;
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unsigned int addr = ipr_data[irq].addr;
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int priority = ipr_data[irq].priority;
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unsigned short value = (priority << ipr_data[irq].shift);
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/* Set priority in IPR back to original value */
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local_irq_save(flags);
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val = ctrl_inw(addr);
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val |= value;
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ctrl_outw(val, addr);
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local_irq_restore(flags);
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}
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static void mask_and_ack_ipr(unsigned int irq)
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{
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disable_ipr_irq(irq);
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
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/* This is needed when we use edge triggered setting */
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/* XXX: Is it really needed? */
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if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
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/* Clear external interrupt request */
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int a = ctrl_inb(INTC_IRR0);
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a &= ~(1 << (irq - IRQ0_IRQ));
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ctrl_outb(a, INTC_IRR0);
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}
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#endif
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}
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static void end_ipr_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_ipr_irq(irq);
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}
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void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
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{
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disable_irq_nosync(irq);
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ipr_data[irq].addr = addr;
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ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
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ipr_data[irq].priority = priority;
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irq_desc[irq].handler = &ipr_irq_type;
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disable_ipr_irq(irq);
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}
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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static unsigned char pint_map[256];
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static unsigned long portcr_mask = 0;
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static void enable_pint_irq(unsigned int irq);
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static void disable_pint_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_pint_irq disable_pint_irq
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static void mask_and_ack_pint(unsigned int);
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static void end_pint_irq(unsigned int irq);
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static unsigned int startup_pint_irq(unsigned int irq)
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{
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enable_pint_irq(irq);
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return 0; /* never anything pending */
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}
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static struct hw_interrupt_type pint_irq_type = {
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"PINT-IRQ",
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startup_pint_irq,
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shutdown_pint_irq,
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enable_pint_irq,
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disable_pint_irq,
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mask_and_ack_pint,
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end_pint_irq
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};
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static void disable_pint_irq(unsigned int irq)
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{
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unsigned long val, flags;
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local_irq_save(flags);
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val = ctrl_inw(INTC_INTER);
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val &= ~(1 << (irq - PINT_IRQ_BASE));
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ctrl_outw(val, INTC_INTER); /* disable PINTn */
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portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
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local_irq_restore(flags);
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}
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static void enable_pint_irq(unsigned int irq)
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{
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unsigned long val, flags;
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local_irq_save(flags);
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val = ctrl_inw(INTC_INTER);
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val |= 1 << (irq - PINT_IRQ_BASE);
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ctrl_outw(val, INTC_INTER); /* enable PINTn */
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portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
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local_irq_restore(flags);
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}
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static void mask_and_ack_pint(unsigned int irq)
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{
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disable_pint_irq(irq);
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}
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static void end_pint_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_pint_irq(irq);
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}
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void make_pint_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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irq_desc[irq].handler = &pint_irq_type;
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disable_pint_irq(irq);
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}
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#endif
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void __init init_IRQ(void)
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{
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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int i;
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#endif
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make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
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make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
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#if defined(CONFIG_SH_RTC)
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make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
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#endif
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#ifdef SCI_ERI_IRQ
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make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
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make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
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make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
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#endif
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#ifdef SCIF1_ERI_IRQ
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make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
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make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
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make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
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make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
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make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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#endif
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#ifdef SCIF_ERI_IRQ
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make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
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make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
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make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
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make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
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#endif
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#ifdef IRDA_ERI_IRQ
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make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
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make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
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make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
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make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
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/*
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* Initialize the Interrupt Controller (INTC)
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* registers to their power on values
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*/
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/*
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* Enable external irq (INTC IRQ mode).
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* You should set corresponding bits of PFC to "00"
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* to enable these interrupts.
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*/
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make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
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make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
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make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
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make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
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make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
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make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
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#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
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make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
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make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
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enable_ipr_irq(PINT0_IRQ);
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enable_ipr_irq(PINT8_IRQ);
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for(i = 0; i < 16; i++)
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make_pint_irq(PINT_IRQ_BASE + i);
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for(i = 0; i < 256; i++)
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{
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if(i & 1) pint_map[i] = 0;
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else if(i & 2) pint_map[i] = 1;
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else if(i & 4) pint_map[i] = 2;
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else if(i & 8) pint_map[i] = 3;
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else if(i & 0x10) pint_map[i] = 4;
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else if(i & 0x20) pint_map[i] = 5;
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else if(i & 0x40) pint_map[i] = 6;
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else if(i & 0x80) pint_map[i] = 7;
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}
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#endif /* !CONFIG_CPU_SUBTYPE_SH7300 */
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#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 || CONFIG_CPU_SUBTYPE_SH7300*/
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#ifdef CONFIG_CPU_SUBTYPE_ST40
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init_IRQ_intc2();
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#endif
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/* Perform the machine specific initialisation */
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if (sh_mv.mv_init_irq != NULL) {
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sh_mv.mv_init_irq();
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}
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}
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
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int ipr_irq_demux(int irq)
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{
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#if !defined(CONFIG_CPU_SUBTYPE_SH7300)
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unsigned long creg, dreg, d, sav;
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if(irq == PINT0_IRQ)
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{
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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creg = PORT_PACR;
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dreg = PORT_PADR;
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#else
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creg = PORT_PCCR;
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dreg = PORT_PCDR;
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#endif
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sav = ctrl_inw(creg);
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ctrl_outw(sav | portcr_mask, creg);
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d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff;
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ctrl_outw(sav, creg);
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if(d == 0) return irq;
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return PINT_IRQ_BASE + pint_map[d];
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}
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else if(irq == PINT8_IRQ)
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{
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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creg = PORT_PBCR;
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dreg = PORT_PBDR;
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#else
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creg = PORT_PFCR;
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dreg = PORT_PFDR;
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#endif
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sav = ctrl_inw(creg);
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ctrl_outw(sav | (portcr_mask >> 16), creg);
|
||
|
|
d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff;
|
||
|
|
ctrl_outw(sav, creg);
|
||
|
|
if(d == 0) return irq;
|
||
|
|
return PINT_IRQ_BASE + 8 + pint_map[d];
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
return irq;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
EXPORT_SYMBOL(make_ipr_irq);
|
||
|
|
|