82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
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/*
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* A collection of structures, addresses, and values associated with
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* the Embedded Planet RPX6 (or RPX Super) MPC8260 board.
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* Copied from the RPX-Classic and SBS8260 stuff.
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*
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* Copyright (c) 2001 Dan Malek <dan@embeddededge.com>
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_PLATFORMS_RPX8260_H__
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#define __ASM_PLATFORMS_RPX8260_H__
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/* A Board Information structure that is given to a program when
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* prom starts it up.
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*/
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typedef struct bd_info {
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unsigned int bi_memstart; /* Memory start address */
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unsigned int bi_memsize; /* Memory (end) size in bytes */
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unsigned int bi_nvsize; /* NVRAM size in bytes (can be 0) */
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unsigned int bi_intfreq; /* Internal Freq, in Hz */
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unsigned int bi_busfreq; /* Bus Freq, in MHz */
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unsigned int bi_cpmfreq; /* CPM Freq, in MHz */
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unsigned int bi_brgfreq; /* BRG Freq, in MHz */
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unsigned int bi_vco; /* VCO Out from PLL */
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unsigned int bi_baudrate; /* Default console baud rate */
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unsigned int bi_immr; /* IMMR when called from boot rom */
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unsigned char bi_enetaddr[6];
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} bd_t;
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extern bd_t m8xx_board_info;
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/* Memory map is configured by the PROM startup.
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* We just map a few things we need. The CSR is actually 4 byte-wide
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* registers that can be accessed as 8-, 16-, or 32-bit values.
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*/
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#define CPM_MAP_ADDR ((uint)0xf0000000)
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#define RPX_CSR_ADDR ((uint)0xfa000000)
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#define RPX_CSR_SIZE ((uint)(512 * 1024))
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#define RPX_NVRTC_ADDR ((uint)0xfa080000)
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#define RPX_NVRTC_SIZE ((uint)(512 * 1024))
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/* The RPX6 has 16, byte wide control/status registers.
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* Not all are used (yet).
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*/
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extern volatile u_char *rpx6_csr_addr;
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/* Things of interest in the CSR.
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*/
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#define BCSR0_ID_MASK ((u_char)0xf0) /* Read only */
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#define BCSR0_SWITCH_MASK ((u_char)0x0f) /* Read only */
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#define BCSR1_XCVR_SMC1 ((u_char)0x80)
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#define BCSR1_XCVR_SMC2 ((u_char)0x40)
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#define BCSR2_FLASH_WENABLE ((u_char)0x20)
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#define BCSR2_NVRAM_ENABLE ((u_char)0x10)
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#define BCSR2_ALT_IRQ2 ((u_char)0x08)
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#define BCSR2_ALT_IRQ3 ((u_char)0x04)
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#define BCSR2_PRST ((u_char)0x02) /* Force reset */
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#define BCSR2_ENPRST ((u_char)0x01) /* Enable POR */
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#define BCSR3_MODCLK_MASK ((u_char)0xe0)
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#define BCSR3_ENCLKHDR ((u_char)0x10)
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#define BCSR3_LED5 ((u_char)0x04) /* 0 == on */
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#define BCSR3_LED6 ((u_char)0x02) /* 0 == on */
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#define BCSR3_LED7 ((u_char)0x01) /* 0 == on */
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#define BCSR4_EN_PHY ((u_char)0x80) /* Enable PHY */
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#define BCSR4_EN_MII ((u_char)0x40) /* Enable PHY */
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#define BCSR4_MII_READ ((u_char)0x04)
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#define BCSR4_MII_MDC ((u_char)0x02)
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#define BCSR4_MII_MDIO ((u_char)0x01)
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#define BCSR13_FETH_IRQMASK ((u_char)0xf0)
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#define BCSR15_FETH_IRQ ((u_char)0x20)
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#define PHY_INTERRUPT SIU_INT_IRQ7
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/* For our show_cpuinfo hooks. */
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#define CPUINFO_VENDOR "Embedded Planet"
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#define CPUINFO_MACHINE "EP8260 PowerPC"
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/* Warm reset vector. */
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#define BOOTROM_RESTART_ADDR ((uint)0xfff00104)
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#endif /* __ASM_PLATFORMS_RPX8260_H__ */
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#endif /* __KERNEL__ */
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