438 lines
14 KiB
C
438 lines
14 KiB
C
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/*
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* Copyright (c) 2000-2005 ZyDAS Technology Corporation
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* Copyright (c) 2007-2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/* Module Name : ud_defs.h */
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/* */
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/* Abstract */
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/* This module contains USB data structure definitions. */
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/* */
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/* NOTES */
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/* None */
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/* */
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/************************************************************************/
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#ifndef _HPUSB_H
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#define _HPUSB_H
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#define ZM_OTUS_ENABLE_RETRY_FREQ_CHANGE
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#define ZM_BEACON_BUFFER_ADDRESS 0x117900
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#define ZM_MAX_CMD_SIZE 64
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#define ZM_HAL_MAX_EEPROM_REQ 510
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#define ZM_HAL_MAX_EEPROM_PRQ 2
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/* For USB STREAM mode */
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#ifdef ZM_DISABLE_AMSDU8K_SUPPORT
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#define ZM_MAX_USB_IN_TRANSFER_SIZE 4096
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#else
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#define ZM_MAX_USB_IN_TRANSFER_SIZE 8192
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#endif
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#define ZM_USB_STREAM_MODE_TAG_LEN 4
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#define ZM_USB_STREAM_MODE_TAG 0x4e00
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#define ZM_USB_MAX_EPINT_BUFFER 64
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struct zsCmdQ
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{
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u16_t src;
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u16_t cmdLen;
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u8_t* buf;
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u32_t cmd[ZM_MAX_CMD_SIZE/4];
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};
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struct zsCommand
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{
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u16_t delayWcmdCount;
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u32_t delayWcmdAddr[(ZM_CMD_QUEUE_SIZE-4)/4];
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u32_t delayWcmdVal[(ZM_CMD_QUEUE_SIZE-4)/4];
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};
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struct zsHalRxInfo
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{
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u32_t currentRSSI[7]; /* RSSI combined */
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u32_t currentRxEVM[14];
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u32_t currentRxDataMT;
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u32_t currentRxDataMCS;
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u32_t currentRxDataBW;
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u32_t currentRxDataSG;
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};
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struct zsHpPriv
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{
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u16_t hwFrequency;
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u8_t hwBw40;
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u8_t hwExtOffset;
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u8_t disableDfsCh;
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u32_t halCapability;
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/* Fortunately the second loop can be disabled with a bit */
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/* called en_pd_dc_offset_thr */
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u8_t hwNotFirstInit;
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/* command queue */
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u16_t cmdHead;
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u16_t cmdTail;
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#ifdef ZM_XP_USB_MULTCMD
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u16_t cmdSend; // Used for Mult send USB cmd
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#endif
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struct zsCmdQ cmdQ[ZM_CMD_QUEUE_SIZE];
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u16_t cmdPending;
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struct zsCommand cmd; /* buffer for delayed commands */
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u8_t ledMode[2];
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u32_t ctlBusy;
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u32_t extBusy;
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/*
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* ANI & Radar support.
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*/
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u32_t procPhyErr; /* Process Phy errs */
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u8_t hasHwPhyCounters; /* Hardware has phy counters */
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u32_t aniPeriod; /* ani update list period */
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struct zsAniStats stats; /* various statistics */
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struct zsAniState *curani; /* cached last reference */
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struct zsAniState ani[50]; /* per-channel state */
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/*
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* Ani tables that change between the 5416 and 5312.
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* These get set at attach time.
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* XXX don't belong here
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* XXX need better explanation
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*/
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s32_t totalSizeDesired[5];
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s32_t coarseHigh[5];
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s32_t coarseLow[5];
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s32_t firpwr[5];
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/*
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* ANI related PHY register value.
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*/
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u32_t regPHYDesiredSZ;
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u32_t regPHYFindSig;
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u32_t regPHYAgcCtl1;
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u32_t regPHYSfcorr;
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u32_t regPHYSfcorrLow;
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u32_t regPHYTiming5;
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u32_t regPHYCckDetect;
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u32_t eepromImage[1024];
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u32_t eepromImageIndex;
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u32_t eepromImageRdReq;
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u8_t halReInit;
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u8_t OpFlags;
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u8_t tPow2xCck[4];
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u8_t tPow2x2g[4];
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u8_t tPow2x2g24HeavyClipOffset;
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u8_t tPow2x2gHt20[8];
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u8_t tPow2x2gHt40[8];
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u8_t tPow2x5g[4];
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u8_t tPow2x5gHt20[8];
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u8_t tPow2x5gHt40[8];
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/* hwBBHeavyClip : used compatibility */
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/* 0 : dongle not support. */
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/* !0: support heavy clip. */
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u8_t hwBBHeavyClip;
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u8_t enableBBHeavyClip; /* 0=>force disable 1=>enable */
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u8_t doBBHeavyClip; /* set 1 if heavy clip need by each frequency switch */
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u32_t setValueHeavyClip; /* save setting value for heavy clip when completed routine */
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/*
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* Rxdata RSSI, EVM, Rate etc...
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*/
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struct zsHalRxInfo halRxInfo;
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u32_t usbSendBytes;
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u32_t usbAcSendBytes[4];
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u16_t aggMaxDurationBE;
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u32_t aggPktNum;
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u16_t txop[4];
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u16_t cwmin[4];
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u16_t cwmax[4];
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u8_t strongRSSI;
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u8_t rxStrongRSSI;
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u8_t slotType; //0->20us, 1=>9us
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#ifdef ZM_OTUS_RX_STREAM_MODE
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u16_t usbRxRemainLen;
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u16_t usbRxPktLen;
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u16_t usbRxPadLen;
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u16_t usbRxTransferLen;
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zbuf_t *remainBuf;
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#endif
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u8_t dot11Mode;
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u8_t ibssBcnEnabled;
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u32_t ibssBcnInterval;
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// For re-issue the frequency change command
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u32_t latestFrequency;
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u8_t latestBw40;
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u8_t latestExtOffset;
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u8_t freqRetryCounter;
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u8_t recordFreqRetryCounter;
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u8_t isSiteSurvey;
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u8_t coldResetNeedFreq;
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u64_t camRollCallTable;
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u8_t currentAckRtsTpc;
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/* #1 Save the initial value of the related RIFS register settings */
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//u32_t isInitialPhy;
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u32_t initDesiredSigSize;
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u32_t initAGC;
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u32_t initAgcControl;
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u32_t initSearchStartDelay;
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u32_t initRIFSSearchParams;
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u32_t initFastChannelChangeControl;
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/* Dynamic SIFS for retransmission event */
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u8_t retransmissionEvent;
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u8_t latestSIFS;
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};
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extern u32_t zfHpLoadEEPROMFromFW(zdev_t* dev);
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typedef u8_t A_UINT8;
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typedef s8_t A_INT8;
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typedef u16_t A_UINT16;
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typedef u32_t A_UINT32;
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#define __ATTRIB_PACK
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#pragma pack (push, 1)
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#define AR5416_EEP_VER 0xE
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#define AR5416_EEP_VER_MINOR_MASK 0xFFF
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#define AR5416_EEP_NO_BACK_VER 0x1
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#define AR5416_EEP_MINOR_VER_2 0x2 // Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc
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#define AR5416_EEP_MINOR_VER_3 0x3 // Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable
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// 16-bit offset location start of calibration struct
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#define AR5416_EEP_START_LOC 256
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#define AR5416_NUM_5G_CAL_PIERS 8
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#define AR5416_NUM_2G_CAL_PIERS 4
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#define AR5416_NUM_5G_20_TARGET_POWERS 8
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#define AR5416_NUM_5G_40_TARGET_POWERS 8
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#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
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#define AR5416_NUM_2G_20_TARGET_POWERS 4
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#define AR5416_NUM_2G_40_TARGET_POWERS 4
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#define AR5416_NUM_CTLS 24
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#define AR5416_NUM_BAND_EDGES 8
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#define AR5416_NUM_PD_GAINS 4
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#define AR5416_PD_GAINS_IN_MASK 4
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#define AR5416_PD_GAIN_ICEPTS 5
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#define AR5416_EEPROM_MODAL_SPURS 5
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#define AR5416_MAX_RATE_POWER 63
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#define AR5416_NUM_PDADC_VALUES 128
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#define AR5416_NUM_RATES 16
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#define AR5416_BCHAN_UNUSED 0xFF
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#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
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#define AR5416_OPFLAGS_11A 0x01
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#define AR5416_OPFLAGS_11G 0x02
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#define AR5416_OPFLAGS_5G_HT40 0x04
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#define AR5416_OPFLAGS_2G_HT40 0x08
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#define AR5416_OPFLAGS_5G_HT20 0x10
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#define AR5416_OPFLAGS_2G_HT20 0x20
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#define AR5416_EEPMISC_BIG_ENDIAN 0x01
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#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
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#define AR5416_MAX_CHAINS 2
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#define AR5416_ANT_16S 25
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#define AR5416_NUM_ANT_CHAIN_FIELDS 7
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#define AR5416_NUM_ANT_COMMON_FIELDS 4
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#define AR5416_SIZE_ANT_CHAIN_FIELD 3
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#define AR5416_SIZE_ANT_COMMON_FIELD 4
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#define AR5416_ANT_CHAIN_MASK 0x7
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#define AR5416_ANT_COMMON_MASK 0xf
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#define AR5416_CHAIN_0_IDX 0
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#define AR5416_CHAIN_1_IDX 1
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#define AR5416_CHAIN_2_IDX 2
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/* Capabilities Enum */
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typedef enum {
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EEPCAP_COMPRESS_DIS = 0x0001,
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EEPCAP_AES_DIS = 0x0002,
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EEPCAP_FASTFRAME_DIS = 0x0004,
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EEPCAP_BURST_DIS = 0x0008,
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EEPCAP_MAXQCU_M = 0x01F0,
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EEPCAP_MAXQCU_S = 4,
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EEPCAP_HEAVY_CLIP_EN = 0x0200,
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EEPCAP_KC_ENTRIES_M = 0xF000,
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EEPCAP_KC_ENTRIES_S = 12,
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} EEPROM_CAPABILITIES;
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typedef enum Ar5416_Rates {
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rate6mb, rate9mb, rate12mb, rate18mb,
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rate24mb, rate36mb, rate48mb, rate54mb,
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rate1l, rate2l, rate2s, rate5_5l,
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rate5_5s, rate11l, rate11s, rateXr,
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rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
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rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
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rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
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rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
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rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
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Ar5416RateSize
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} AR5416_RATES;
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typedef struct eepFlags {
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A_UINT8 opFlags;
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A_UINT8 eepMisc;
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} __ATTRIB_PACK EEP_FLAGS;
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#define AR5416_CHECKSUM_LOCATION (AR5416_EEP_START_LOC + 1)
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typedef struct BaseEepHeader {
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A_UINT16 length;
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A_UINT16 checksum;
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A_UINT16 version;
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EEP_FLAGS opCapFlags;
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A_UINT16 regDmn[2];
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A_UINT8 macAddr[6];
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A_UINT8 rxMask;
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A_UINT8 txMask;
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A_UINT16 rfSilent;
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A_UINT16 blueToothOptions;
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A_UINT16 deviceCap;
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A_UINT32 binBuildNumber;
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A_UINT8 deviceType;
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A_UINT8 futureBase[33];
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} __ATTRIB_PACK BASE_EEP_HEADER; // 64 B
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typedef struct spurChanStruct {
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A_UINT16 spurChan;
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A_UINT8 spurRangeLow;
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A_UINT8 spurRangeHigh;
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} __ATTRIB_PACK SPUR_CHAN;
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typedef struct ModalEepHeader {
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A_UINT32 antCtrlChain[AR5416_MAX_CHAINS]; // 12
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A_UINT32 antCtrlCommon; // 4
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A_INT8 antennaGainCh[AR5416_MAX_CHAINS]; // 3
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A_UINT8 switchSettling; // 1
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A_UINT8 txRxAttenCh[AR5416_MAX_CHAINS]; // 3
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A_UINT8 rxTxMarginCh[AR5416_MAX_CHAINS]; // 3
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A_INT8 adcDesiredSize; // 1
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A_INT8 pgaDesiredSize; // 1
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A_UINT8 xlnaGainCh[AR5416_MAX_CHAINS]; // 3
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A_UINT8 txEndToXpaOff; // 1
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A_UINT8 txEndToRxOn; // 1
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A_UINT8 txFrameToXpaOn; // 1
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A_UINT8 thresh62; // 1
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A_INT8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3
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A_UINT8 xpdGain; // 1
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A_UINT8 xpd; // 1
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A_INT8 iqCalICh[AR5416_MAX_CHAINS]; // 1
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A_INT8 iqCalQCh[AR5416_MAX_CHAINS]; // 1
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A_UINT8 pdGainOverlap; // 1
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A_UINT8 ob; // 1
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A_UINT8 db; // 1
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A_UINT8 xpaBiasLvl; // 1
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A_UINT8 pwrDecreaseFor2Chain; // 1
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A_UINT8 pwrDecreaseFor3Chain; // 1 -> 48 B
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A_UINT8 txFrameToDataStart; // 1
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A_UINT8 txFrameToPaOn; // 1
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A_UINT8 ht40PowerIncForPdadc; // 1
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A_UINT8 bswAtten[AR5416_MAX_CHAINS]; // 3
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A_UINT8 bswMargin[AR5416_MAX_CHAINS]; // 3
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A_UINT8 swSettleHt40; // 1
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A_UINT8 futureModal[22]; //
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SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
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} __ATTRIB_PACK MODAL_EEP_HEADER; // == 100 B
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typedef struct calDataPerFreq {
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A_UINT8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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A_UINT8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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} __ATTRIB_PACK CAL_DATA_PER_FREQ;
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typedef struct CalTargetPowerLegacy {
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A_UINT8 bChannel;
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A_UINT8 tPow2x[4];
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} __ATTRIB_PACK CAL_TARGET_POWER_LEG;
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typedef struct CalTargetPowerHt {
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A_UINT8 bChannel;
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A_UINT8 tPow2x[8];
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} __ATTRIB_PACK CAL_TARGET_POWER_HT;
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#if defined(ARCH_BIG_ENDIAN) || defined(BIG_ENDIAN)
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typedef struct CalCtlEdges {
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A_UINT8 bChannel;
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A_UINT8 flag :2,
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tPower :6;
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} __ATTRIB_PACK CAL_CTL_EDGES;
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#else
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typedef struct CalCtlEdges {
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A_UINT8 bChannel;
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A_UINT8 tPower :6,
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flag :2;
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} __ATTRIB_PACK CAL_CTL_EDGES;
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#endif
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typedef struct CalCtlData {
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CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
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} __ATTRIB_PACK CAL_CTL_DATA;
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typedef struct ar5416Eeprom {
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BASE_EEP_HEADER baseEepHeader; // 64 B
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A_UINT8 custData[64]; // 64 B
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MODAL_EEP_HEADER modalHeader[2]; // 200 B
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A_UINT8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
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A_UINT8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
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CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
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CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
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CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
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||
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CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
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CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
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||
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CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
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||
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CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
|
||
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A_UINT8 ctlIndex[AR5416_NUM_CTLS];
|
||
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CAL_CTL_DATA ctlData[AR5416_NUM_CTLS];
|
||
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A_UINT8 padding;
|
||
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} __ATTRIB_PACK AR5416_EEPROM;
|
||
|
|
||
|
#pragma pack (pop)
|
||
|
|
||
|
typedef enum ConformanceTestLimits {
|
||
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FCC = 0x10,
|
||
|
MKK = 0x40,
|
||
|
ETSI = 0x30,
|
||
|
SD_NO_CTL = 0xE0,
|
||
|
NO_CTL = 0xFF,
|
||
|
CTL_MODE_M = 0xF,
|
||
|
CTL_11A = 0,
|
||
|
CTL_11B = 1,
|
||
|
CTL_11G = 2,
|
||
|
CTL_TURBO = 3,
|
||
|
CTL_108G = 4,
|
||
|
CTL_2GHT20 = 5,
|
||
|
CTL_5GHT20 = 6,
|
||
|
CTL_2GHT40 = 7,
|
||
|
CTL_5GHT40 = 8,
|
||
|
} ATH_CTLS;
|
||
|
|
||
|
#endif /* #ifndef _HPUSB_H */
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