2006-05-24 00:18:44 +00:00
|
|
|
#
|
|
|
|
|
# DMA engine configuration
|
|
|
|
|
#
|
|
|
|
|
|
2007-10-16 08:27:42 +00:00
|
|
|
menuconfig DMADEVICES
|
2007-11-29 00:21:43 +00:00
|
|
|
bool "DMA Engine support"
|
2008-06-27 08:21:11 +00:00
|
|
|
depends on !HIGHMEM64G && HAS_DMA
|
2007-10-16 08:27:42 +00:00
|
|
|
help
|
2007-11-29 00:21:43 +00:00
|
|
|
DMA engines can do asynchronous data transfers without
|
|
|
|
|
involving the host CPU. Currently, this framework can be
|
|
|
|
|
used to offload memory copies in the network stack and
|
2008-06-27 08:21:11 +00:00
|
|
|
RAID operations in the MD driver. This menu only presents
|
|
|
|
|
DMA Device drivers supported by the configured arch, it may
|
|
|
|
|
be empty in some cases.
|
2007-10-16 08:27:42 +00:00
|
|
|
|
|
|
|
|
if DMADEVICES
|
|
|
|
|
|
|
|
|
|
comment "DMA Devices"
|
|
|
|
|
|
|
|
|
|
config INTEL_IOATDMA
|
|
|
|
|
tristate "Intel I/OAT DMA support"
|
|
|
|
|
depends on PCI && X86
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DCA
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Intel(R) I/OAT DMA engine present
|
|
|
|
|
in recent Intel Xeon chipsets.
|
|
|
|
|
|
|
|
|
|
Say Y here if you have such a chipset.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config INTEL_IOP_ADMA
|
|
|
|
|
tristate "Intel IOP ADMA support"
|
|
|
|
|
depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Intel(R) IOP Series RAID engines.
|
2006-05-24 00:18:44 +00:00
|
|
|
|
2008-07-08 18:59:42 +00:00
|
|
|
config DW_DMAC
|
|
|
|
|
tristate "Synopsys DesignWare AHB DMA support"
|
|
|
|
|
depends on AVR32
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
default y if CPU_AT32AP7000
|
|
|
|
|
help
|
|
|
|
|
Support the Synopsys DesignWare AHB DMA controller. This
|
|
|
|
|
can be integrated in chips such as the Atmel AT32ap7000.
|
|
|
|
|
|
2008-03-01 14:42:48 +00:00
|
|
|
config FSL_DMA
|
2008-09-27 00:00:11 +00:00
|
|
|
tristate "Freescale Elo and Elo Plus DMA support"
|
|
|
|
|
depends on FSL_SOC
|
2008-03-01 14:42:48 +00:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
---help---
|
2008-09-27 00:00:11 +00:00
|
|
|
Enable support for the Freescale Elo and Elo Plus DMA controllers.
|
|
|
|
|
The Elo is the DMA controller on some 82xx and 83xx parts, and the
|
|
|
|
|
Elo Plus is the DMA controller on 85xx and 86xx parts.
|
2008-03-01 14:42:48 +00:00
|
|
|
|
2008-07-08 18:58:36 +00:00
|
|
|
config MV_XOR
|
|
|
|
|
bool "Marvell XOR engine support"
|
|
|
|
|
depends on PLAT_ORION
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
---help---
|
|
|
|
|
Enable support for the Marvell XOR engine.
|
|
|
|
|
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19 22:36:21 +00:00
|
|
|
config MX3_IPU
|
|
|
|
|
bool "MX3x Image Processing Unit support"
|
|
|
|
|
depends on ARCH_MX3
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
If you plan to use the Image Processing unit in the i.MX3x, say
|
|
|
|
|
Y here. If unsure, select Y.
|
|
|
|
|
|
|
|
|
|
config MX3_IPU_IRQS
|
|
|
|
|
int "Number of dynamically mapped interrupts for IPU"
|
|
|
|
|
depends on MX3_IPU
|
|
|
|
|
range 2 137
|
|
|
|
|
default 4
|
|
|
|
|
help
|
|
|
|
|
Out of 137 interrupt sources on i.MX31 IPU only very few are used.
|
|
|
|
|
To avoid bloating the irq_desc[] array we allocate a sufficient
|
|
|
|
|
number of IRQ slots and map them dynamically to specific sources.
|
|
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
config DMA_ENGINE
|
2007-10-16 08:27:42 +00:00
|
|
|
bool
|
2006-05-24 00:18:44 +00:00
|
|
|
|
2006-06-18 04:24:58 +00:00
|
|
|
comment "DMA Clients"
|
2007-10-16 08:27:42 +00:00
|
|
|
depends on DMA_ENGINE
|
2006-06-18 04:24:58 +00:00
|
|
|
|
|
|
|
|
config NET_DMA
|
|
|
|
|
bool "Network: TCP receive copy offload"
|
|
|
|
|
depends on DMA_ENGINE && NET
|
2008-06-27 08:21:11 +00:00
|
|
|
default (INTEL_IOATDMA || FSL_DMA)
|
2007-10-16 08:27:42 +00:00
|
|
|
help
|
2006-06-18 04:24:58 +00:00
|
|
|
This enables the use of DMA engines in the network stack to
|
|
|
|
|
offload receive copy-to-user operations, freeing CPU cycles.
|
2008-06-27 08:21:11 +00:00
|
|
|
|
|
|
|
|
Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
|
|
|
|
|
say N.
|
2006-06-18 04:24:58 +00:00
|
|
|
|
2008-07-08 18:58:45 +00:00
|
|
|
config DMATEST
|
|
|
|
|
tristate "DMA Test client"
|
|
|
|
|
depends on DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Simple DMA test client. Say N unless you're debugging a
|
|
|
|
|
DMA Device driver.
|
|
|
|
|
|
2007-10-16 08:27:42 +00:00
|
|
|
endif
|
