81 lines
3.2 KiB
C
81 lines
3.2 KiB
C
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#ifndef _LINUX_FD1772REG_H
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#define _LINUX_FD1772REG_H
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/*
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** WD1772 stuff - originally from the M68K Linux
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* Modified for Archimedes by Dave Gilbert (gilbertd@cs.man.ac.uk)
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*/
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/* register codes */
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#define FDC1772SELREG_STP (0x80) /* command/status register */
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#define FDC1772SELREG_TRA (0x82) /* track register */
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#define FDC1772SELREG_SEC (0x84) /* sector register */
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#define FDC1772SELREG_DTA (0x86) /* data register */
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/* register names for FDC1772_READ/WRITE macros */
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#define FDC1772REG_CMD 0
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#define FDC1772REG_STATUS 0
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#define FDC1772REG_TRACK 2
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#define FDC1772REG_SECTOR 4
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#define FDC1772REG_DATA 6
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/* command opcodes */
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#define FDC1772CMD_RESTORE (0x00) /* - */
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#define FDC1772CMD_SEEK (0x10) /* | */
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#define FDC1772CMD_STEP (0x20) /* | TYP 1 Commands */
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#define FDC1772CMD_STIN (0x40) /* | */
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#define FDC1772CMD_STOT (0x60) /* - */
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#define FDC1772CMD_RDSEC (0x80) /* - TYP 2 Commands */
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#define FDC1772CMD_WRSEC (0xa0) /* - " */
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#define FDC1772CMD_RDADR (0xc0) /* - */
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#define FDC1772CMD_RDTRA (0xe0) /* | TYP 3 Commands */
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#define FDC1772CMD_WRTRA (0xf0) /* - */
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#define FDC1772CMD_FORCI (0xd0) /* - TYP 4 Command */
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/* command modifier bits */
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#define FDC1772CMDADD_SR6 (0x00) /* step rate settings */
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#define FDC1772CMDADD_SR12 (0x01)
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#define FDC1772CMDADD_SR2 (0x02)
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#define FDC1772CMDADD_SR3 (0x03)
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#define FDC1772CMDADD_V (0x04) /* verify */
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#define FDC1772CMDADD_H (0x08) /* wait for spin-up */
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#define FDC1772CMDADD_U (0x10) /* update track register */
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#define FDC1772CMDADD_M (0x10) /* multiple sector access */
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#define FDC1772CMDADD_E (0x04) /* head settling flag */
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#define FDC1772CMDADD_P (0x02) /* precompensation */
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#define FDC1772CMDADD_A0 (0x01) /* DAM flag */
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/* status register bits */
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#define FDC1772STAT_MOTORON (0x80) /* motor on */
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#define FDC1772STAT_WPROT (0x40) /* write protected (FDC1772CMD_WR*) */
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#define FDC1772STAT_SPINUP (0x20) /* motor speed stable (Type I) */
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#define FDC1772STAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */
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#define FDC1772STAT_RECNF (0x10) /* record not found */
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#define FDC1772STAT_CRC (0x08) /* CRC error */
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#define FDC1772STAT_TR00 (0x04) /* Track 00 flag (Type I) */
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#define FDC1772STAT_LOST (0x04) /* Lost Data (Type II+III) */
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#define FDC1772STAT_IDX (0x02) /* Index status (Type I) */
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#define FDC1772STAT_DRQ (0x02) /* DRQ status (Type II+III) */
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#define FDC1772STAT_BUSY (0x01) /* FDC1772 is busy */
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/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
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#define DSKSIDE (0x01)
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#define DSKDRVNONE (0x06)
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#define DSKDRV0 (0x02)
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#define DSKDRV1 (0x04)
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/* step rates */
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#define FDC1772STEP_6 0x00
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#define FDC1772STEP_12 0x01
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#define FDC1772STEP_2 0x02
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#define FDC1772STEP_3 0x03
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#endif
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