2008-10-23 05:26:29 +00:00
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#ifndef _ASM_X86_PGTABLE_32_H
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#define _ASM_X86_PGTABLE_32_H
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2005-04-16 22:20:36 +00:00
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2009-02-09 02:49:05 +00:00
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#include <asm/pgtable_32_types.h>
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2005-04-16 22:20:36 +00:00
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* the i386, we use that, but "fold" the mid level into the top-level page
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* table, so that we physically have the same two-level page table as the
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* i386 mmu expects.
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*
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* This file contains the functions and defines necessary to modify and use
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* the i386 page table tree.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <linux/threads.h>
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2006-12-07 01:14:08 +00:00
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#include <asm/paravirt.h>
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2005-04-16 22:20:36 +00:00
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2007-10-19 06:40:25 +00:00
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#include <linux/bitops.h>
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2005-04-16 22:20:36 +00:00
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#include <linux/list.h>
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#include <linux/spinlock.h>
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2005-11-07 08:59:43 +00:00
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struct mm_struct;
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struct vm_area_struct;
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2005-04-16 22:20:36 +00:00
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extern pgd_t swapper_pg_dir[1024];
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x86-32: Separate 1:1 pagetables from swapper_pg_dir
This patch fixes machine crashes which occur when heavily exercising the
CPU hotplug codepaths on a 32-bit kernel. These crashes are caused by
AMD Erratum 383 and result in a fatal machine check exception. Here's
the scenario:
1. On 32-bit, the swapper_pg_dir page table is used as the initial page
table for booting a secondary CPU.
2. To make this work, swapper_pg_dir needs a direct mapping of physical
memory in it (the low mappings). By adding those low, large page (2M)
mappings (PAE kernel), we create the necessary conditions for Erratum
383 to occur.
3. Other CPUs which do not participate in the off- and onlining game may
use swapper_pg_dir while the low mappings are present (when leave_mm is
called). For all steps below, the CPU referred to is a CPU that is using
swapper_pg_dir, and not the CPU which is being onlined.
4. The presence of the low mappings in swapper_pg_dir can result
in TLB entries for addresses below __PAGE_OFFSET to be established
speculatively. These TLB entries are marked global and large.
5. When the CPU with such TLB entry switches to another page table, this
TLB entry remains because it is global.
6. The process then generates an access to an address covered by the
above TLB entry but there is a permission mismatch - the TLB entry
covers a large global page not accessible to userspace.
7. Due to this permission mismatch a new 4kb, user TLB entry gets
established. Further, Erratum 383 provides for a small window of time
where both TLB entries are present. This results in an uncorrectable
machine check exception signalling a TLB multimatch which panics the
machine.
There are two ways to fix this issue:
1. Always do a global TLB flush when a new cr3 is loaded and the
old page table was swapper_pg_dir. I consider this a hack hard
to understand and with performance implications
2. Do not use swapper_pg_dir to boot secondary CPUs like 64-bit
does.
This patch implements solution 2. It introduces a trampoline_pg_dir
which has the same layout as swapper_pg_dir with low_mappings. This page
table is used as the initial page table of the booting CPU. Later in the
bringup process, it switches to swapper_pg_dir and does a global TLB
flush. This fixes the crashes in our test cases.
-v2: switch to swapper_pg_dir right after entering start_secondary() so
that we are able to access percpu data which might not be mapped in the
trampoline page table.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
LKML-Reference: <20100816123833.GB28147@aftab>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2010-08-16 12:38:33 +00:00
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extern pgd_t trampoline_pg_dir[1024];
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2005-04-16 22:20:36 +00:00
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2008-03-09 12:14:37 +00:00
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static inline void pgtable_cache_init(void) { }
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static inline void check_pgt_cache(void) { }
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2005-04-16 22:20:36 +00:00
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void paging_init(void);
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2008-07-23 12:11:59 +00:00
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extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t);
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2007-05-12 18:15:24 +00:00
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2008-08-20 23:43:03 +00:00
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2005-04-16 22:20:36 +00:00
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/*
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* Define this if things work differently on an i386 and an i486:
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* it will (on an i486) warn about kernel memory accesses that are
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2005-05-01 15:59:08 +00:00
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* done without a 'access_ok(VERIFY_WRITE,..)'
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2005-04-16 22:20:36 +00:00
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*/
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2005-05-01 15:59:08 +00:00
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#undef TEST_ACCESS_OK
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2005-04-16 22:20:36 +00:00
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#ifdef CONFIG_X86_PAE
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# include <asm/pgtable-3level.h>
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#else
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# include <asm/pgtable-2level.h>
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#endif
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#if defined(CONFIG_HIGHPTE)
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2009-06-15 14:46:05 +00:00
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#define __KM_PTE \
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(in_nmi() ? KM_NMI_PTE : \
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in_irq() ? KM_IRQ_PTE : \
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KM_PTE0)
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2008-03-23 08:03:09 +00:00
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#define pte_offset_map(dir, address) \
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2010-02-26 17:16:02 +00:00
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((pte_t *)kmap_atomic(pmd_page(*(dir)), __KM_PTE) + \
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2008-03-23 08:03:09 +00:00
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pte_index((address)))
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#define pte_offset_map_nested(dir, address) \
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2010-02-26 17:16:02 +00:00
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((pte_t *)kmap_atomic(pmd_page(*(dir)), KM_PTE1) + \
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2008-03-23 08:03:09 +00:00
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pte_index((address)))
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2009-06-15 10:40:41 +00:00
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#define pte_unmap(pte) kunmap_atomic((pte), __KM_PTE)
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2008-03-23 08:03:09 +00:00
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#define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1)
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2005-04-16 22:20:36 +00:00
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#else
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2008-03-23 08:03:09 +00:00
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
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#define pte_offset_map_nested(dir, address) pte_offset_map((dir), (address))
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2005-04-16 22:20:36 +00:00
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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#endif
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2006-10-01 06:29:35 +00:00
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/* Clear a kernel PTE and flush it from the TLB */
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2008-03-23 08:03:09 +00:00
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#define kpte_clear_flush(ptep, vaddr) \
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do { \
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pte_clear(&init_mm, (vaddr), (ptep)); \
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__flush_tlb_one((vaddr)); \
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2006-10-01 06:29:35 +00:00
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} while (0)
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2005-04-16 22:20:36 +00:00
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/*
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* The i386 doesn't have any external MMU info: the kernel page
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* tables contain all the necessary information.
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*/
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MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 16:40:18 +00:00
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#define update_mmu_cache(vma, address, ptep) do { } while (0)
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[PATCH] i386: PARAVIRT: Hooks to set up initial pagetable
This patch introduces paravirt_ops hooks to control how the kernel's
initial pagetable is set up.
In the case of a native boot, the very early bootstrap code creates a
simple non-PAE pagetable to map the kernel and physical memory. When
the VM subsystem is initialized, it creates a proper pagetable which
respects the PAE mode, large pages, etc.
When booting under a hypervisor, there are many possibilities for what
paging environment the hypervisor establishes for the guest kernel, so
the constructon of the kernel's pagetable depends on the hypervisor.
In the case of Xen, the hypervisor boots the kernel with a fully
constructed pagetable, which is already using PAE if necessary. Also,
Xen requires particular care when constructing pagetables to make sure
all pagetables are always mapped read-only.
In order to make this easier, kernel's initial pagetable construction
has been changed to only allocate and initialize a pagetable page if
there's no page already present in the pagetable. This allows the Xen
paravirt backend to make a copy of the hypervisor-provided pagetable,
allowing the kernel to establish any more mappings it needs while
keeping the existing ones.
A slightly subtle point which is worth highlighting here is that Xen
requires all kernel mappings to share the same pte_t pages between all
pagetables, so that updating a kernel page's mapping in one pagetable
is reflected in all other pagetables. This makes it possible to
allocate a page and attach it to a pagetable without having to
explicitly enumerate that page's mapping in all pagetables.
And:
+From: "Eric W. Biederman" <ebiederm@xmission.com>
If we don't set the leaf page table entries it is quite possible that
will inherit and incorrect page table entry from the initial boot
page table setup in head.S. So we need to redo the effort here,
so we pick up PSE, PGE and the like.
Hypervisors like Xen require that their page tables be read-only,
which is slightly incompatible with our low identity mappings, however
I discussed this with Jeremy he has modified the Xen early set_pte
function to avoid problems in this area.
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Acked-by: William Irwin <bill.irwin@oracle.com>
Cc: Ingo Molnar <mingo@elte.hu>
2007-05-02 17:27:13 +00:00
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2005-04-16 22:20:36 +00:00
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#endif /* !__ASSEMBLY__ */
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2008-01-30 12:30:37 +00:00
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/*
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* kern_addr_valid() is (1) for FLATMEM and (0) for
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* SPARSEMEM and DISCONTIGMEM
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*/
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2005-06-23 07:07:57 +00:00
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#ifdef CONFIG_FLATMEM
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2005-04-16 22:20:36 +00:00
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#define kern_addr_valid(addr) (1)
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2008-01-30 12:30:37 +00:00
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#else
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#define kern_addr_valid(kaddr) (0)
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#endif
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2005-04-16 22:20:36 +00:00
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2008-10-23 05:26:29 +00:00
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#endif /* _ASM_X86_PGTABLE_32_H */
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