280 lines
8.4 KiB
C
280 lines
8.4 KiB
C
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#include <linux/irq.h>
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/*
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* Global registers
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*/
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#define MPIC_GREG_BASE 0x01000
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#define MPIC_GREG_FEATURE_0 0x00000
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#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
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#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
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#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
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#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
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#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
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#define MPIC_GREG_FEATURE_1 0x00010
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#define MPIC_GREG_GLOBAL_CONF_0 0x00020
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#define MPIC_GREG_GCONF_RESET 0x80000000
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#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
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#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
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#define MPIC_GREG_GLOBAL_CONF_1 0x00030
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#define MPIC_GREG_VENDOR_0 0x00040
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#define MPIC_GREG_VENDOR_1 0x00050
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#define MPIC_GREG_VENDOR_2 0x00060
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#define MPIC_GREG_VENDOR_3 0x00070
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#define MPIC_GREG_VENDOR_ID 0x00080
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#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
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#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
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#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
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#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
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#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
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#define MPIC_GREG_PROCESSOR_INIT 0x00090
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#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
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#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
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#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
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#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
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#define MPIC_GREG_SPURIOUS 0x000e0
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#define MPIC_GREG_TIMER_FREQ 0x000f0
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/*
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*
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* Timer registers
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*/
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#define MPIC_TIMER_BASE 0x01100
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#define MPIC_TIMER_STRIDE 0x40
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#define MPIC_TIMER_CURRENT_CNT 0x00000
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#define MPIC_TIMER_BASE_CNT 0x00010
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#define MPIC_TIMER_VECTOR_PRI 0x00020
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#define MPIC_TIMER_DESTINATION 0x00030
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/*
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* Per-Processor registers
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*/
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#define MPIC_CPU_THISBASE 0x00000
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#define MPIC_CPU_BASE 0x20000
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#define MPIC_CPU_STRIDE 0x01000
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#define MPIC_CPU_IPI_DISPATCH_0 0x00040
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#define MPIC_CPU_IPI_DISPATCH_1 0x00050
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#define MPIC_CPU_IPI_DISPATCH_2 0x00060
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#define MPIC_CPU_IPI_DISPATCH_3 0x00070
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#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
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#define MPIC_CPU_TASKPRI_MASK 0x0000000f
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#define MPIC_CPU_WHOAMI 0x00090
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#define MPIC_CPU_WHOAMI_MASK 0x0000001f
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#define MPIC_CPU_INTACK 0x000a0
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#define MPIC_CPU_EOI 0x000b0
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/*
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* Per-source registers
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*/
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#define MPIC_IRQ_BASE 0x10000
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#define MPIC_IRQ_STRIDE 0x00020
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#define MPIC_IRQ_VECTOR_PRI 0x00000
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#define MPIC_VECPRI_MASK 0x80000000
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#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
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#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
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#define MPIC_VECPRI_PRIORITY_SHIFT 16
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#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
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#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
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#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
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#define MPIC_VECPRI_POLARITY_MASK 0x00800000
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#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
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#define MPIC_VECPRI_SENSE_EDGE 0x00000000
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#define MPIC_VECPRI_SENSE_MASK 0x00400000
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#define MPIC_IRQ_DESTINATION 0x00010
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#define MPIC_MAX_IRQ_SOURCES 2048
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#define MPIC_MAX_CPUS 32
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#define MPIC_MAX_ISU 32
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/*
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* Special vector numbers (internal use only)
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*/
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#define MPIC_VEC_SPURRIOUS 255
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#define MPIC_VEC_IPI_3 254
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#define MPIC_VEC_IPI_2 253
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#define MPIC_VEC_IPI_1 252
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#define MPIC_VEC_IPI_0 251
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/* unused */
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#define MPIC_VEC_TIMER_3 250
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#define MPIC_VEC_TIMER_2 249
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#define MPIC_VEC_TIMER_1 248
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#define MPIC_VEC_TIMER_0 247
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/* Type definition of the cascade handler */
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typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
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#ifdef CONFIG_MPIC_BROKEN_U3
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/* Fixup table entry */
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struct mpic_irq_fixup
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{
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u8 __iomem *base;
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unsigned int irq;
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};
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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/* The instance data of a given MPIC */
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struct mpic
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{
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/* The "linux" controller struct */
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hw_irq_controller hc_irq;
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#ifdef CONFIG_SMP
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hw_irq_controller hc_ipi;
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#endif
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const char *name;
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/* Flags */
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unsigned int flags;
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/* How many irq sources in a given ISU */
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unsigned int isu_size;
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unsigned int isu_shift;
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unsigned int isu_mask;
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/* Offset of irq vector numbers */
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unsigned int irq_offset;
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unsigned int irq_count;
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/* Offset of ipi vector numbers */
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unsigned int ipi_offset;
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/* Number of sources */
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unsigned int num_sources;
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/* Number of CPUs */
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unsigned int num_cpus;
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/* cascade handler */
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mpic_cascade_t cascade;
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void *cascade_data;
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unsigned int cascade_vec;
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/* senses array */
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unsigned char *senses;
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unsigned int senses_count;
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#ifdef CONFIG_MPIC_BROKEN_U3
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/* The fixup table */
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struct mpic_irq_fixup *fixups;
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spinlock_t fixup_lock;
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#endif
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/* The various ioremap'ed bases */
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volatile u32 __iomem *gregs;
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volatile u32 __iomem *tmregs;
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volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
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volatile u32 __iomem *isus[MPIC_MAX_ISU];
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/* link */
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struct mpic *next;
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};
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/* This is the primary controller, only that one has IPIs and
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* has afinity control. A non-primary MPIC always uses CPU0
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* registers only
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*/
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#define MPIC_PRIMARY 0x00000001
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/* Set this for a big-endian MPIC */
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#define MPIC_BIG_ENDIAN 0x00000002
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/* Broken U3 MPIC */
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#define MPIC_BROKEN_U3 0x00000004
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/* Broken IPI registers (autodetected) */
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#define MPIC_BROKEN_IPI 0x00000008
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/* MPIC wants a reset */
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#define MPIC_WANTS_RESET 0x00000010
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/* Allocate the controller structure and setup the linux irq descs
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* for the range if interrupts passed in. No HW initialization is
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* actually performed.
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*
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* @phys_addr: physial base address of the MPIC
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* @flags: flags, see constants above
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* @isu_size: number of interrupts in an ISU. Use 0 to use a
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* standard ISU-less setup (aka powermac)
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* @irq_offset: first irq number to assign to this mpic
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* @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
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* to match the number of sources
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* @ipi_offset: first irq number to assign to this mpic IPI sources,
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* used only on primary mpic
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* @senses: array of sense values
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* @senses_num: number of entries in the array
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*
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* Note about the sense array. If none is passed, all interrupts are
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* setup to be level negative unless MPIC_BROKEN_U3 is set in which
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* case they are edge positive (and the array is ignored anyway).
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* The values in the array start at the first source of the MPIC,
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* that is senses[0] correspond to linux irq "irq_offset".
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*/
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extern struct mpic *mpic_alloc(unsigned long phys_addr,
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unsigned int flags,
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unsigned int isu_size,
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unsigned int irq_offset,
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unsigned int irq_count,
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unsigned int ipi_offset,
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unsigned char *senses,
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unsigned int senses_num,
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const char *name);
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/* Assign ISUs, to call before mpic_init()
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*
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* @mpic: controller structure as returned by mpic_alloc()
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* @isu_num: ISU number
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* @phys_addr: physical address of the ISU
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*/
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extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
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unsigned long phys_addr);
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/* Initialize the controller. After this has been called, none of the above
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* should be called again for this mpic
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*/
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extern void mpic_init(struct mpic *mpic);
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/* Setup a cascade. Currently, only one cascade is supported this
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* way, though you can always do a normal request_irq() and add
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* other cascades this way. You should call this _after_ having
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* added all the ISUs
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*
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* @irq_no: "linux" irq number of the cascade (that is offset'ed vector)
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* @handler: cascade handler function
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*/
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extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
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void *data);
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/*
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* All of the following functions must only be used after the
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* ISUs have been assigned and the controller fully initialized
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* with mpic_init()
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*/
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/* Change/Read the priority of an interrupt. Default is 8 for irqs and
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* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
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* IPI number is then the offset'ed (linux irq number mapped to the IPI)
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*/
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extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
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extern unsigned int mpic_irq_get_priority(unsigned int irq);
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/* Setup a non-boot CPU */
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extern void mpic_setup_this_cpu(void);
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/* Clean up for kexec (or cpu offline or ...) */
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extern void mpic_teardown_this_cpu(int secondary);
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/* Get the current cpu priority for this cpu (0..15) */
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extern int mpic_cpu_get_priority(void);
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/* Set the current cpu priority for this cpu */
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extern void mpic_cpu_set_priority(int prio);
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/* Request IPIs on primary mpic */
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extern void mpic_request_ipis(void);
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/* Send an IPI (non offseted number 0..3) */
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extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
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/* Fetch interrupt from a given mpic */
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extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
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/* This one gets to the primary mpic */
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extern int mpic_get_irq(struct pt_regs *regs);
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/* global mpic for pSeries */
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extern struct mpic *pSeries_mpic;
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