497 lines
14 KiB
ArmAsm
497 lines
14 KiB
ArmAsm
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| bugfix.sa 3.2 1/31/91
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| This file contains workarounds for bugs in the 040
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| relating to the Floating-Point Software Package (FPSP)
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| Fixes for bugs: 1238
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| Bug: 1238
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| /* The following dirty_bit clear should be left in
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| * the handler permanently to improve throughput.
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| * The dirty_bits are located at bits [23:16] in
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| * longword $08 in the busy frame $4x60. Bit 16
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| * corresponds to FP0, bit 17 corresponds to FP1,
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| * and so on.
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| */
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| if (E3_exception_just_serviced) {
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| dirty_bit[cmdreg3b[9:7]] = 0;
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| }
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| if (fsave_format_version != $40) {goto NOFIX}
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| if !(E3_exception_just_serviced) {goto NOFIX}
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| if (cupc == 0000000) {goto NOFIX}
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| if ((cmdreg1b[15:13] != 000) &&
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| (cmdreg1b[15:10] != 010001)) {goto NOFIX}
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| if (((cmdreg1b[15:13] != 000) || ((cmdreg1b[12:10] != cmdreg2b[9:7]) &&
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| (cmdreg1b[12:10] != cmdreg3b[9:7])) ) &&
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| ((cmdreg1b[ 9: 7] != cmdreg2b[9:7]) &&
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| (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) ) {goto NOFIX}
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| /* Note: for 6d43b or 8d43b, you may want to add the following code
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| * to get better coverage. (If you do not insert this code, the part
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| * won't lock up; it will simply get the wrong answer.)
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| * Do NOT insert this code for 10d43b or later parts.
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| *
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| * if (fpiarcu == integer stack return address) {
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| * cupc = 0000000;
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| * goto NOFIX;
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| * }
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| */
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| if (cmdreg1b[15:13] != 000) {goto FIX_OPCLASS2}
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| FIX_OPCLASS0:
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| if (((cmdreg1b[12:10] == cmdreg2b[9:7]) ||
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| (cmdreg1b[ 9: 7] == cmdreg2b[9:7])) &&
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| (cmdreg1b[12:10] != cmdreg3b[9:7]) &&
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| (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) { /* xu conflict only */
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| /* We execute the following code if there is an
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| xu conflict and NOT an nu conflict */
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| /* first save some values on the fsave frame */
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| stag_temp = STAG[fsave_frame];
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| cmdreg1b_temp = CMDREG1B[fsave_frame];
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| dtag_temp = DTAG[fsave_frame];
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| ete15_temp = ETE15[fsave_frame];
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| CUPC[fsave_frame] = 0000000;
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| FRESTORE
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| FSAVE
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| /* If the xu instruction is exceptional, we punt.
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| * Otherwise, we would have to include OVFL/UNFL handler
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| * code here to get the correct answer.
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| */
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| if (fsave_frame_format == $4060) {goto KILL_PROCESS}
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| fsave_frame = /* build a long frame of all zeros */
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| fsave_frame_format = $4060; /* label it as long frame */
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| /* load it with the temps we saved */
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| STAG[fsave_frame] = stag_temp;
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| CMDREG1B[fsave_frame] = cmdreg1b_temp;
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| DTAG[fsave_frame] = dtag_temp;
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| ETE15[fsave_frame] = ete15_temp;
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| /* Make sure that the cmdreg3b dest reg is not going to
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| * be destroyed by a FMOVEM at the end of all this code.
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| * If it is, you should move the current value of the reg
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| * onto the stack so that the reg will loaded with that value.
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| */
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| /* All done. Proceed with the code below */
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| }
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| etemp = FP_reg_[cmdreg1b[12:10]];
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| ete15 = ~ete14;
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| cmdreg1b[15:10] = 010010;
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| clear(bug_flag_procIDxxxx);
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| FRESTORE and return;
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| FIX_OPCLASS2:
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| if ((cmdreg1b[9:7] == cmdreg2b[9:7]) &&
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| (cmdreg1b[9:7] != cmdreg3b[9:7])) { /* xu conflict only */
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| /* We execute the following code if there is an
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| xu conflict and NOT an nu conflict */
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| /* first save some values on the fsave frame */
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| stag_temp = STAG[fsave_frame];
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| cmdreg1b_temp = CMDREG1B[fsave_frame];
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| dtag_temp = DTAG[fsave_frame];
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| ete15_temp = ETE15[fsave_frame];
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| etemp_temp = ETEMP[fsave_frame];
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| CUPC[fsave_frame] = 0000000;
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| FRESTORE
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| FSAVE
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| /* If the xu instruction is exceptional, we punt.
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| * Otherwise, we would have to include OVFL/UNFL handler
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| * code here to get the correct answer.
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| */
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| if (fsave_frame_format == $4060) {goto KILL_PROCESS}
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| fsave_frame = /* build a long frame of all zeros */
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| fsave_frame_format = $4060; /* label it as long frame */
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| /* load it with the temps we saved */
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| STAG[fsave_frame] = stag_temp;
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| CMDREG1B[fsave_frame] = cmdreg1b_temp;
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| DTAG[fsave_frame] = dtag_temp;
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| ETE15[fsave_frame] = ete15_temp;
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| ETEMP[fsave_frame] = etemp_temp;
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| /* Make sure that the cmdreg3b dest reg is not going to
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| * be destroyed by a FMOVEM at the end of all this code.
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| * If it is, you should move the current value of the reg
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| * onto the stack so that the reg will loaded with that value.
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| */
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| /* All done. Proceed with the code below */
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| }
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| if (etemp_exponent == min_sgl) etemp_exponent = min_dbl;
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| if (etemp_exponent == max_sgl) etemp_exponent = max_dbl;
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| cmdreg1b[15:10] = 010101;
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| clear(bug_flag_procIDxxxx);
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| FRESTORE and return;
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| NOFIX:
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| clear(bug_flag_procIDxxxx);
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| FRESTORE and return;
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| Copyright (C) Motorola, Inc. 1990
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| All Rights Reserved
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| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
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| The copyright notice above does not evidence any
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| actual or intended publication of such source code.
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|BUGFIX idnt 2,1 | Motorola 040 Floating Point Software Package
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|section 8
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#include "fpsp.h"
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|xref fpsp_fmt_error
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.global b1238_fix
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b1238_fix:
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| This code is entered only on completion of the handling of an
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| nu-generated ovfl, unfl, or inex exception. If the version
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| number of the fsave is not $40, this handler is not necessary.
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| Simply branch to fix_done and exit normally.
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cmpib #VER_40,4(%a7)
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bne fix_done
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| Test for cu_savepc equal to zero. If not, this is not a bug
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| #1238 case.
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moveb CU_SAVEPC(%a6),%d0
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andib #0xFE,%d0
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beq fix_done |if zero, this is not bug #1238
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| Test the register conflict aspect. If opclass0, check for
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| cu src equal to xu dest or equal to nu dest. If so, go to
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| op0. Else, or if opclass2, check for cu dest equal to
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| xu dest or equal to nu dest. If so, go to tst_opcl. Else,
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| exit, it is not the bug case.
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| Check for opclass 0. If not, go and check for opclass 2 and sgl.
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movew CMDREG1B(%a6),%d0
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andiw #0xE000,%d0 |strip all but opclass
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bne op2sgl |not opclass 0, check op2
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| Check for cu and nu register conflict. If one exists, this takes
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| priority over a cu and xu conflict.
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bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
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bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
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cmpb %d0,%d1
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beqs op0 |if equal, continue bugfix
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| Check for cu dest equal to nu dest. If so, go and fix the
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| bug condition. Otherwise, exit.
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bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
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cmpb %d0,%d1 |cmp 1st dest with 3rd dest
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beqs op0 |if equal, continue bugfix
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| Check for cu and xu register conflict.
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bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
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cmpb %d0,%d1 |cmp 1st dest with 2nd dest
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beqs op0_xu |if equal, continue bugfix
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bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
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cmpb %d0,%d1 |cmp 1st src with 2nd dest
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beq op0_xu
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bne fix_done |if the reg checks fail, exit
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| We have the opclass 0 situation.
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op0:
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bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no
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movel #7,%d1
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subl %d0,%d1
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clrl %d0
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bsetl %d1,%d0
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fmovemx %d0,ETEMP(%a6) |load source to ETEMP
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moveb #0x12,%d0
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bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
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| Set ETEMP exponent bit 15 as the opposite of ete14
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btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14
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beq setete15
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bclr #etemp15_bit,STAG(%a6)
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bra finish
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setete15:
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bset #etemp15_bit,STAG(%a6)
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bra finish
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| We have the case in which a conflict exists between the cu src or
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| dest and the dest of the xu. We must clear the instruction in
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| the cu and restore the state, allowing the instruction in the
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| xu to complete. Remember, the instruction in the nu
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| was exceptional, and was completed by the appropriate handler.
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| If the result of the xu instruction is not exceptional, we can
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| restore the instruction from the cu to the frame and continue
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| processing the original exception. If the result is also
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| exceptional, we choose to kill the process.
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| Items saved from the stack:
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| $3c stag - L_SCR1
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| $40 cmdreg1b - L_SCR2
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| $44 dtag - L_SCR3
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| The cu savepc is set to zero, and the frame is restored to the
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| fpu.
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op0_xu:
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movel STAG(%a6),L_SCR1(%a6)
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movel CMDREG1B(%a6),L_SCR2(%a6)
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movel DTAG(%a6),L_SCR3(%a6)
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andil #0xe0000000,L_SCR3(%a6)
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moveb #0,CU_SAVEPC(%a6)
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movel (%a7)+,%d1 |save return address from bsr
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frestore (%a7)+
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fsave -(%a7)
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| Check if the instruction which just completed was exceptional.
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cmpw #0x4060,(%a7)
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beq op0_xb
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| It is necessary to isolate the result of the instruction in the
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| xu if it is to fp0 - fp3 and write that value to the USER_FPn
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| locations on the stack. The correct destination register is in
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| cmdreg2b.
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bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
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cmpil #3,%d0
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bgts op0_xi
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beqs op0_fp3
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cmpil #1,%d0
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blts op0_fp0
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beqs op0_fp1
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op0_fp2:
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fmovemx %fp2-%fp2,USER_FP2(%a6)
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bras op0_xi
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op0_fp1:
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fmovemx %fp1-%fp1,USER_FP1(%a6)
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bras op0_xi
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op0_fp0:
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fmovemx %fp0-%fp0,USER_FP0(%a6)
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bras op0_xi
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op0_fp3:
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fmovemx %fp3-%fp3,USER_FP3(%a6)
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| The frame returned is idle. We must build a busy frame to hold
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| the cu state information and setup etemp.
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op0_xi:
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movel #22,%d0 |clear 23 lwords
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clrl (%a7)
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op0_loop:
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clrl -(%a7)
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dbf %d0,op0_loop
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movel #0x40600000,-(%a7)
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movel L_SCR1(%a6),STAG(%a6)
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movel L_SCR2(%a6),CMDREG1B(%a6)
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movel L_SCR3(%a6),DTAG(%a6)
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moveb #0x6,CU_SAVEPC(%a6)
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movel %d1,-(%a7) |return bsr return address
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bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no
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movel #7,%d1
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subl %d0,%d1
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clrl %d0
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bsetl %d1,%d0
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fmovemx %d0,ETEMP(%a6) |load source to ETEMP
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moveb #0x12,%d0
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bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
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| Set ETEMP exponent bit 15 as the opposite of ete14
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btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14
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beq op0_sete15
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bclr #etemp15_bit,STAG(%a6)
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bra finish
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op0_sete15:
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bset #etemp15_bit,STAG(%a6)
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bra finish
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|
|
|
|
||
|
|
| The frame returned is busy. It is not possible to reconstruct
|
||
|
|
| the code sequence to allow completion. We will jump to
|
||
|
|
| fpsp_fmt_error and allow the kernel to kill the process.
|
||
|
|
|
|
||
|
|
op0_xb:
|
||
|
|
jmp fpsp_fmt_error
|
||
|
|
|
||
|
|
|
|
||
|
|
| Check for opclass 2 and single size. If not both, exit.
|
||
|
|
|
|
||
|
|
op2sgl:
|
||
|
|
movew CMDREG1B(%a6),%d0
|
||
|
|
andiw #0xFC00,%d0 |strip all but opclass and size
|
||
|
|
cmpiw #0x4400,%d0 |test for opclass 2 and size=sgl
|
||
|
|
bne fix_done |if not, it is not bug 1238
|
||
|
|
|
|
||
|
|
| Check for cu dest equal to nu dest or equal to xu dest, with
|
||
|
|
| a cu and nu conflict taking priority an nu conflict. If either,
|
||
|
|
| go and fix the bug condition. Otherwise, exit.
|
||
|
|
|
|
||
|
|
bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
|
||
|
|
bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
|
||
|
|
cmpb %d0,%d1 |cmp 1st dest with 3rd dest
|
||
|
|
beq op2_com |if equal, continue bugfix
|
||
|
|
bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
|
||
|
|
cmpb %d0,%d1 |cmp 1st dest with 2nd dest
|
||
|
|
bne fix_done |if the reg checks fail, exit
|
||
|
|
|
|
||
|
|
| We have the case in which a conflict exists between the cu src or
|
||
|
|
| dest and the dest of the xu. We must clear the instruction in
|
||
|
|
| the cu and restore the state, allowing the instruction in the
|
||
|
|
| xu to complete. Remember, the instruction in the nu
|
||
|
|
| was exceptional, and was completed by the appropriate handler.
|
||
|
|
| If the result of the xu instruction is not exceptional, we can
|
||
|
|
| restore the instruction from the cu to the frame and continue
|
||
|
|
| processing the original exception. If the result is also
|
||
|
|
| exceptional, we choose to kill the process.
|
||
|
|
|
|
||
|
|
| Items saved from the stack:
|
||
|
|
|
|
||
|
|
| $3c stag - L_SCR1
|
||
|
|
| $40 cmdreg1b - L_SCR2
|
||
|
|
| $44 dtag - L_SCR3
|
||
|
|
| etemp - FP_SCR2
|
||
|
|
|
|
||
|
|
| The cu savepc is set to zero, and the frame is restored to the
|
||
|
|
| fpu.
|
||
|
|
|
|
||
|
|
op2_xu:
|
||
|
|
movel STAG(%a6),L_SCR1(%a6)
|
||
|
|
movel CMDREG1B(%a6),L_SCR2(%a6)
|
||
|
|
movel DTAG(%a6),L_SCR3(%a6)
|
||
|
|
andil #0xe0000000,L_SCR3(%a6)
|
||
|
|
moveb #0,CU_SAVEPC(%a6)
|
||
|
|
movel ETEMP(%a6),FP_SCR2(%a6)
|
||
|
|
movel ETEMP_HI(%a6),FP_SCR2+4(%a6)
|
||
|
|
movel ETEMP_LO(%a6),FP_SCR2+8(%a6)
|
||
|
|
movel (%a7)+,%d1 |save return address from bsr
|
||
|
|
frestore (%a7)+
|
||
|
|
fsave -(%a7)
|
||
|
|
|
|
||
|
|
| Check if the instruction which just completed was exceptional.
|
||
|
|
|
|
||
|
|
cmpw #0x4060,(%a7)
|
||
|
|
beq op2_xb
|
||
|
|
|
|
||
|
|
| It is necessary to isolate the result of the instruction in the
|
||
|
|
| xu if it is to fp0 - fp3 and write that value to the USER_FPn
|
||
|
|
| locations on the stack. The correct destination register is in
|
||
|
|
| cmdreg2b.
|
||
|
|
|
|
||
|
|
bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
|
||
|
|
cmpil #3,%d0
|
||
|
|
bgts op2_xi
|
||
|
|
beqs op2_fp3
|
||
|
|
cmpil #1,%d0
|
||
|
|
blts op2_fp0
|
||
|
|
beqs op2_fp1
|
||
|
|
op2_fp2:
|
||
|
|
fmovemx %fp2-%fp2,USER_FP2(%a6)
|
||
|
|
bras op2_xi
|
||
|
|
op2_fp1:
|
||
|
|
fmovemx %fp1-%fp1,USER_FP1(%a6)
|
||
|
|
bras op2_xi
|
||
|
|
op2_fp0:
|
||
|
|
fmovemx %fp0-%fp0,USER_FP0(%a6)
|
||
|
|
bras op2_xi
|
||
|
|
op2_fp3:
|
||
|
|
fmovemx %fp3-%fp3,USER_FP3(%a6)
|
||
|
|
|
|
||
|
|
| The frame returned is idle. We must build a busy frame to hold
|
||
|
|
| the cu state information and fix up etemp.
|
||
|
|
|
|
||
|
|
op2_xi:
|
||
|
|
movel #22,%d0 |clear 23 lwords
|
||
|
|
clrl (%a7)
|
||
|
|
op2_loop:
|
||
|
|
clrl -(%a7)
|
||
|
|
dbf %d0,op2_loop
|
||
|
|
movel #0x40600000,-(%a7)
|
||
|
|
movel L_SCR1(%a6),STAG(%a6)
|
||
|
|
movel L_SCR2(%a6),CMDREG1B(%a6)
|
||
|
|
movel L_SCR3(%a6),DTAG(%a6)
|
||
|
|
moveb #0x6,CU_SAVEPC(%a6)
|
||
|
|
movel FP_SCR2(%a6),ETEMP(%a6)
|
||
|
|
movel FP_SCR2+4(%a6),ETEMP_HI(%a6)
|
||
|
|
movel FP_SCR2+8(%a6),ETEMP_LO(%a6)
|
||
|
|
movel %d1,-(%a7)
|
||
|
|
bra op2_com
|
||
|
|
|
||
|
|
|
|
||
|
|
| We have the opclass 2 single source situation.
|
||
|
|
|
|
||
|
|
op2_com:
|
||
|
|
moveb #0x15,%d0
|
||
|
|
bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, double
|
||
|
|
|
||
|
|
cmpw #0x407F,ETEMP_EX(%a6) |single +max
|
||
|
|
bnes case2
|
||
|
|
movew #0x43FF,ETEMP_EX(%a6) |to double +max
|
||
|
|
bra finish
|
||
|
|
case2:
|
||
|
|
cmpw #0xC07F,ETEMP_EX(%a6) |single -max
|
||
|
|
bnes case3
|
||
|
|
movew #0xC3FF,ETEMP_EX(%a6) |to double -max
|
||
|
|
bra finish
|
||
|
|
case3:
|
||
|
|
cmpw #0x3F80,ETEMP_EX(%a6) |single +min
|
||
|
|
bnes case4
|
||
|
|
movew #0x3C00,ETEMP_EX(%a6) |to double +min
|
||
|
|
bra finish
|
||
|
|
case4:
|
||
|
|
cmpw #0xBF80,ETEMP_EX(%a6) |single -min
|
||
|
|
bne fix_done
|
||
|
|
movew #0xBC00,ETEMP_EX(%a6) |to double -min
|
||
|
|
bra finish
|
||
|
|
|
|
||
|
|
| The frame returned is busy. It is not possible to reconstruct
|
||
|
|
| the code sequence to allow completion. fpsp_fmt_error causes
|
||
|
|
| an fline illegal instruction to be executed.
|
||
|
|
|
|
||
|
|
| You should replace the jump to fpsp_fmt_error with a jump
|
||
|
|
| to the entry point used to kill a process.
|
||
|
|
|
|
||
|
|
op2_xb:
|
||
|
|
jmp fpsp_fmt_error
|
||
|
|
|
||
|
|
|
|
||
|
|
| Enter here if the case is not of the situations affected by
|
||
|
|
| bug #1238, or if the fix is completed, and exit.
|
||
|
|
|
|
||
|
|
finish:
|
||
|
|
fix_done:
|
||
|
|
rts
|
||
|
|
|
||
|
|
|end
|