348 lines
10 KiB
C
348 lines
10 KiB
C
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/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright <EFBFBD> 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et131x_adapter.h - Header which includes the private adapter structure, along
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* with related support structures, macros, definitions, etc.
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright <EFBFBD> 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED <EFBFBD>AS IS<EFBFBD> AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#ifndef __ET131X_ADAPTER_H__
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#define __ET131X_ADAPTER_H__
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#include "et1310_address_map.h"
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#include "et1310_tx.h"
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#include "et1310_rx.h"
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/*
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* Do not change these values: if changed, then change also in respective
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* TXdma and Rxdma engines
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*/
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#define NUM_DESC_PER_RING_TX 512 // TX Do not change these values
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#define NUM_TCB 64
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/*
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* These values are all superseded by registry entries to facilitate tuning.
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* Once the desired performance has been achieved, the optimal registry values
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* should be re-populated to these #defines:
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*/
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#define NUM_TRAFFIC_CLASSES 1
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/*
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* There are three ways of counting errors - if there are more than X errors
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* in Y packets (represented by the "SAMPLE" macros), if there are more than
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* N errors in a S mSec time period (the "PERIOD" macros), or if there are
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* consecutive packets with errors (CONSEC_ERRORED_THRESH). This last covers
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* for "Bursty" errors, and the errored packets may well not be contiguous,
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* but several errors where the packet counter has changed by less than a
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* small amount will cause this count to increment.
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*/
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#define TX_PACKETS_IN_SAMPLE 10000
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#define TX_MAX_ERRORS_IN_SAMPLE 50
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#define TX_ERROR_PERIOD 1000
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#define TX_MAX_ERRORS_IN_PERIOD 10
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#define LINK_DETECTION_TIMER 5000
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#define TX_CONSEC_RANGE 5
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#define TX_CONSEC_ERRORED_THRESH 10
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#define LO_MARK_PERCENT_FOR_PSR 15
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#define LO_MARK_PERCENT_FOR_RX 15
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/* Macros for flag and ref count operations */
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#define MP_SET_FLAG(_M, _F) ((_M)->Flags |= (_F))
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#define MP_CLEAR_FLAG(_M, _F) ((_M)->Flags &= ~(_F))
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#define MP_CLEAR_FLAGS(_M) ((_M)->Flags = 0)
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#define MP_TEST_FLAG(_M, _F) (((_M)->Flags & (_F)) != 0)
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#define MP_TEST_FLAGS(_M, _F) (((_M)->Flags & (_F)) == (_F))
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#define MP_IS_FLAG_CLEAR(_M, _F) (((_M)->Flags & (_F)) == 0)
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#define MP_INC_RCV_REF(_A) atomic_inc(&(_A)->RcvRefCount)
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#define MP_DEC_RCV_REF(_A) atomic_dec(&(_A)->RcvRefCount)
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#define MP_GET_RCV_REF(_A) atomic_read(&(_A)->RcvRefCount)
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/* Macros specific to the private adapter structure */
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#define MP_TCB_RESOURCES_AVAILABLE(_M) ((_M)->TxRing.nBusySend < NUM_TCB)
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#define MP_TCB_RESOURCES_NOT_AVAILABLE(_M) ((_M)->TxRing.nBusySend >= NUM_TCB)
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#define MP_SHOULD_FAIL_SEND(_M) ((_M)->Flags & fMP_ADAPTER_FAIL_SEND_MASK)
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#define MP_IS_NOT_READY(_M) ((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
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#define MP_IS_READY(_M) !((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
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#define MP_HAS_CABLE(_M) !((_M)->Flags & fMP_ADAPTER_NO_CABLE)
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#define MP_LINK_DETECTED(_M) !((_M)->Flags & fMP_ADAPTER_LINK_DETECTION)
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/* Counters for error rate monitoring */
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typedef struct _MP_ERR_COUNTERS {
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u32 PktCountTxPackets;
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u32 PktCountTxErrors;
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u32 TimerBasedTxErrors;
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u32 PktCountLastError;
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u32 ErredConsecPackets;
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} MP_ERR_COUNTERS, *PMP_ERR_COUNTERS;
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/* RFD (Receive Frame Descriptor) */
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typedef struct _MP_RFD {
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struct list_head list_node;
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struct sk_buff *Packet;
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u32 PacketSize; // total size of receive frame
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u16 iBufferIndex;
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u8 iRingIndex;
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} MP_RFD, *PMP_RFD;
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/* Enum for Flow Control */
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typedef enum _eflow_control_t {
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Both = 0,
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TxOnly = 1,
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RxOnly = 2,
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None = 3
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} eFLOW_CONTROL_t, *PeFLOW_CONTROL_t;
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/* Struct to define some device statistics */
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typedef struct _ce_stats_t {
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/* Link Input/Output stats */
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uint64_t ipackets; // # of in packets
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uint64_t opackets; // # of out packets
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/* MIB II variables
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*
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* NOTE: atomic_t types are only guaranteed to store 24-bits; if we
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* MUST have 32, then we'll need another way to perform atomic
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* operations
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*/
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u32 unircv; // # multicast packets received
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atomic_t unixmt; // # multicast packets for Tx
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u32 multircv; // # multicast packets received
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atomic_t multixmt; // # multicast packets for Tx
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u32 brdcstrcv; // # broadcast packets received
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atomic_t brdcstxmt; // # broadcast packets for Tx
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u32 norcvbuf; // # Rx packets discarded
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u32 noxmtbuf; // # Tx packets discarded
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/* Transciever state informations. */
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u8 xcvr_addr;
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u32 xcvr_id;
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/* Tx Statistics. */
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u32 tx_uflo; // Tx Underruns
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u32 collisions;
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u32 excessive_collisions;
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u32 first_collision;
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u32 late_collisions;
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u32 max_pkt_error;
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u32 tx_deferred;
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/* Rx Statistics. */
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u32 rx_ov_flow; // Rx Over Flow
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u32 length_err;
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u32 alignment_err;
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u32 crc_err;
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u32 code_violations;
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u32 other_errors;
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#ifdef CONFIG_ET131X_DEBUG
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u32 UnhandledInterruptsPerSec;
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u32 RxDmaInterruptsPerSec;
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u32 TxDmaInterruptsPerSec;
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u32 WatchDogInterruptsPerSec;
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#endif /* CONFIG_ET131X_DEBUG */
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u32 SynchrounousIterations;
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INTERRUPT_t InterruptStatus;
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} CE_STATS_t, *PCE_STATS_t;
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/* The private adapter structure */
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struct et131x_adapter {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct work_struct task;
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/* Flags that indicate current state of the adapter */
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u32 Flags;
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u32 HwErrCount;
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/* Configuration */
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u8 PermanentAddress[ETH_ALEN];
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u8 CurrentAddress[ETH_ALEN];
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bool bOverrideAddress;
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bool bEepromPresent;
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u8 eepromData[2];
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/* Spinlocks */
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spinlock_t Lock;
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spinlock_t TCBSendQLock;
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spinlock_t TCBReadyQLock;
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spinlock_t SendHWLock;
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spinlock_t SendWaitLock;
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spinlock_t RcvLock;
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spinlock_t RcvPendLock;
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spinlock_t FbrLock;
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spinlock_t PHYLock;
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/* Packet Filter and look ahead size */
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u32 PacketFilter;
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u32 ulLookAhead;
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u32 uiLinkSpeed;
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u32 uiDuplexMode;
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u32 uiAutoNegStatus;
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u8 ucLinkStatus;
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/* multicast list */
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u32 MCAddressCount;
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u8 MCList[NIC_MAX_MCAST_LIST][ETH_ALEN];
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/* MAC test */
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TXMAC_TXTEST_t TxMacTest;
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/* Pointer to the device's PCI register space */
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ADDRESS_MAP_t __iomem *CSRAddress;
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/* PCI config space info, for debug purposes only. */
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u8 RevisionID;
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u16 VendorID;
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u16 DeviceID;
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u16 SubVendorID;
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u16 SubSystemID;
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u32 CacheFillSize;
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u16 PciXDevCtl;
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u8 pci_lat_timer;
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u8 pci_hdr_type;
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u8 pci_bist;
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u32 pci_cfg_state[64 / sizeof(u32)];
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/* Registry parameters */
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u8 SpeedDuplex; // speed/duplex
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eFLOW_CONTROL_t RegistryFlowControl; // for 802.3x flow control
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u8 RegistryWOLMatch; // Enable WOL pattern-matching
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u8 RegistryWOLLink; // Link state change is independant
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u8 RegistryPhyComa; // Phy Coma mode enable/disable
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u32 RegistryRxMemEnd; // Size of internal rx memory
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u8 RegistryMACStat; // If set, read MACSTAT, else don't
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u32 RegistryVlanTag; // 802.1q Vlan TAG
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u32 RegistryJumboPacket; // Max supported ethernet packet size
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u32 RegistryTxNumBuffers;
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u32 RegistryTxTimeInterval;
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u32 RegistryRxNumBuffers;
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u32 RegistryRxTimeInterval;
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/* Validation helpers */
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u8 RegistryPMWOL;
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u8 RegistryNMIDisable;
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u32 RegistryDMACache;
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u32 RegistrySCGain;
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u8 RegistryPhyLoopbk; // Enable Phy loopback
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/* Derived from the registry: */
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u8 AiForceDpx; // duplex setting
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u16 AiForceSpeed; // 'Speed', user over-ride of line speed
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eFLOW_CONTROL_t FlowControl; // flow control validated by the far-end
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enum {
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NETIF_STATUS_INVALID = 0,
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NETIF_STATUS_MEDIA_CONNECT,
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NETIF_STATUS_MEDIA_DISCONNECT,
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NETIF_STATUS_MAX
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} MediaState;
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u8 DriverNoPhyAccess;
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/* Minimize init-time */
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bool bQueryPending;
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bool bSetPending;
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bool bResetPending;
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struct timer_list ErrorTimer;
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bool bLinkTimerActive;
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MP_POWER_MGMT PoMgmt;
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INTERRUPT_t CachedMaskValue;
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atomic_t RcvRefCount; // Num packets not yet returned
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/* Xcvr status at last poll */
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MI_BMSR_t Bmsr;
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/* Tx Memory Variables */
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TX_RING_t TxRing;
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/* Rx Memory Variables */
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RX_RING_t RxRing;
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/* ET1310 register Access */
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JAGCORE_ACCESS_REGS JagCoreRegs;
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PCI_CFG_SPACE_REGS PciCfgRegs;
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/* Loopback specifics */
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u8 ReplicaPhyLoopbk; // Replica Enable
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u8 ReplicaPhyLoopbkPF; // Replica Enable Pass/Fail
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/* Stats */
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CE_STATS_t Stats;
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struct net_device_stats net_stats;
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struct net_device_stats net_stats_prev;
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};
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#define MPSendPacketsHandler MPSendPackets
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#define MP_FREE_SEND_PACKET_FUN(Adapter, pMpTcb) \
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et131x_free_send_packet(Adapter, pMpTcb)
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#define MpSendPacketFun(Adapter, Packet) MpSendPacket(Adapter, Packet)
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#endif /* __ET131X_ADAPTER_H__ */
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