468 lines
14 KiB
C
468 lines
14 KiB
C
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/*
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* arch/ppc/platform/85xx/mpc85xx_cds_common.c
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*
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* MPC85xx CDS board specific routines
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/serial.h>
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#include <linux/module.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/tty.h>
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#include <linux/serial_core.h>
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#include <linux/fsl_devices.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/todc.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/open_pic.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_cpm2.h>
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#include <asm/ppc_sys.h>
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#include <asm/kgdb.h>
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#include <mm/mmu_decl.h>
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#include <syslib/cpm2_pic.h>
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#include <syslib/ppc85xx_common.h>
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#include <syslib/ppc85xx_setup.h>
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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#endif
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extern unsigned long total_memory; /* in mm/init */
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unsigned char __res[sizeof (bd_t)];
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static int cds_pci_slot = 2;
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static volatile u8 * cadmus;
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/* Internal interrupts are all Level Sensitive, and Positive Polarity */
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static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
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#if defined(CONFIG_PCI)
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
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#else
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0x0, /* External 0: */
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0x0, /* External 1: */
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0x0, /* External 2: */
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0x0, /* External 3: */
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#endif
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0x0, /* External 4: */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
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0x0, /* External 6: */
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0x0, /* External 7: */
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0x0, /* External 8: */
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0x0, /* External 9: */
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0x0, /* External 10: */
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#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
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#else
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0x0, /* External 11: */
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#endif
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};
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/* ************************************************************************ */
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int
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mpc85xx_cds_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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uint memsize = total_memory;
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bd_t *binfo = (bd_t *) __res;
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unsigned int freq;
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/* get the core frequency */
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freq = binfo->bi_intfreq;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
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seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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/* Display the amount of memory */
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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return 0;
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}
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#ifdef CONFIG_CPM2
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static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
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{
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while((irq = cpm2_get_irq(regs)) >= 0)
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__do_IRQ(irq, regs);
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}
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static struct irqaction cpm2_irqaction = {
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.handler = cpm2_cascade,
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.flags = SA_INTERRUPT,
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.mask = CPU_MASK_NONE,
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.name = "cpm2_cascade",
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};
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#endif /* CONFIG_CPM2 */
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void __init
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mpc85xx_cds_init_IRQ(void)
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{
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bd_t *binfo = (bd_t *) __res;
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/* Determine the Physical Address of the OpenPIC regs */
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phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
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OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
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OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
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/* Skip reserved space and internal sources */
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openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
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/* Map PIC IRQs 0-11 */
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openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
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/* we let openpic interrupts starting from an offset, to
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* leave space for cascading interrupts underneath.
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*/
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openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
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#ifdef CONFIG_CPM2
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/* Setup CPM2 PIC */
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cpm2_init_IRQ();
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setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
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#endif
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return;
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}
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#ifdef CONFIG_PCI
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/*
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* interrupt routing
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*/
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int
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mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
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if (!hose->index)
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{
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/* Handle PCI1 interrupts */
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char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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/* Note IRQ assignment for slots is based on which slot the elysium is
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* in -- in this setup elysium is in slot #2 (this PIRQA as first
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* interrupt on slot */
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{
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{ 0, 1, 2, 3 }, /* 16 - PMC */
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{ 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
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{ 0, 1, 2, 3 }, /* 18 - Slot 1 */
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{ 1, 2, 3, 0 }, /* 19 - Slot 2 */
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{ 2, 3, 0, 1 }, /* 20 - Slot 3 */
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{ 3, 0, 1, 2 }, /* 21 - Slot 4 */
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};
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const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
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int i, j;
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for (i = 0; i < 6; i++)
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for (j = 0; j < 4; j++)
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pci_irq_table[i][j] =
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((pci_irq_table[i][j] + 5 -
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cds_pci_slot) & 0x3) + PIRQ0A;
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return PCI_IRQ_TABLE_LOOKUP;
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} else {
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/* Handle PCI2 interrupts (if we have one) */
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char pci_irq_table[][4] =
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{
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/*
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* We only have one slot and one interrupt
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* going to PIRQA - PIRQD */
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{ PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
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};
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const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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}
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#define ARCADIA_HOST_BRIDGE_IDSEL 17
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#define ARCADIA_2ND_BRIDGE_IDSEL 3
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extern int mpc85xx_pci1_last_busno;
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int
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mpc85xx_exclude_device(u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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#ifdef CONFIG_85xx_PCI2
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if (mpc85xx_pci1_last_busno)
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if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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#endif
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/* We explicitly do not go past the Tundra 320 Bridge */
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if (bus == 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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#endif /* CONFIG_PCI */
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TODC_ALLOC();
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void __init
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mpc85xx_cds_setup_arch(void)
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{
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bd_t *binfo = (bd_t *) __res;
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unsigned int freq;
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struct gianfar_platform_data *pdata;
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/* get the core frequency */
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freq = binfo->bi_intfreq;
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printk("mpc85xx_cds_setup_arch\n");
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#ifdef CONFIG_CPM2
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cpm2_reset();
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#endif
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cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
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cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
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printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
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/* Setup TODC access */
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TODC_INIT(TODC_TYPE_DS1743,
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0,
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0,
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ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
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8);
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/* Set loops_per_jiffy to a half-way reasonable value,
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for use until calibrate_delay gets called. */
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loops_per_jiffy = freq / HZ;
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#ifdef CONFIG_PCI
|
||
|
|
/* setup PCI host bridges */
|
||
|
|
mpc85xx_setup_hose();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_SERIAL_8250
|
||
|
|
mpc85xx_early_serial_map();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_SERIAL_TEXT_DEBUG
|
||
|
|
/* Invalidate the entry we stole earlier the serial ports
|
||
|
|
* should be properly mapped */
|
||
|
|
invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* setup the board related information for the enet controllers */
|
||
|
|
pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
|
||
|
|
pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
|
||
|
|
pdata->interruptPHY = MPC85xx_IRQ_EXT5;
|
||
|
|
pdata->phyid = 0;
|
||
|
|
/* fixup phy address */
|
||
|
|
pdata->phy_reg_addr += binfo->bi_immr_base;
|
||
|
|
memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
|
||
|
|
|
||
|
|
pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
|
||
|
|
pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
|
||
|
|
pdata->interruptPHY = MPC85xx_IRQ_EXT5;
|
||
|
|
pdata->phyid = 1;
|
||
|
|
/* fixup phy address */
|
||
|
|
pdata->phy_reg_addr += binfo->bi_immr_base;
|
||
|
|
memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
||
|
|
if (initrd_start)
|
||
|
|
ROOT_DEV = Root_RAM0;
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_ROOT_NFS
|
||
|
|
ROOT_DEV = Root_NFS;
|
||
|
|
#else
|
||
|
|
ROOT_DEV = Root_HDA1;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ************************************************************************ */
|
||
|
|
void __init
|
||
|
|
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||
|
|
unsigned long r6, unsigned long r7)
|
||
|
|
{
|
||
|
|
/* parse_bootinfo must always be called first */
|
||
|
|
parse_bootinfo(find_bootinfo());
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If we were passed in a board information, copy it into the
|
||
|
|
* residual data area.
|
||
|
|
*/
|
||
|
|
if (r3) {
|
||
|
|
memcpy((void *) __res, (void *) (r3 + KERNELBASE),
|
||
|
|
sizeof (bd_t));
|
||
|
|
|
||
|
|
}
|
||
|
|
#ifdef CONFIG_SERIAL_TEXT_DEBUG
|
||
|
|
{
|
||
|
|
bd_t *binfo = (bd_t *) __res;
|
||
|
|
struct uart_port p;
|
||
|
|
|
||
|
|
/* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
|
||
|
|
settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
|
||
|
|
binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
|
||
|
|
|
||
|
|
memset(&p, 0, sizeof (p));
|
||
|
|
p.iotype = SERIAL_IO_MEM;
|
||
|
|
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
|
||
|
|
p.uartclk = binfo->bi_busfreq;
|
||
|
|
|
||
|
|
gen550_init(0, &p);
|
||
|
|
|
||
|
|
memset(&p, 0, sizeof (p));
|
||
|
|
p.iotype = SERIAL_IO_MEM;
|
||
|
|
p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
|
||
|
|
p.uartclk = binfo->bi_busfreq;
|
||
|
|
|
||
|
|
gen550_init(1, &p);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_BLK_DEV_INITRD)
|
||
|
|
/*
|
||
|
|
* If the init RAM disk has been configured in, and there's a valid
|
||
|
|
* starting address for it, set it up.
|
||
|
|
*/
|
||
|
|
if (r4) {
|
||
|
|
initrd_start = r4 + KERNELBASE;
|
||
|
|
initrd_end = r5 + KERNELBASE;
|
||
|
|
}
|
||
|
|
#endif /* CONFIG_BLK_DEV_INITRD */
|
||
|
|
|
||
|
|
/* Copy the kernel command line arguments to a safe place. */
|
||
|
|
|
||
|
|
if (r6) {
|
||
|
|
*(char *) (r7 + KERNELBASE) = 0;
|
||
|
|
strcpy(cmd_line, (char *) (r6 + KERNELBASE));
|
||
|
|
}
|
||
|
|
|
||
|
|
identify_ppc_sys_by_id(mfspr(SPRN_SVR));
|
||
|
|
|
||
|
|
/* setup the PowerPC module struct */
|
||
|
|
ppc_md.setup_arch = mpc85xx_cds_setup_arch;
|
||
|
|
ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
|
||
|
|
|
||
|
|
ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
|
||
|
|
ppc_md.get_irq = openpic_get_irq;
|
||
|
|
|
||
|
|
ppc_md.restart = mpc85xx_restart;
|
||
|
|
ppc_md.power_off = mpc85xx_power_off;
|
||
|
|
ppc_md.halt = mpc85xx_halt;
|
||
|
|
|
||
|
|
ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
|
||
|
|
|
||
|
|
ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
|
||
|
|
|
||
|
|
ppc_md.time_init = todc_time_init;
|
||
|
|
ppc_md.set_rtc_time = todc_set_rtc_time;
|
||
|
|
ppc_md.get_rtc_time = todc_get_rtc_time;
|
||
|
|
|
||
|
|
ppc_md.nvram_read_val = todc_direct_read_val;
|
||
|
|
ppc_md.nvram_write_val = todc_direct_write_val;
|
||
|
|
|
||
|
|
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
|
||
|
|
ppc_md.progress = gen550_progress;
|
||
|
|
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
|
||
|
|
|
||
|
|
if (ppc_md.progress)
|
||
|
|
ppc_md.progress("mpc85xx_cds_init(): exit", 0);
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|