279 lines
8.1 KiB
C
279 lines
8.1 KiB
C
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/*
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* arch/ppc/platforms/4xx/sycamore.c
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*
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* Architecture- / platform-specific boot-time initialization code for
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* IBM PowerPC 4xx based boards.
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*
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* Author: Armin Kuster <akuster@mvista.com>
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*
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* 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/rtc.h>
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#include <asm/ocp.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/system.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/ibm_ocp_pci.h>
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#include <asm/todc.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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void *kb_cs;
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void *kb_data;
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void *sycamore_rtc_base;
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/*
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* Define external IRQ senses and polarities.
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*/
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unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 10 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 11 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 12 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
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};
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/* Some IRQs unique to Sycamore.
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* Used by the generic 405 PCI setup functions in ppc4xx_pci.c
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*/
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int __init
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ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
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{29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
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{30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
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{31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
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};
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const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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};
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void __init
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sycamore_setup_arch(void)
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{
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#define SYCAMORE_PS2_BASE 0xF0100000
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#define SYCAMORE_FPGA_BASE 0xF0300000
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void *fpga_brdc;
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unsigned char fpga_brdc_data;
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void *fpga_enable;
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void *fpga_polarity;
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void *fpga_status;
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void *fpga_trigger;
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ppc4xx_setup_arch();
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ibm_ocp_set_emac(0, 1);
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kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
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if (!kb_data) {
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printk(KERN_CRIT
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"sycamore_setup_arch() kb_data ioremap failed\n");
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return;
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}
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kb_cs = kb_data + 1;
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fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8);
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if (!fpga_status) {
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printk(KERN_CRIT
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"sycamore_setup_arch() fpga_status ioremap failed\n");
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return;
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}
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fpga_enable = fpga_status + 1;
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fpga_polarity = fpga_status + 2;
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fpga_trigger = fpga_status + 3;
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fpga_brdc = fpga_status + 4;
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/* split the keyboard and mouse interrupts */
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fpga_brdc_data = readb(fpga_brdc);
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fpga_brdc_data |= 0x80;
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writeb(fpga_brdc_data, fpga_brdc);
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writeb(0x3, fpga_enable);
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writeb(0x3, fpga_polarity);
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writeb(0x3, fpga_trigger);
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/* RTC step for the sycamore */
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sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
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TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
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sycamore_rtc_base, 8);
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/* Identify the system */
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printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
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printk(KERN_INFO
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"Port by MontaVista Software, Inc. (source@mvista.com)\n");
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}
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void __init
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bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
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{
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#ifdef CONFIG_PCI
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unsigned int bar_response, bar;
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/*
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* Expected PCI mapping:
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*
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* PLB addr PCI memory addr
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* --------------------- ---------------------
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* 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
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* 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
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*
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* PLB addr PCI io addr
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* --------------------- ---------------------
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* e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
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*
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* The following code is simplified by assuming that the bootrom
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* has been well behaved in following this mapping.
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*/
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#ifdef DEBUG
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int i;
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printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
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printk("PCI bridge regs before fixup \n");
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for (i = 0; i <= 3; i++) {
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
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}
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printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
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printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
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printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
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printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
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#endif
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/* added for IBM boot rom version 1.15 bios bar changes -AK */
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/* Disable region first */
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out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
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/* PLB starting addr, PCI: 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
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/* PCI start addr, 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
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/* 512MB range of PLB to PCI */
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out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
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/* Enable no pre-fetch, enable region */
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out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
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(PPC405_PCI_UPPER_MEM -
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PPC405_PCI_MEM_BASE)) | 0x01));
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/* Enable inbound region one - 1GB size */
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out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
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/* Disable outbound region one */
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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/* Disable inbound region two */
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out_le32((void *) &(pcip->ptm2ms), 0x00000000);
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/* Disable outbound region two */
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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/* Zero config bars */
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for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
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early_write_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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0x00000000);
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early_read_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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&bar_response);
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DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
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hose->first_busno, PCI_SLOT(hose->first_busno),
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PCI_FUNC(hose->first_busno), bar, bar_response);
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}
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/* end work arround */
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#ifdef DEBUG
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printk("PCI bridge regs after fixup \n");
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for (i = 0; i <= 3; i++) {
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
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}
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printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
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printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
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printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
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printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
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#endif
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#endif
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}
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void __init
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sycamore_map_io(void)
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{
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ppc4xx_map_io();
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io_block_mapping(SYCAMORE_RTC_VADDR,
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SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
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}
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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ppc4xx_init(r3, r4, r5, r6, r7);
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ppc_md.setup_arch = sycamore_setup_arch;
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ppc_md.setup_io_mappings = sycamore_map_io;
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#ifdef CONFIG_GEN_RTC
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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#endif
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}
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