2008-08-21 21:04:55 +00:00
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/**************************************************************************
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*
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* Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of Alacritech, Inc.
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*
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**************************************************************************/
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/*
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* FILENAME: sxg.c
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*
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* The SXG driver for Alacritech's 10Gbe products.
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*
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* NOTE: This is the standard, non-accelerated version of Alacritech's
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* IS-NIC driver.
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/skbuff.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/dma-mapping.h>
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#include <linux/mii.h>
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#define SLIC_DUMP_ENABLED 0
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#define SLIC_GET_STATS_ENABLED 0
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#define LINUX_FREES_ADAPTER_RESOURCES 1
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#define SXG_OFFLOAD_IP_CHECKSUM 0
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#define SXG_POWER_MANAGEMENT_ENABLED 0
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#define VPCI 0
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#define DBG 1
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#define ATK_DEBUG 1
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#include "sxg_os.h"
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#include "sxghw.h"
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#include "sxghif.h"
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#include "sxg.h"
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#include "sxgdbg.h"
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#include "sxgphycode.h"
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#include "saharadbgdownload.h"
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2008-10-28 22:42:02 +00:00
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static int sxg_allocate_buffer_memory(struct adapter_t *adapter, u32 Size,
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enum SXG_BUFFER_TYPE BufferType);
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static void sxg_allocate_rcvblock_complete(struct adapter_t *adapter, void *RcvBlock,
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2008-10-06 00:38:52 +00:00
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dma_addr_t PhysicalAddress,
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u32 Length);
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2008-10-28 22:42:02 +00:00
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static void sxg_allocate_sgl_buffer_complete(struct adapter_t *adapter,
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struct SXG_SCATTER_GATHER *SxgSgl,
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2008-10-06 00:38:52 +00:00
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dma_addr_t PhysicalAddress,
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u32 Length);
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2008-08-21 21:04:55 +00:00
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static void sxg_mcast_init_crc32(void);
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static int sxg_entry_open(p_net_device dev);
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static int sxg_entry_halt(p_net_device dev);
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static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd);
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static int sxg_send_packets(struct sk_buff *skb, p_net_device dev);
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2008-10-28 22:42:02 +00:00
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static int sxg_transmit_packet(struct adapter_t *adapter, struct sk_buff *skb);
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2009-01-05 15:43:23 +00:00
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static void sxg_dumb_sgl(struct SXG_X64_SGL *pSgl, struct SXG_SCATTER_GATHER *SxgSgl);
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2008-10-28 22:42:02 +00:00
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static void sxg_handle_interrupt(struct adapter_t *adapter);
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static int sxg_process_isr(struct adapter_t *adapter, u32 MessageId);
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static u32 sxg_process_event_queue(struct adapter_t *adapter, u32 RssId);
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static void sxg_complete_slow_send(struct adapter_t *adapter);
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static struct sk_buff *sxg_slow_receive(struct adapter_t *adapter, struct SXG_EVENT *Event);
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static void sxg_process_rcv_error(struct adapter_t *adapter, u32 ErrorStatus);
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static bool sxg_mac_filter(struct adapter_t *adapter,
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struct ether_header *EtherHdr, ushort length);
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2008-08-21 21:04:55 +00:00
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#if SLIC_GET_STATS_ENABLED
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static struct net_device_stats *sxg_get_stats(p_net_device dev);
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#endif
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2008-10-21 17:41:45 +00:00
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#define XXXTODO 0
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2008-10-06 00:38:52 +00:00
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static int sxg_mac_set_address(p_net_device dev, void *ptr);
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2008-10-21 17:41:45 +00:00
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static void sxg_mcast_set_list(p_net_device dev);
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2008-08-21 21:04:55 +00:00
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2008-10-28 22:42:02 +00:00
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static void sxg_adapter_set_hwaddr(struct adapter_t *adapter);
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2008-08-21 21:04:55 +00:00
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2008-10-28 22:42:02 +00:00
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static void sxg_unmap_mmio_space(struct adapter_t *adapter);
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2008-08-21 21:04:55 +00:00
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2008-10-28 22:42:02 +00:00
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static int sxg_initialize_adapter(struct adapter_t *adapter);
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static void sxg_stock_rcv_buffers(struct adapter_t *adapter);
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static void sxg_complete_descriptor_blocks(struct adapter_t *adapter,
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2008-10-06 00:38:52 +00:00
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unsigned char Index);
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2008-10-28 22:42:02 +00:00
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static int sxg_initialize_link(struct adapter_t *adapter);
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static int sxg_phy_init(struct adapter_t *adapter);
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static void sxg_link_event(struct adapter_t *adapter);
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static enum SXG_LINK_STATE sxg_get_link_state(struct adapter_t *adapter);
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static void sxg_link_state(struct adapter_t *adapter, enum SXG_LINK_STATE LinkState);
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static int sxg_write_mdio_reg(struct adapter_t *adapter,
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2008-10-06 00:38:52 +00:00
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u32 DevAddr, u32 RegAddr, u32 Value);
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2008-10-28 22:42:02 +00:00
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static int sxg_read_mdio_reg(struct adapter_t *adapter,
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2008-10-06 00:38:52 +00:00
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u32 DevAddr, u32 RegAddr, u32 *pValue);
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2008-08-21 21:04:55 +00:00
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static unsigned int sxg_first_init = 1;
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static char *sxg_banner =
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"Alacritech SLIC Technology(tm) Server and Storage 10Gbe Accelerator (Non-Accelerated)\n";
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static int sxg_debug = 1;
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static int debug = -1;
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static p_net_device head_netdevice = NULL;
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2008-10-28 22:42:02 +00:00
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static struct sxgbase_driver_t sxg_global = {
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2008-08-21 21:04:55 +00:00
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.dynamic_intagg = 1,
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};
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static int intagg_delay = 100;
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static u32 dynamic_intagg = 0;
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#define DRV_NAME "sxg"
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#define DRV_VERSION "1.0.1"
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#define DRV_AUTHOR "Alacritech, Inc. Engineering"
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#define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) Non-Accelerated 10Gbe Driver"
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#define DRV_COPYRIGHT "Copyright 2000-2008 Alacritech, Inc. All rights reserved."
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MODULE_AUTHOR(DRV_AUTHOR);
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MODULE_DESCRIPTION(DRV_DESCRIPTION);
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MODULE_LICENSE("GPL");
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module_param(dynamic_intagg, int, 0);
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MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting");
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module_param(intagg_delay, int, 0);
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MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay");
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static struct pci_device_id sxg_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(SXG_VENDOR_ID, SXG_DEVICE_ID)},
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{0,}
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};
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2008-10-06 00:38:52 +00:00
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2008-08-21 21:04:55 +00:00
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MODULE_DEVICE_TABLE(pci, sxg_pci_tbl);
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/***********************************************************************
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************************************************************************
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************************************************************************
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************************************************************************
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************************************************************************/
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static inline void sxg_reg32_write(void __iomem *reg, u32 value, bool flush)
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{
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writel(value, reg);
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if (flush)
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mb();
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}
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2008-10-28 22:42:02 +00:00
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static inline void sxg_reg64_write(struct adapter_t *adapter, void __iomem *reg,
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2008-08-21 21:04:55 +00:00
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u64 value, u32 cpu)
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{
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u32 value_high = (u32) (value >> 32);
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u32 value_low = (u32) (value & 0x00000000FFFFFFFF);
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unsigned long flags;
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spin_lock_irqsave(&adapter->Bit64RegLock, flags);
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writel(value_high, (void __iomem *)(&adapter->UcodeRegs[cpu].Upper));
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writel(value_low, reg);
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spin_unlock_irqrestore(&adapter->Bit64RegLock, flags);
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}
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static void sxg_init_driver(void)
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{
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if (sxg_first_init) {
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DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n",
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2008-10-17 21:46:10 +00:00
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__func__, jiffies);
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2008-08-21 21:04:55 +00:00
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sxg_first_init = 0;
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spin_lock_init(&sxg_global.driver_lock);
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}
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}
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2008-10-28 22:42:02 +00:00
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static void sxg_dbg_macaddrs(struct adapter_t *adapter)
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2008-08-21 21:04:55 +00:00
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{
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DBG_ERROR(" (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
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adapter->netdev->name, adapter->currmacaddr[0],
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adapter->currmacaddr[1], adapter->currmacaddr[2],
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adapter->currmacaddr[3], adapter->currmacaddr[4],
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adapter->currmacaddr[5]);
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DBG_ERROR(" (%s) mac %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
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adapter->netdev->name, adapter->macaddr[0],
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adapter->macaddr[1], adapter->macaddr[2],
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adapter->macaddr[3], adapter->macaddr[4],
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adapter->macaddr[5]);
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return;
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}
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2008-10-20 23:28:58 +00:00
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/* SXG Globals */
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2008-10-28 22:42:02 +00:00
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static struct SXG_DRIVER SxgDriver;
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2008-08-21 21:04:55 +00:00
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#ifdef ATKDBG
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2008-10-28 22:42:02 +00:00
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static struct sxg_trace_buffer_t LSxgTraceBuffer;
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2008-08-21 21:04:55 +00:00
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#endif /* ATKDBG */
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2008-10-28 22:42:02 +00:00
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static struct sxg_trace_buffer_t *SxgTraceBuffer = NULL;
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2008-08-21 21:04:55 +00:00
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/*
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* sxg_download_microcode
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*
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* Download Microcode to Sahara adapter
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*
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* Arguments -
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* adapter - A pointer to our adapter structure
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* UcodeSel - microcode file selection
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*
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* Return
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* int
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*/
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2008-10-28 22:42:02 +00:00
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static bool sxg_download_microcode(struct adapter_t *adapter, enum SXG_UCODE_SEL UcodeSel)
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2008-08-21 21:04:55 +00:00
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{
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2008-10-28 22:42:02 +00:00
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struct SXG_HW_REGS *HwRegs = adapter->HwRegs;
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2008-08-21 21:04:55 +00:00
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u32 Section;
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u32 ThisSectionSize;
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2008-10-06 00:38:52 +00:00
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u32 *Instruction = NULL;
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2008-08-21 21:04:55 +00:00
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u32 BaseAddress, AddressOffset, Address;
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2008-10-20 23:28:58 +00:00
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/* u32 Failure; */
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2008-08-21 21:04:55 +00:00
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u32 ValueRead;
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u32 i;
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u32 numSections = 0;
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u32 sectionSize[16];
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u32 sectionStart[16];
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DnldUcod",
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adapter, 0, 0, 0);
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2008-10-17 21:46:10 +00:00
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DBG_ERROR("sxg: %s ENTER\n", __func__);
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2008-08-21 21:04:55 +00:00
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switch (UcodeSel) {
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2008-10-20 23:28:58 +00:00
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case SXG_UCODE_SAHARA: /* Sahara operational ucode */
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2008-08-21 21:04:55 +00:00
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numSections = SNumSections;
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for (i = 0; i < numSections; i++) {
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sectionSize[i] = SSectionSize[i];
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sectionStart[i] = SSectionStart[i];
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}
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break;
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default:
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printk(KERN_ERR KBUILD_MODNAME
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": Woah, big error with the microcode!\n");
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break;
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}
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DBG_ERROR("sxg: RESET THE CARD\n");
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2008-10-20 23:28:58 +00:00
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/* First, reset the card */
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2008-08-21 21:04:55 +00:00
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WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
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2008-10-20 23:28:58 +00:00
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/* Download each section of the microcode as specified in */
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/* its download file. The *download.c file is generated using */
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/* the saharaobjtoc facility which converts the metastep .obj */
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/* file to a .c file which contains a two dimentional array. */
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2008-08-21 21:04:55 +00:00
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for (Section = 0; Section < numSections; Section++) {
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DBG_ERROR("sxg: SECTION # %d\n", Section);
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switch (UcodeSel) {
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case SXG_UCODE_SAHARA:
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Instruction = (u32 *) & SaharaUCode[Section][0];
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break;
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default:
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ASSERT(0);
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break;
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}
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BaseAddress = sectionStart[Section];
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2008-10-20 23:28:58 +00:00
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ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */
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2008-08-21 21:04:55 +00:00
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for (AddressOffset = 0; AddressOffset < ThisSectionSize;
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AddressOffset++) {
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Address = BaseAddress + AddressOffset;
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ASSERT((Address & ~MICROCODE_ADDRESS_MASK) == 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write instruction bits 31 - 0 */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->UcodeDataLow, *Instruction, FLUSH);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write instruction bits 63-32 */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->UcodeDataMiddle, *(Instruction + 1),
|
|
|
|
FLUSH);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write instruction bits 95-64 */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->UcodeDataHigh, *(Instruction + 2),
|
|
|
|
FLUSH);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write instruction address with the WRITE bit set */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->UcodeAddr,
|
|
|
|
(Address | MICROCODE_ADDRESS_WRITE), FLUSH);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Sahara bug in the ucode download logic - the write to DataLow */
|
|
|
|
/* for the next instruction could get corrupted. To avoid this, */
|
|
|
|
/* write to DataLow again for this instruction (which may get */
|
|
|
|
/* corrupted, but it doesn't matter), then increment the address */
|
|
|
|
/* and write the data for the next instruction to DataLow. That */
|
|
|
|
/* write should succeed. */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->UcodeDataLow, *Instruction, TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Advance 3 u32S to start of next instruction */
|
2008-08-21 21:04:55 +00:00
|
|
|
Instruction += 3;
|
|
|
|
}
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now repeat the entire operation reading the instruction back and */
|
|
|
|
/* checking for parity errors */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (Section = 0; Section < numSections; Section++) {
|
|
|
|
DBG_ERROR("sxg: check SECTION # %d\n", Section);
|
|
|
|
switch (UcodeSel) {
|
|
|
|
case SXG_UCODE_SAHARA:
|
|
|
|
Instruction = (u32 *) & SaharaUCode[Section][0];
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ASSERT(0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
BaseAddress = sectionStart[Section];
|
2008-10-20 23:28:58 +00:00
|
|
|
ThisSectionSize = sectionSize[Section] / 12; /* Size in instructions */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (AddressOffset = 0; AddressOffset < ThisSectionSize;
|
|
|
|
AddressOffset++) {
|
|
|
|
Address = BaseAddress + AddressOffset;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write the address with the READ bit set */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->UcodeAddr,
|
|
|
|
(Address | MICROCODE_ADDRESS_READ), FLUSH);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Read it back and check parity bit. */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->UcodeAddr, ValueRead);
|
|
|
|
if (ValueRead & MICROCODE_ADDRESS_PARITY) {
|
|
|
|
DBG_ERROR("sxg: %s PARITY ERROR\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
return (FALSE); /* Parity error */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
ASSERT((ValueRead & MICROCODE_ADDRESS_MASK) == Address);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Read the instruction back and compare */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->UcodeDataLow, ValueRead);
|
|
|
|
if (ValueRead != *Instruction) {
|
|
|
|
DBG_ERROR("sxg: %s MISCOMPARE LOW\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-10-20 23:28:58 +00:00
|
|
|
return (FALSE); /* Miscompare */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
READ_REG(HwRegs->UcodeDataMiddle, ValueRead);
|
|
|
|
if (ValueRead != *(Instruction + 1)) {
|
|
|
|
DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-10-20 23:28:58 +00:00
|
|
|
return (FALSE); /* Miscompare */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
READ_REG(HwRegs->UcodeDataHigh, ValueRead);
|
|
|
|
if (ValueRead != *(Instruction + 2)) {
|
|
|
|
DBG_ERROR("sxg: %s MISCOMPARE HIGH\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-10-20 23:28:58 +00:00
|
|
|
return (FALSE); /* Miscompare */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Advance 3 u32S to start of next instruction */
|
2008-08-21 21:04:55 +00:00
|
|
|
Instruction += 3;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Everything OK, Go. */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->UcodeAddr, MICROCODE_ADDRESS_GO, FLUSH);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Poll the CardUp register to wait for microcode to initialize */
|
|
|
|
/* Give up after 10,000 attemps (500ms). */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (i = 0; i < 10000; i++) {
|
|
|
|
udelay(50);
|
|
|
|
READ_REG(adapter->UcodeRegs[0].CardUp, ValueRead);
|
|
|
|
if (ValueRead == 0xCAFE) {
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s BOO YA 0xCAFE\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (i == 10000) {
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s TIMEOUT\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
return (FALSE); /* Timeout */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now write the LoadSync register. This is used to */
|
|
|
|
/* synchronize with the card so it can scribble on the memory */
|
|
|
|
/* that contained 0xCAFE from the "CardUp" step above */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (UcodeSel == SXG_UCODE_SAHARA) {
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH);
|
|
|
|
}
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDnldUcd",
|
|
|
|
adapter, 0, 0, 0);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
return (TRUE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_allocate_resources - Allocate memory and locks
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* int
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_allocate_resources(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
int status;
|
|
|
|
u32 i;
|
|
|
|
u32 RssIds, IsrCount;
|
2008-10-28 22:42:02 +00:00
|
|
|
/* struct SXG_XMT_RING *XmtRing; */
|
|
|
|
/* struct SXG_RCV_RING *RcvRing; */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s ENTER\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocRes",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Windows tells us how many CPUs it plans to use for */
|
|
|
|
/* RSS */
|
2008-08-21 21:04:55 +00:00
|
|
|
RssIds = SXG_RSS_CPU_COUNT(adapter);
|
|
|
|
IsrCount = adapter->MsiEnabled ? RssIds : 1;
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s Setup the spinlocks\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Allocate spinlocks and initialize listheads first. */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock_init(&adapter->RcvQLock);
|
|
|
|
spin_lock_init(&adapter->SglQLock);
|
|
|
|
spin_lock_init(&adapter->XmtZeroLock);
|
|
|
|
spin_lock_init(&adapter->Bit64RegLock);
|
|
|
|
spin_lock_init(&adapter->AdapterLock);
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s Setup the lists\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
InitializeListHead(&adapter->FreeRcvBuffers);
|
|
|
|
InitializeListHead(&adapter->FreeRcvBlocks);
|
|
|
|
InitializeListHead(&adapter->AllRcvBlocks);
|
|
|
|
InitializeListHead(&adapter->FreeSglBuffers);
|
|
|
|
InitializeListHead(&adapter->AllSglBuffers);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Mark these basic allocations done. This flags essentially */
|
|
|
|
/* tells the SxgFreeResources routine that it can grab spinlocks */
|
|
|
|
/* and reference listheads. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->BasicAllocations = TRUE;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Main allocation loop. Start with the maximum supported by */
|
|
|
|
/* the microcode and back off if memory allocation */
|
|
|
|
/* fails. If we hit a minimum, fail. */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
for (;;) {
|
2008-10-21 17:41:45 +00:00
|
|
|
DBG_ERROR("%s Allocate XmtRings size[%x]\n", __func__,
|
2008-10-28 22:42:02 +00:00
|
|
|
(unsigned int)(sizeof(struct SXG_XMT_RING) * 1));
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Start with big items first - receive and transmit rings. At the moment */
|
|
|
|
/* I'm going to keep the ring size fixed and adjust the number of */
|
|
|
|
/* TCBs if we fail. Later we might consider reducing the ring size as well.. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->XmtRings = pci_alloc_consistent(adapter->pcidev,
|
2008-10-28 22:42:02 +00:00
|
|
|
sizeof(struct SXG_XMT_RING) *
|
2008-08-21 21:04:55 +00:00
|
|
|
1,
|
|
|
|
&adapter->PXmtRings);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s XmtRings[%p]\n", __func__, adapter->XmtRings);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
if (!adapter->XmtRings) {
|
|
|
|
goto per_tcb_allocation_failed;
|
|
|
|
}
|
2008-10-28 22:42:02 +00:00
|
|
|
memset(adapter->XmtRings, 0, sizeof(struct SXG_XMT_RING) * 1);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-21 17:41:45 +00:00
|
|
|
DBG_ERROR("%s Allocate RcvRings size[%x]\n", __func__,
|
2008-10-28 22:42:02 +00:00
|
|
|
(unsigned int)(sizeof(struct SXG_RCV_RING) * 1));
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->RcvRings =
|
|
|
|
pci_alloc_consistent(adapter->pcidev,
|
2008-10-28 22:42:02 +00:00
|
|
|
sizeof(struct SXG_RCV_RING) * 1,
|
2008-08-21 21:04:55 +00:00
|
|
|
&adapter->PRcvRings);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s RcvRings[%p]\n", __func__, adapter->RcvRings);
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!adapter->RcvRings) {
|
|
|
|
goto per_tcb_allocation_failed;
|
|
|
|
}
|
2008-10-28 22:42:02 +00:00
|
|
|
memset(adapter->RcvRings, 0, sizeof(struct SXG_RCV_RING) * 1);
|
2008-08-21 21:04:55 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
per_tcb_allocation_failed:
|
2008-10-20 23:28:58 +00:00
|
|
|
/* an allocation failed. Free any successful allocations. */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->XmtRings) {
|
|
|
|
pci_free_consistent(adapter->pcidev,
|
2008-10-28 22:42:02 +00:00
|
|
|
sizeof(struct SXG_XMT_RING) * 4096,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->XmtRings,
|
|
|
|
adapter->PXmtRings);
|
|
|
|
adapter->XmtRings = NULL;
|
|
|
|
}
|
|
|
|
if (adapter->RcvRings) {
|
|
|
|
pci_free_consistent(adapter->pcidev,
|
2008-10-28 22:42:02 +00:00
|
|
|
sizeof(struct SXG_RCV_RING) * 4096,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->RcvRings,
|
|
|
|
adapter->PRcvRings);
|
|
|
|
adapter->RcvRings = NULL;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Loop around and try again.... */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __func__);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize rcv zero and xmt zero rings */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_INITIALIZE_RING(adapter->RcvRingZeroInfo, SXG_RCV_RING_SIZE);
|
|
|
|
SXG_INITIALIZE_RING(adapter->XmtRingZeroInfo, SXG_XMT_RING_SIZE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Sanity check receive data structure format */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
|
|
|
|
(adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
|
2008-10-28 22:42:02 +00:00
|
|
|
ASSERT(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK) ==
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RCV_DESCRIPTOR_BLOCK_SIZE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Allocate receive data buffers. We allocate a block of buffers and */
|
|
|
|
/* a corresponding descriptor block at once. See sxghw.h:SXG_RCV_BLOCK */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (i = 0; i < SXG_INITIAL_RCV_DATA_BUFFERS;
|
|
|
|
i += SXG_RCV_DESCRIPTORS_PER_BLOCK) {
|
|
|
|
sxg_allocate_buffer_memory(adapter,
|
|
|
|
SXG_RCV_BLOCK_SIZE(adapter->
|
|
|
|
ReceiveBufferSize),
|
|
|
|
SXG_BUFFER_TYPE_RCV);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* NBL resource allocation can fail in the 'AllocateComplete' routine, which */
|
|
|
|
/* doesn't return status. Make sure we got the number of buffers we requested */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->FreeRcvBufferCount < SXG_INITIAL_RCV_DATA_BUFFERS) {
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF6",
|
|
|
|
adapter, adapter->FreeRcvBufferCount, SXG_MAX_ENTRIES,
|
|
|
|
0);
|
|
|
|
return (STATUS_RESOURCES);
|
|
|
|
}
|
|
|
|
|
2008-10-21 17:41:45 +00:00
|
|
|
DBG_ERROR("%s Allocate EventRings size[%x]\n", __func__,
|
2008-10-28 22:42:02 +00:00
|
|
|
(unsigned int)(sizeof(struct SXG_EVENT_RING) * RssIds));
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Allocate event queues. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->EventRings = pci_alloc_consistent(adapter->pcidev,
|
2008-10-28 22:42:02 +00:00
|
|
|
sizeof(struct SXG_EVENT_RING) *
|
2008-08-21 21:04:55 +00:00
|
|
|
RssIds,
|
|
|
|
&adapter->PEventRings);
|
|
|
|
|
|
|
|
if (!adapter->EventRings) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Caller will call SxgFreeAdapter to clean up above allocations */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF8",
|
|
|
|
adapter, SXG_MAX_ENTRIES, 0, 0);
|
|
|
|
status = STATUS_RESOURCES;
|
|
|
|
goto per_tcb_allocation_failed;
|
|
|
|
}
|
2008-10-28 22:42:02 +00:00
|
|
|
memset(adapter->EventRings, 0, sizeof(struct SXG_EVENT_RING) * RssIds);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s Allocate ISR size[%x]\n", __func__, IsrCount);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Allocate ISR */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Isr = pci_alloc_consistent(adapter->pcidev,
|
|
|
|
IsrCount, &adapter->PIsr);
|
|
|
|
if (!adapter->Isr) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Caller will call SxgFreeAdapter to clean up above allocations */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF9",
|
|
|
|
adapter, SXG_MAX_ENTRIES, 0, 0);
|
|
|
|
status = STATUS_RESOURCES;
|
|
|
|
goto per_tcb_allocation_failed;
|
|
|
|
}
|
|
|
|
memset(adapter->Isr, 0, sizeof(u32) * IsrCount);
|
|
|
|
|
2008-10-21 17:41:45 +00:00
|
|
|
DBG_ERROR("%s Allocate shared XMT ring zero index location size[%x]\n",
|
|
|
|
__func__, (unsigned int)sizeof(u32));
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Allocate shared XMT ring zero index location */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->XmtRingZeroIndex = pci_alloc_consistent(adapter->pcidev,
|
|
|
|
sizeof(u32),
|
|
|
|
&adapter->
|
|
|
|
PXmtRingZeroIndex);
|
|
|
|
if (!adapter->XmtRingZeroIndex) {
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAResF10",
|
|
|
|
adapter, SXG_MAX_ENTRIES, 0, 0);
|
|
|
|
status = STATUS_RESOURCES;
|
|
|
|
goto per_tcb_allocation_failed;
|
|
|
|
}
|
|
|
|
memset(adapter->XmtRingZeroIndex, 0, sizeof(u32));
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlcResS",
|
|
|
|
adapter, SXG_MAX_ENTRIES, 0, 0);
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s EXIT\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_config_pci -
|
|
|
|
*
|
|
|
|
* Set up PCI Configuration space
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* pcidev - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static void sxg_config_pci(struct pci_dev *pcidev)
|
|
|
|
{
|
|
|
|
u16 pci_command;
|
|
|
|
u16 new_command;
|
|
|
|
|
|
|
|
pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s PCI command[%4.4x]\n", __func__, pci_command);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set the command register */
|
|
|
|
new_command = pci_command | (PCI_COMMAND_MEMORY | /* Memory Space Enable */
|
|
|
|
PCI_COMMAND_MASTER | /* Bus master enable */
|
|
|
|
PCI_COMMAND_INVALIDATE | /* Memory write and invalidate */
|
|
|
|
PCI_COMMAND_PARITY | /* Parity error response */
|
|
|
|
PCI_COMMAND_SERR | /* System ERR */
|
|
|
|
PCI_COMMAND_FAST_BACK); /* Fast back-to-back */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (pci_command != new_command) {
|
|
|
|
DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, pci_command, new_command);
|
2008-08-21 21:04:55 +00:00
|
|
|
pci_write_config_word(pcidev, PCI_COMMAND, new_command);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
static unsigned char temp_mac_address[6] = { 0x00, 0xab, 0xcd, 0xef, 0x12, 0x69 };
|
|
|
|
/*
|
|
|
|
* sxg_read_config
|
|
|
|
* @adapter : Pointer to the adapter structure for the card
|
|
|
|
* This function will read the configuration data from EEPROM/FLASH
|
|
|
|
*/
|
|
|
|
static inline int sxg_read_config(struct adapter_t *adapter)
|
|
|
|
{
|
|
|
|
//struct sxg_config data;
|
|
|
|
struct SW_CFG_DATA *data;
|
|
|
|
dma_addr_t p_addr;
|
|
|
|
unsigned long status;
|
|
|
|
unsigned long i;
|
|
|
|
|
|
|
|
data = pci_alloc_consistent(adapter->pcidev, sizeof(struct SW_CFG_DATA), &p_addr);
|
|
|
|
if(!data) {
|
|
|
|
/* We cant get even this much memory. Raise a hell
|
|
|
|
* Get out of here
|
|
|
|
*/
|
|
|
|
printk(KERN_ERR"%s : Could not allocate memory for reading EEPROM\n", __FUNCTION__);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].ConfigStat, SXG_CFG_TIMEOUT, TRUE);
|
|
|
|
|
|
|
|
WRITE_REG64(adapter, adapter->UcodeRegs[0].Config, p_addr, 0);
|
|
|
|
for(i=0; i<1000; i++) {
|
|
|
|
READ_REG(adapter->UcodeRegs[0].ConfigStat, status);
|
|
|
|
if (status != SXG_CFG_TIMEOUT)
|
|
|
|
break;
|
|
|
|
mdelay(1); /* Do we really need this */
|
|
|
|
}
|
|
|
|
|
|
|
|
switch(status) {
|
|
|
|
case SXG_CFG_LOAD_EEPROM: /*Config read from EEPROM succeeded */
|
|
|
|
case SXG_CFG_LOAD_FLASH: /* onfig read from Flash succeeded */
|
|
|
|
/* Copy the MAC address to adapter structure */
|
|
|
|
memcpy(temp_mac_address, data->MacAddr[0].MacAddr, 6);
|
|
|
|
/* TODO: We are not doing the remaining part : FRU, etc */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SXG_CFG_TIMEOUT:
|
|
|
|
case SXG_CFG_LOAD_INVALID:
|
|
|
|
case SXG_CFG_LOAD_ERROR:
|
|
|
|
default: /* Fix default handler later */
|
|
|
|
printk(KERN_WARNING"%s : We could not read the config word."
|
|
|
|
"Status = %ld\n", __FUNCTION__, status);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
pci_free_consistent(adapter->pcidev, sizeof(struct SW_CFG_DATA), data, p_addr);
|
|
|
|
if (adapter->netdev) {
|
|
|
|
memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
|
|
|
|
memcpy(adapter->netdev->perm_addr, adapter->currmacaddr, 6);
|
|
|
|
}
|
|
|
|
printk("LINSYS : These are the new MAC address\n");
|
|
|
|
sxg_dbg_macaddrs(adapter);
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2008-08-21 21:04:55 +00:00
|
|
|
static int sxg_entry_probe(struct pci_dev *pcidev,
|
|
|
|
const struct pci_device_id *pci_tbl_entry)
|
|
|
|
{
|
|
|
|
static int did_version = 0;
|
|
|
|
int err;
|
|
|
|
struct net_device *netdev;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter;
|
2008-08-21 21:04:55 +00:00
|
|
|
void __iomem *memmapped_ioaddr;
|
|
|
|
u32 status = 0;
|
|
|
|
ulong mmio_start = 0;
|
|
|
|
ulong mmio_len = 0;
|
|
|
|
|
|
|
|
DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, jiffies, smp_processor_id());
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize trace buffer */
|
2008-08-21 21:04:55 +00:00
|
|
|
#ifdef ATKDBG
|
|
|
|
SxgTraceBuffer = &LSxgTraceBuffer;
|
|
|
|
SXG_TRACE_INIT(SxgTraceBuffer, TRACE_NOISY);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
sxg_global.dynamic_intagg = dynamic_intagg;
|
|
|
|
|
|
|
|
err = pci_enable_device(pcidev);
|
|
|
|
|
|
|
|
DBG_ERROR("Call pci_enable_device(%p) status[%x]\n", pcidev, err);
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sxg_debug > 0 && did_version++ == 0) {
|
|
|
|
printk(KERN_INFO "%s\n", sxg_banner);
|
|
|
|
printk(KERN_INFO "%s\n", DRV_VERSION);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(err = pci_set_dma_mask(pcidev, DMA_64BIT_MASK))) {
|
|
|
|
DBG_ERROR("pci_set_dma_mask(DMA_64BIT_MASK) successful\n");
|
|
|
|
} else {
|
|
|
|
if ((err = pci_set_dma_mask(pcidev, DMA_32BIT_MASK))) {
|
|
|
|
DBG_ERROR
|
|
|
|
("No usable DMA configuration, aborting err[%x]\n",
|
|
|
|
err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
DBG_ERROR("pci_set_dma_mask(DMA_32BIT_MASK) successful\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG_ERROR("Call pci_request_regions\n");
|
|
|
|
|
|
|
|
err = pci_request_regions(pcidev, DRV_NAME);
|
|
|
|
if (err) {
|
|
|
|
DBG_ERROR("pci_request_regions FAILED err[%x]\n", err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG_ERROR("call pci_set_master\n");
|
|
|
|
pci_set_master(pcidev);
|
|
|
|
|
|
|
|
DBG_ERROR("call alloc_etherdev\n");
|
2008-10-28 22:42:02 +00:00
|
|
|
netdev = alloc_etherdev(sizeof(struct adapter_t));
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!netdev) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto err_out_exit_sxg_probe;
|
|
|
|
}
|
|
|
|
DBG_ERROR("alloc_etherdev for slic netdev[%p]\n", netdev);
|
|
|
|
|
|
|
|
SET_NETDEV_DEV(netdev, &pcidev->dev);
|
|
|
|
|
|
|
|
pci_set_drvdata(pcidev, netdev);
|
|
|
|
adapter = netdev_priv(netdev);
|
|
|
|
adapter->netdev = netdev;
|
|
|
|
adapter->pcidev = pcidev;
|
|
|
|
|
|
|
|
mmio_start = pci_resource_start(pcidev, 0);
|
|
|
|
mmio_len = pci_resource_len(pcidev, 0);
|
|
|
|
|
|
|
|
DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
|
|
|
|
mmio_start, mmio_len);
|
|
|
|
|
|
|
|
memmapped_ioaddr = ioremap(mmio_start, mmio_len);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__,
|
2008-10-06 00:38:52 +00:00
|
|
|
memmapped_ioaddr);
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!memmapped_ioaddr) {
|
|
|
|
DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, mmio_len, mmio_start);
|
2008-08-21 21:04:55 +00:00
|
|
|
goto err_out_free_mmio_region;
|
|
|
|
}
|
|
|
|
|
2008-10-06 00:38:52 +00:00
|
|
|
DBG_ERROR
|
|
|
|
("sxg: %s found Alacritech SXG PCI, MMIO at %p, start[%lx] len[%lx], IRQ %d.\n",
|
2008-08-21 21:04:55 +00:00
|
|
|
__func__, memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq);
|
|
|
|
|
2008-10-06 00:38:52 +00:00
|
|
|
adapter->HwRegs = (void *)memmapped_ioaddr;
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->base_addr = memmapped_ioaddr;
|
|
|
|
|
|
|
|
mmio_start = pci_resource_start(pcidev, 2);
|
|
|
|
mmio_len = pci_resource_len(pcidev, 2);
|
|
|
|
|
|
|
|
DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
|
|
|
|
mmio_start, mmio_len);
|
|
|
|
|
|
|
|
memmapped_ioaddr = ioremap(mmio_start, mmio_len);
|
2008-10-06 00:38:52 +00:00
|
|
|
DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__,
|
|
|
|
memmapped_ioaddr);
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!memmapped_ioaddr) {
|
|
|
|
DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, mmio_len, mmio_start);
|
2008-08-21 21:04:55 +00:00
|
|
|
goto err_out_free_mmio_region;
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, "
|
|
|
|
"start[%lx] len[%lx], IRQ %d.\n", __func__,
|
|
|
|
memmapped_ioaddr, mmio_start, mmio_len, pcidev->irq);
|
|
|
|
|
|
|
|
adapter->UcodeRegs = (void *)memmapped_ioaddr;
|
|
|
|
|
|
|
|
adapter->State = SXG_STATE_INITIALIZING;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Maintain a list of all adapters anchored by */
|
|
|
|
/* the global SxgDriver structure. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Next = SxgDriver.Adapters;
|
|
|
|
SxgDriver.Adapters = adapter;
|
|
|
|
adapter->AdapterID = ++SxgDriver.AdapterID;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize CRC table used to determine multicast hash */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_mcast_init_crc32();
|
|
|
|
|
|
|
|
adapter->JumboEnabled = FALSE;
|
|
|
|
adapter->RssEnabled = FALSE;
|
|
|
|
if (adapter->JumboEnabled) {
|
|
|
|
adapter->FrameSize = JUMBOMAXFRAME;
|
|
|
|
adapter->ReceiveBufferSize = SXG_RCV_JUMBO_BUFFER_SIZE;
|
|
|
|
} else {
|
|
|
|
adapter->FrameSize = ETHERMAXFRAME;
|
|
|
|
adapter->ReceiveBufferSize = SXG_RCV_DATA_BUFFER_SIZE;
|
|
|
|
}
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* status = SXG_READ_EEPROM(adapter); */
|
|
|
|
/* if (!status) { */
|
|
|
|
/* goto sxg_init_bad; */
|
|
|
|
/* } */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_config_pci(pcidev);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_init_driver();
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
adapter->vendid = pci_tbl_entry->vendor;
|
|
|
|
adapter->devid = pci_tbl_entry->device;
|
|
|
|
adapter->subsysid = pci_tbl_entry->subdevice;
|
|
|
|
adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F);
|
|
|
|
adapter->functionnumber = (pcidev->devfn & 0x7);
|
|
|
|
adapter->memorylength = pci_resource_len(pcidev, 0);
|
|
|
|
adapter->irq = pcidev->irq;
|
|
|
|
adapter->next_netdevice = head_netdevice;
|
|
|
|
head_netdevice = netdev;
|
2008-10-20 23:28:58 +00:00
|
|
|
adapter->port = 0; /*adapter->functionnumber; */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Allocate memory and other resources */
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
status = sxg_allocate_resources(adapter);
|
|
|
|
DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, status);
|
2008-08-21 21:04:55 +00:00
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
goto err_out_unmap;
|
|
|
|
}
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) {
|
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2009-01-05 15:43:23 +00:00
|
|
|
sxg_read_config(adapter);
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_adapter_set_hwaddr(adapter);
|
|
|
|
} else {
|
|
|
|
adapter->state = ADAPT_FAIL;
|
|
|
|
adapter->linkstate = LINK_DOWN;
|
|
|
|
DBG_ERROR("sxg_download_microcode FAILED status[%x]\n", status);
|
|
|
|
}
|
|
|
|
|
|
|
|
netdev->base_addr = (unsigned long)adapter->base_addr;
|
|
|
|
netdev->irq = adapter->irq;
|
|
|
|
netdev->open = sxg_entry_open;
|
|
|
|
netdev->stop = sxg_entry_halt;
|
|
|
|
netdev->hard_start_xmit = sxg_send_packets;
|
|
|
|
netdev->do_ioctl = sxg_ioctl;
|
|
|
|
#if XXXTODO
|
|
|
|
netdev->set_mac_address = sxg_mac_set_address;
|
|
|
|
#if SLIC_GET_STATS_ENABLED
|
|
|
|
netdev->get_stats = sxg_get_stats;
|
|
|
|
#endif
|
|
|
|
#endif
|
2009-01-05 15:43:23 +00:00
|
|
|
netdev->set_multicast_list = sxg_mcast_set_list;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
strcpy(netdev->name, "eth%d");
|
2008-10-20 23:28:58 +00:00
|
|
|
/* strcpy(netdev->name, pci_name(pcidev)); */
|
2008-08-21 21:04:55 +00:00
|
|
|
if ((err = register_netdev(netdev))) {
|
|
|
|
DBG_ERROR("Cannot register net device, aborting. %s\n",
|
|
|
|
netdev->name);
|
|
|
|
goto err_out_unmap;
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG_ERROR
|
|
|
|
("sxg: %s addr 0x%lx, irq %d, MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
|
|
|
|
netdev->name, netdev->base_addr, pcidev->irq, netdev->dev_addr[0],
|
|
|
|
netdev->dev_addr[1], netdev->dev_addr[2], netdev->dev_addr[3],
|
|
|
|
netdev->dev_addr[4], netdev->dev_addr[5]);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/*sxg_init_bad: */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(status == FALSE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* sxg_free_adapter(adapter); */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
status, jiffies, smp_processor_id());
|
|
|
|
return status;
|
|
|
|
|
|
|
|
err_out_unmap:
|
|
|
|
iounmap((void *)memmapped_ioaddr);
|
|
|
|
|
|
|
|
err_out_free_mmio_region:
|
|
|
|
release_mem_region(mmio_start, mmio_len);
|
|
|
|
|
|
|
|
err_out_exit_sxg_probe:
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __func__, jiffies,
|
2008-08-21 21:04:55 +00:00
|
|
|
smp_processor_id());
|
|
|
|
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/***********************************************************************
|
|
|
|
* LINE BASE Interrupt routines..
|
|
|
|
***********************************************************************/
|
|
|
|
/*
|
|
|
|
*
|
|
|
|
* sxg_disable_interrupt
|
|
|
|
*
|
|
|
|
* DisableInterrupt Handler
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
*
|
|
|
|
* adapter: Our adapter structure
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* None.
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_disable_interrupt(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DisIntr",
|
|
|
|
adapter, adapter->InterruptsEnabled, 0, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* For now, RSS is disabled with line based interrupts */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(adapter->RssEnabled == FALSE);
|
|
|
|
ASSERT(adapter->MsiEnabled == FALSE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Turn off interrupts by writing to the icr register. */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_DISABLE), TRUE);
|
|
|
|
|
|
|
|
adapter->InterruptsEnabled = 0;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDisIntr",
|
|
|
|
adapter, adapter->InterruptsEnabled, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
*
|
|
|
|
* sxg_enable_interrupt
|
|
|
|
*
|
|
|
|
* EnableInterrupt Handler
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
*
|
|
|
|
* adapter: Our adapter structure
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* None.
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_enable_interrupt(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "EnIntr",
|
|
|
|
adapter, adapter->InterruptsEnabled, 0, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* For now, RSS is disabled with line based interrupts */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(adapter->RssEnabled == FALSE);
|
|
|
|
ASSERT(adapter->MsiEnabled == FALSE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Turn on interrupts by writing to the icr register. */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_ENABLE), TRUE);
|
|
|
|
|
|
|
|
adapter->InterruptsEnabled = 1;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XEnIntr",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
*
|
|
|
|
* sxg_isr - Process an line-based interrupt
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
* Context - Our adapter structure
|
|
|
|
* QueueDefault - Output parameter to queue to default CPU
|
|
|
|
* TargetCpus - Output bitmap to schedule DPC's
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* TRUE if our interrupt
|
|
|
|
*/
|
|
|
|
static irqreturn_t sxg_isr(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
p_net_device dev = (p_net_device) dev_id;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* u32 CpuMask = 0, i; */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
adapter->Stats.NumInts++;
|
|
|
|
if (adapter->Isr[0] == 0) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* The SLIC driver used to experience a number of spurious interrupts */
|
|
|
|
/* due to the delay associated with the masking of the interrupt */
|
|
|
|
/* (we'd bounce back in here). If we see that again with Sahara, */
|
|
|
|
/* add a READ_REG of the Icr register after the WRITE_REG below. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.FalseInts++;
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Move the Isr contents and clear the value in */
|
|
|
|
/* shared memory, and mask interrupts */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->IsrCopy[0] = adapter->Isr[0];
|
|
|
|
adapter->Isr[0] = 0;
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].Icr, SXG_ICR(0, SXG_ICR_MASK), TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* ASSERT(adapter->IsrDpcsPending == 0); */
|
|
|
|
#if XXXTODO /* RSS Stuff */
|
|
|
|
/* If RSS is enabled and the ISR specifies */
|
|
|
|
/* SXG_ISR_EVENT, then schedule DPC's */
|
|
|
|
/* based on event queues. */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->RssEnabled && (adapter->IsrCopy[0] & SXG_ISR_EVENT)) {
|
|
|
|
for (i = 0;
|
|
|
|
i < adapter->RssSystemInfo->ProcessorInfo.RssCpuCount;
|
|
|
|
i++) {
|
2008-10-28 22:42:02 +00:00
|
|
|
struct XG_EVENT_RING *EventRing = &adapter->EventRings[i];
|
|
|
|
struct SXG_EVENT *Event =
|
2008-08-21 21:04:55 +00:00
|
|
|
&EventRing->Ring[adapter->NextEvent[i]];
|
2008-10-06 00:38:52 +00:00
|
|
|
unsigned char Cpu =
|
|
|
|
adapter->RssSystemInfo->RssIdToCpu[i];
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Event->Status & EVENT_STATUS_VALID) {
|
|
|
|
adapter->IsrDpcsPending++;
|
|
|
|
CpuMask |= (1 << Cpu);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now, either schedule the CPUs specified by the CpuMask, */
|
|
|
|
/* or queue default */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (CpuMask) {
|
|
|
|
*QueueDefault = FALSE;
|
|
|
|
} else {
|
|
|
|
adapter->IsrDpcsPending = 1;
|
|
|
|
*QueueDefault = TRUE;
|
|
|
|
}
|
|
|
|
*TargetCpus = CpuMask;
|
|
|
|
#endif
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* There are no DPCs in Linux, so call the handler now */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_handle_interrupt(adapter);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
int debug_inthandler = 0;
|
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_handle_interrupt(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-20 23:28:58 +00:00
|
|
|
/* unsigned char RssId = 0; */
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 NewIsr;
|
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
if (++debug_inthandler < 20) {
|
2008-08-21 21:04:55 +00:00
|
|
|
DBG_ERROR("Enter sxg_handle_interrupt ISR[%x]\n",
|
|
|
|
adapter->IsrCopy[0]);
|
|
|
|
}
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "HndlIntr",
|
|
|
|
adapter, adapter->IsrCopy[0], 0, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* For now, RSS is disabled with line based interrupts */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(adapter->RssEnabled == FALSE);
|
|
|
|
ASSERT(adapter->MsiEnabled == FALSE);
|
|
|
|
ASSERT(adapter->IsrCopy[0]);
|
2008-10-20 23:28:58 +00:00
|
|
|
/*/////////////////////////// */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Always process the event queue. */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_process_event_queue(adapter,
|
|
|
|
(adapter->RssEnabled ? /*RssId */ 0 : 0));
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
#if XXXTODO /* RSS stuff */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (--adapter->IsrDpcsPending) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* We're done. */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(adapter->RssEnabled);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DPCsPend",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Last (or only) DPC processes the ISR and clears the interrupt. */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
NewIsr = sxg_process_isr(adapter, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Reenable interrupts */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->IsrCopy[0] = 0;
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ClearIsr",
|
|
|
|
adapter, NewIsr, 0, 0);
|
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
if (debug_inthandler < 20) {
|
2008-08-21 21:04:55 +00:00
|
|
|
DBG_ERROR
|
|
|
|
("Exit sxg_handle_interrupt2 after enabling interrupt\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].Isr, NewIsr, TRUE);
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XHndlInt",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
*
|
|
|
|
* sxg_process_isr - Process an interrupt. Called from the line-based and
|
|
|
|
* message based interrupt DPC routines
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
* adapter - Our adapter structure
|
|
|
|
* Queue - The ISR that needs processing
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* None
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_process_isr(struct adapter_t *adapter, u32 MessageId)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
u32 Isr = adapter->IsrCopy[MessageId];
|
|
|
|
u32 NewIsr = 0;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "ProcIsr",
|
|
|
|
adapter, Isr, 0, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Error */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_ERR) {
|
|
|
|
if (Isr & SXG_ISR_PDQF) {
|
|
|
|
adapter->Stats.PdqFull++;
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s: SXG_ISR_ERR PDQF!!\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* No host buffer */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_RMISS) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* There is a bunch of code in the SLIC driver which */
|
|
|
|
/* attempts to process more receive events per DPC */
|
|
|
|
/* if we start to fall behind. We'll probably */
|
|
|
|
/* need to do something similar here, but hold */
|
|
|
|
/* off for now. I don't want to make the code more */
|
|
|
|
/* complicated than strictly needed. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.RcvNoBuffer++;
|
|
|
|
if (adapter->Stats.RcvNoBuffer < 5) {
|
|
|
|
DBG_ERROR("%s: SXG_ISR_ERR RMISS!!\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Card crash */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_DEAD) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set aside the crash info and set the adapter state to RESET */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->CrashCpu =
|
2008-10-06 00:38:52 +00:00
|
|
|
(unsigned char)((Isr & SXG_ISR_CPU) >>
|
|
|
|
SXG_ISR_CPU_SHIFT);
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->CrashLocation = (ushort) (Isr & SXG_ISR_CRASH);
|
|
|
|
adapter->Dead = TRUE;
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->CrashLocation, adapter->CrashCpu);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Event ring full */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_ERFULL) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Same issue as RMISS, really. This means the */
|
|
|
|
/* host is falling behind the card. Need to increase */
|
|
|
|
/* event ring size, process more events per interrupt, */
|
|
|
|
/* and/or reduce/remove interrupt aggregation. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.EventRingFull++;
|
|
|
|
DBG_ERROR("%s: SXG_ISR_ERR EVENT RING FULL!!\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Transmit drop - no DRAM buffers or XMT error */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_XDROP) {
|
|
|
|
adapter->Stats.XmtDrops++;
|
|
|
|
adapter->Stats.XmtErrors++;
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s: SXG_ISR_ERR XDROP!!\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Slowpath send completions */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_SPSEND) {
|
|
|
|
sxg_complete_slow_send(adapter);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Dump */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_UPC) {
|
2008-10-20 23:28:58 +00:00
|
|
|
ASSERT(adapter->DumpCmdRunning); /* Maybe change when debug is added.. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->DumpCmdRunning = FALSE;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Link event */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_LINK) {
|
|
|
|
sxg_link_event(adapter);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Debug - breakpoint hit */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_BREAK) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* At the moment AGDB isn't written to support interactive */
|
|
|
|
/* debug sessions. When it is, this interrupt will be used */
|
|
|
|
/* to signal AGDB that it has hit a breakpoint. For now, ASSERT. */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(0);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Heartbeat response */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Isr & SXG_ISR_PING) {
|
|
|
|
adapter->PingOutstanding = FALSE;
|
|
|
|
}
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XProcIsr",
|
|
|
|
adapter, Isr, NewIsr, 0);
|
|
|
|
|
|
|
|
return (NewIsr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
*
|
|
|
|
* sxg_process_event_queue - Process our event queue
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
* - adapter - Adapter structure
|
|
|
|
* - RssId - The event queue requiring processing
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* None.
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static u32 sxg_process_event_queue(struct adapter_t *adapter, u32 RssId)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_EVENT_RING *EventRing = &adapter->EventRings[RssId];
|
|
|
|
struct SXG_EVENT *Event = &EventRing->Ring[adapter->NextEvent[RssId]];
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 EventsProcessed = 0, Batches = 0;
|
|
|
|
u32 num_skbs = 0;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
|
|
|
|
struct sk_buff *prev_skb = NULL;
|
|
|
|
struct sk_buff *IndicationList[SXG_RCV_ARRAYSIZE];
|
|
|
|
u32 Index;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_RCV_DATA_BUFFER_HDR *RcvDataBufferHdr;
|
2008-08-21 21:04:55 +00:00
|
|
|
#endif
|
|
|
|
u32 ReturnStatus = 0;
|
|
|
|
|
|
|
|
ASSERT((adapter->State == SXG_STATE_RUNNING) ||
|
|
|
|
(adapter->State == SXG_STATE_PAUSING) ||
|
|
|
|
(adapter->State == SXG_STATE_PAUSED) ||
|
|
|
|
(adapter->State == SXG_STATE_HALTING));
|
2008-10-20 23:28:58 +00:00
|
|
|
/* We may still have unprocessed events on the queue if */
|
|
|
|
/* the card crashed. Don't process them. */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->Dead) {
|
|
|
|
return (0);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* In theory there should only be a single processor that */
|
|
|
|
/* accesses this queue, and only at interrupt-DPC time. So */
|
|
|
|
/* we shouldn't need a lock for any of this. */
|
2008-08-21 21:04:55 +00:00
|
|
|
while (Event->Status & EVENT_STATUS_VALID) {
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "Event",
|
|
|
|
Event, Event->Code, Event->Status,
|
|
|
|
adapter->NextEvent);
|
|
|
|
switch (Event->Code) {
|
|
|
|
case EVENT_CODE_BUFFERS:
|
2008-10-20 23:28:58 +00:00
|
|
|
ASSERT(!(Event->CommandIndex & 0xFF00)); /* SXG_RING_INFO Head & Tail == unsigned char */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_complete_descriptor_blocks(adapter,
|
|
|
|
Event->CommandIndex);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
break;
|
|
|
|
case EVENT_CODE_SLOWRCV:
|
|
|
|
--adapter->RcvBuffersOnCard;
|
|
|
|
if ((skb = sxg_slow_receive(adapter, Event))) {
|
|
|
|
u32 rx_bytes;
|
|
|
|
#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Add it to our indication list */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_ADD_RCV_PACKET(adapter, skb, prev_skb,
|
|
|
|
IndicationList, num_skbs);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* In Linux, we just pass up each skb to the protocol above at this point, */
|
|
|
|
/* there is no capability of an indication list. */
|
2008-08-21 21:04:55 +00:00
|
|
|
#else
|
2008-10-20 23:28:58 +00:00
|
|
|
/* CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE); */
|
|
|
|
rx_bytes = Event->Length; /* (rcvbuf->length & IRHDDR_FLEN_MSK); */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->stats.rx_packets++;
|
|
|
|
adapter->stats.rx_bytes += rx_bytes;
|
|
|
|
#if SXG_OFFLOAD_IP_CHECKSUM
|
|
|
|
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
|
|
|
#endif
|
|
|
|
skb->dev = adapter->netdev;
|
|
|
|
netif_rx(skb);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DBG_ERROR("%s: ERROR Invalid EventCode %d\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, Event->Code);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* ASSERT(0); */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* See if we need to restock card receive buffers. */
|
|
|
|
/* There are two things to note here: */
|
|
|
|
/* First - This test is not SMP safe. The */
|
|
|
|
/* adapter->BuffersOnCard field is protected via atomic interlocked calls, but */
|
|
|
|
/* we do not protect it with respect to these tests. The only way to do that */
|
|
|
|
/* is with a lock, and I don't want to grab a lock every time we adjust the */
|
|
|
|
/* BuffersOnCard count. Instead, we allow the buffer replenishment to be off */
|
|
|
|
/* once in a while. The worst that can happen is the card is given one */
|
|
|
|
/* more-or-less descriptor block than the arbitrary value we've chosen. */
|
|
|
|
/* No big deal */
|
|
|
|
/* In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard is adjusted. */
|
|
|
|
/* Second - We expect this test to rarely evaluate to true. We attempt to */
|
|
|
|
/* refill descriptor blocks as they are returned to us */
|
|
|
|
/* (sxg_complete_descriptor_blocks), so The only time this should evaluate */
|
|
|
|
/* to true is when sxg_complete_descriptor_blocks failed to allocate */
|
|
|
|
/* receive buffers. */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
|
|
|
|
sxg_stock_rcv_buffers(adapter);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* It's more efficient to just set this to zero. */
|
|
|
|
/* But clearing the top bit saves potential debug info... */
|
2008-08-21 21:04:55 +00:00
|
|
|
Event->Status &= ~EVENT_STATUS_VALID;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Advanct to the next event */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_ADVANCE_INDEX(adapter->NextEvent[RssId], EVENT_RING_SIZE);
|
|
|
|
Event = &EventRing->Ring[adapter->NextEvent[RssId]];
|
|
|
|
EventsProcessed++;
|
|
|
|
if (EventsProcessed == EVENT_RING_BATCH) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Release a batch of events back to the card */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
|
|
|
|
EVENT_RING_BATCH, FALSE);
|
|
|
|
EventsProcessed = 0;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* If we've processed our batch limit, break out of the */
|
|
|
|
/* loop and return SXG_ISR_EVENT to arrange for us to */
|
|
|
|
/* be called again */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (Batches++ == EVENT_BATCH_LIMIT) {
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
|
|
|
|
TRACE_NOISY, "EvtLimit", Batches,
|
|
|
|
adapter->NextEvent, 0, 0);
|
|
|
|
ReturnStatus = SXG_ISR_EVENT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Indicate any received dumb-nic frames */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_INDICATE_PACKETS(adapter, IndicationList, num_skbs);
|
|
|
|
#endif
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Release events back to the card. */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (EventsProcessed) {
|
|
|
|
WRITE_REG(adapter->UcodeRegs[RssId].EventRelease,
|
|
|
|
EventsProcessed, FALSE);
|
|
|
|
}
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XPrcEvnt",
|
|
|
|
Batches, EventsProcessed, adapter->NextEvent, num_skbs);
|
|
|
|
|
|
|
|
return (ReturnStatus);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_complete_slow_send - Complete slowpath or dumb-nic sends
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
|
|
|
|
* Return
|
|
|
|
* None
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_complete_slow_send(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_XMT_RING *XmtRing = &adapter->XmtRings[0];
|
|
|
|
struct SXG_RING_INFO *XmtRingInfo = &adapter->XmtRingZeroInfo;
|
2008-10-06 00:38:52 +00:00
|
|
|
u32 *ContextType;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_CMD *XmtCmd;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* NOTE - This lock is dropped and regrabbed in this loop. */
|
|
|
|
/* This means two different processors can both be running */
|
|
|
|
/* through this loop. Be *very* careful. */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock(&adapter->XmtZeroLock);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnds",
|
|
|
|
adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
|
|
|
|
|
|
|
|
while (XmtRingInfo->Tail != *adapter->XmtRingZeroIndex) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Locate the current Cmd (ring descriptor entry), and */
|
|
|
|
/* associated SGL, and advance the tail */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RETURN_CMD(XmtRing, XmtRingInfo, XmtCmd, ContextType);
|
|
|
|
ASSERT(ContextType);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
|
|
|
|
XmtRingInfo->Head, XmtRingInfo->Tail, XmtCmd, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Clear the SGL field. */
|
2008-08-21 21:04:55 +00:00
|
|
|
XmtCmd->Sgl = 0;
|
|
|
|
|
|
|
|
switch (*ContextType) {
|
|
|
|
case SXG_SGL_DUMB:
|
|
|
|
{
|
|
|
|
struct sk_buff *skb;
|
2009-01-05 15:43:23 +00:00
|
|
|
struct SXG_SCATTER_GATHER *SxgSgl = (struct SXG_SCATTER_GATHER *)ContextType;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Dumb-nic send. Command context is the dumb-nic SGL */
|
2008-08-21 21:04:55 +00:00
|
|
|
skb = (struct sk_buff *)ContextType;
|
2009-01-05 15:43:23 +00:00
|
|
|
skb = SxgSgl->DumbPacket;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Complete the send */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer,
|
|
|
|
TRACE_IMPORTANT, "DmSndCmp", skb, 0,
|
|
|
|
0, 0);
|
2009-01-05 15:43:23 +00:00
|
|
|
printk("ASK:sxg_complete_slow_send: freeing an skb [%p]\n", skb);
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(adapter->Stats.XmtQLen);
|
2008-10-20 23:28:58 +00:00
|
|
|
adapter->Stats.XmtQLen--; /* within XmtZeroLock */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.XmtOk++;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now drop the lock and complete the send back to */
|
|
|
|
/* Microsoft. We need to drop the lock because */
|
|
|
|
/* Microsoft can come back with a chimney send, which */
|
|
|
|
/* results in a double trip in SxgTcpOuput */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_unlock(&adapter->XmtZeroLock);
|
|
|
|
SXG_COMPLETE_DUMB_SEND(adapter, skb);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* and reacquire.. */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock(&adapter->XmtZeroLock);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ASSERT(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock(&adapter->XmtZeroLock);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpSnd",
|
|
|
|
adapter, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_slow_receive
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* Event - Receive event
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* skb
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static struct sk_buff *sxg_slow_receive(struct adapter_t *adapter, struct SXG_EVENT *Event)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_RCV_DATA_BUFFER_HDR *RcvDataBufferHdr;
|
2008-08-21 21:04:55 +00:00
|
|
|
struct sk_buff *Packet;
|
2009-01-05 15:43:23 +00:00
|
|
|
unsigned char*data;
|
|
|
|
int i;
|
|
|
|
char dstr[128];
|
|
|
|
char *dptr = dstr;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
RcvDataBufferHdr = (struct SXG_RCV_DATA_BUFFER_HDR*) Event->HostHandle;
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(RcvDataBufferHdr);
|
|
|
|
ASSERT(RcvDataBufferHdr->State == SXG_BUFFER_ONCARD);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "SlowRcv", Event,
|
|
|
|
RcvDataBufferHdr, RcvDataBufferHdr->State,
|
|
|
|
RcvDataBufferHdr->VirtualAddress);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Drop rcv frames in non-running state */
|
2008-08-21 21:04:55 +00:00
|
|
|
switch (adapter->State) {
|
|
|
|
case SXG_STATE_RUNNING:
|
|
|
|
break;
|
|
|
|
case SXG_STATE_PAUSING:
|
|
|
|
case SXG_STATE_PAUSED:
|
|
|
|
case SXG_STATE_HALTING:
|
|
|
|
goto drop;
|
|
|
|
default:
|
|
|
|
ASSERT(0);
|
|
|
|
goto drop;
|
|
|
|
}
|
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
printk("ASK:sxg_slow_receive: event host handle %p\n", RcvDataBufferHdr);
|
|
|
|
data = SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr);
|
|
|
|
for (i = 0; i < 32; i++)
|
|
|
|
dptr += sprintf(dptr, "%02x ", (unsigned)data[i]);
|
|
|
|
printk("ASK:sxg_slow_receive: data %s\n", dstr);
|
|
|
|
//memcpy(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr), RcvDataBufferHdr->VirtualAddress, Event->Length);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Change buffer state to UPSTREAM */
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM;
|
|
|
|
if (Event->Status & EVENT_STATUS_RCVERR) {
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError",
|
|
|
|
Event, Event->Status, Event->HostHandle, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* XXXTODO - Remove this print later */
|
2008-10-06 00:38:52 +00:00
|
|
|
DBG_ERROR("SXG: Receive error %x\n", *(u32 *)
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr));
|
2008-10-06 00:38:52 +00:00
|
|
|
sxg_process_rcv_error(adapter, *(u32 *)
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RECEIVE_DATA_LOCATION
|
|
|
|
(RcvDataBufferHdr));
|
|
|
|
goto drop;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
#if XXXTODO /* VLAN stuff */
|
|
|
|
/* If there's a VLAN tag, extract it and validate it */
|
2008-10-28 22:42:02 +00:00
|
|
|
if (((struct ether_header*) (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr)))->
|
2008-08-21 21:04:55 +00:00
|
|
|
EtherType == ETHERTYPE_VLAN) {
|
|
|
|
if (SxgExtractVlanHeader(adapter, RcvDataBufferHdr, Event) !=
|
|
|
|
STATUS_SUCCESS) {
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY,
|
|
|
|
"BadVlan", Event,
|
|
|
|
SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
|
|
|
|
Event->Length, 0);
|
|
|
|
goto drop;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Dumb-nic frame. See if it passes our mac filter and update stats */
|
|
|
|
/* */
|
2009-01-05 15:43:23 +00:00
|
|
|
/* ASK if (!sxg_mac_filter(adapter,
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
|
|
|
|
Event->Length)) {
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvFiltr",
|
|
|
|
Event, SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
|
|
|
|
Event->Length, 0);
|
|
|
|
goto drop;
|
2009-01-05 15:43:23 +00:00
|
|
|
} */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
Packet = RcvDataBufferHdr->SxgDumbRcvPacket;
|
2009-01-05 15:43:23 +00:00
|
|
|
SXG_ADJUST_RCV_PACKET(Packet, RcvDataBufferHdr, Event);
|
|
|
|
Packet->protocol = eth_type_trans(Packet, adapter->netdev);
|
|
|
|
printk("ASK:sxg_slow_receive: protocol %x\n", (unsigned) Packet->protocol);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumbRcv",
|
|
|
|
RcvDataBufferHdr, Packet, Event->Length, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Lastly adjust the receive packet length. */
|
|
|
|
/* */
|
2009-01-05 15:43:23 +00:00
|
|
|
RcvDataBufferHdr->SxgDumbRcvPacket = NULL;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
|
2008-08-21 21:04:55 +00:00
|
|
|
return (Packet);
|
|
|
|
|
|
|
|
drop:
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DropRcv",
|
|
|
|
RcvDataBufferHdr, Event->Length, 0, 0);
|
|
|
|
adapter->Stats.RcvDiscards++;
|
|
|
|
spin_lock(&adapter->RcvQLock);
|
|
|
|
SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
|
|
|
|
spin_unlock(&adapter->RcvQLock);
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_process_rcv_error - process receive error and update
|
|
|
|
* stats
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
* adapter - Adapter structure
|
|
|
|
* ErrorStatus - 4-byte receive error status
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* None
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_process_rcv_error(struct adapter_t *adapter, u32 ErrorStatus)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
u32 Error;
|
|
|
|
|
|
|
|
adapter->Stats.RcvErrors++;
|
|
|
|
|
|
|
|
if (ErrorStatus & SXG_RCV_STATUS_TRANSPORT_ERROR) {
|
|
|
|
Error = ErrorStatus & SXG_RCV_STATUS_TRANSPORT_MASK;
|
|
|
|
switch (Error) {
|
|
|
|
case SXG_RCV_STATUS_TRANSPORT_CSUM:
|
|
|
|
adapter->Stats.TransportCsum++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_TRANSPORT_UFLOW:
|
|
|
|
adapter->Stats.TransportUflow++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_TRANSPORT_HDRLEN:
|
|
|
|
adapter->Stats.TransportHdrLen++;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (ErrorStatus & SXG_RCV_STATUS_NETWORK_ERROR) {
|
|
|
|
Error = ErrorStatus & SXG_RCV_STATUS_NETWORK_MASK;
|
|
|
|
switch (Error) {
|
|
|
|
case SXG_RCV_STATUS_NETWORK_CSUM:
|
|
|
|
adapter->Stats.NetworkCsum++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_NETWORK_UFLOW:
|
|
|
|
adapter->Stats.NetworkUflow++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_NETWORK_HDRLEN:
|
|
|
|
adapter->Stats.NetworkHdrLen++;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (ErrorStatus & SXG_RCV_STATUS_PARITY) {
|
|
|
|
adapter->Stats.Parity++;
|
|
|
|
}
|
|
|
|
if (ErrorStatus & SXG_RCV_STATUS_LINK_ERROR) {
|
|
|
|
Error = ErrorStatus & SXG_RCV_STATUS_LINK_MASK;
|
|
|
|
switch (Error) {
|
|
|
|
case SXG_RCV_STATUS_LINK_PARITY:
|
|
|
|
adapter->Stats.LinkParity++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_LINK_EARLY:
|
|
|
|
adapter->Stats.LinkEarly++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_LINK_BUFOFLOW:
|
|
|
|
adapter->Stats.LinkBufOflow++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_LINK_CODE:
|
|
|
|
adapter->Stats.LinkCode++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_LINK_DRIBBLE:
|
|
|
|
adapter->Stats.LinkDribble++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_LINK_CRC:
|
|
|
|
adapter->Stats.LinkCrc++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_LINK_OFLOW:
|
|
|
|
adapter->Stats.LinkOflow++;
|
|
|
|
break;
|
|
|
|
case SXG_RCV_STATUS_LINK_UFLOW:
|
|
|
|
adapter->Stats.LinkUflow++;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_mac_filter
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
* adapter - Adapter structure
|
|
|
|
* pether - Ethernet header
|
|
|
|
* length - Frame length
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* TRUE if the frame is to be allowed
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static bool sxg_mac_filter(struct adapter_t *adapter, struct ether_header *EtherHdr,
|
2008-10-06 00:38:52 +00:00
|
|
|
ushort length)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
bool EqualAddr;
|
|
|
|
|
|
|
|
if (SXG_MULTICAST_PACKET(EtherHdr)) {
|
|
|
|
if (SXG_BROADCAST_PACKET(EtherHdr)) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* broadcast */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->MacFilter & MAC_BCAST) {
|
|
|
|
adapter->Stats.DumbRcvBcastPkts++;
|
|
|
|
adapter->Stats.DumbRcvBcastBytes += length;
|
|
|
|
adapter->Stats.DumbRcvPkts++;
|
|
|
|
adapter->Stats.DumbRcvBytes += length;
|
|
|
|
return (TRUE);
|
|
|
|
}
|
|
|
|
} else {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* multicast */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->MacFilter & MAC_ALLMCAST) {
|
|
|
|
adapter->Stats.DumbRcvMcastPkts++;
|
|
|
|
adapter->Stats.DumbRcvMcastBytes += length;
|
|
|
|
adapter->Stats.DumbRcvPkts++;
|
|
|
|
adapter->Stats.DumbRcvBytes += length;
|
|
|
|
return (TRUE);
|
|
|
|
}
|
|
|
|
if (adapter->MacFilter & MAC_MCAST) {
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_MULTICAST_ADDRESS *MulticastAddrs =
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->MulticastAddrs;
|
|
|
|
while (MulticastAddrs) {
|
|
|
|
ETHER_EQ_ADDR(MulticastAddrs->Address,
|
|
|
|
EtherHdr->ether_dhost,
|
|
|
|
EqualAddr);
|
|
|
|
if (EqualAddr) {
|
|
|
|
adapter->Stats.
|
|
|
|
DumbRcvMcastPkts++;
|
|
|
|
adapter->Stats.
|
|
|
|
DumbRcvMcastBytes += length;
|
|
|
|
adapter->Stats.DumbRcvPkts++;
|
|
|
|
adapter->Stats.DumbRcvBytes +=
|
|
|
|
length;
|
|
|
|
return (TRUE);
|
|
|
|
}
|
|
|
|
MulticastAddrs = MulticastAddrs->Next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else if (adapter->MacFilter & MAC_DIRECTED) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Not broadcast or multicast. Must be directed at us or */
|
|
|
|
/* the card is in promiscuous mode. Either way, consider it */
|
|
|
|
/* ours if MAC_DIRECTED is set */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.DumbRcvUcastPkts++;
|
|
|
|
adapter->Stats.DumbRcvUcastBytes += length;
|
|
|
|
adapter->Stats.DumbRcvPkts++;
|
|
|
|
adapter->Stats.DumbRcvBytes += length;
|
|
|
|
return (TRUE);
|
|
|
|
}
|
|
|
|
if (adapter->MacFilter & MAC_PROMISC) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Whatever it is, keep it. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.DumbRcvPkts++;
|
|
|
|
adapter->Stats.DumbRcvBytes += length;
|
|
|
|
return (TRUE);
|
|
|
|
}
|
|
|
|
adapter->Stats.RcvDiscards++;
|
|
|
|
return (FALSE);
|
|
|
|
}
|
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_register_interrupt(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
if (!adapter->intrregistered) {
|
|
|
|
int retval;
|
|
|
|
|
|
|
|
DBG_ERROR
|
|
|
|
("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter, adapter->netdev->irq, NR_IRQS);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-06 00:38:52 +00:00
|
|
|
spin_unlock_irqrestore(&sxg_global.driver_lock,
|
|
|
|
sxg_global.flags);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
retval = request_irq(adapter->netdev->irq,
|
|
|
|
&sxg_isr,
|
|
|
|
IRQF_SHARED,
|
|
|
|
adapter->netdev->name, adapter->netdev);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
|
|
|
|
|
|
|
|
if (retval) {
|
|
|
|
DBG_ERROR("sxg: request_irq (%s) FAILED [%x]\n",
|
|
|
|
adapter->netdev->name, retval);
|
|
|
|
return (retval);
|
|
|
|
}
|
|
|
|
adapter->intrregistered = 1;
|
|
|
|
adapter->IntRegistered = TRUE;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Disable RSS with line-based interrupts */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->MsiEnabled = FALSE;
|
|
|
|
adapter->RssEnabled = FALSE;
|
|
|
|
DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter, adapter->netdev->irq);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_deregister_interrupt(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __func__, adapter);
|
2008-08-21 21:04:55 +00:00
|
|
|
#if XXXTODO
|
|
|
|
slic_init_cleanup(adapter);
|
|
|
|
#endif
|
|
|
|
memset(&adapter->stats, 0, sizeof(struct net_device_stats));
|
|
|
|
adapter->error_interrupts = 0;
|
|
|
|
adapter->rcv_interrupts = 0;
|
|
|
|
adapter->xmit_interrupts = 0;
|
|
|
|
adapter->linkevent_interrupts = 0;
|
|
|
|
adapter->upr_interrupts = 0;
|
|
|
|
adapter->num_isrs = 0;
|
|
|
|
adapter->xmit_completes = 0;
|
|
|
|
adapter->rcv_broadcasts = 0;
|
|
|
|
adapter->rcv_multicasts = 0;
|
|
|
|
adapter->rcv_unicasts = 0;
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_if_init
|
|
|
|
*
|
|
|
|
* Perform initialization of our slic interface.
|
|
|
|
*
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_if_init(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
p_net_device dev = adapter->netdev;
|
|
|
|
int status = 0;
|
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d] flags[%x]\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter->netdev->name,
|
2009-01-05 15:43:23 +00:00
|
|
|
adapter->state,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->linkstate, dev->flags);
|
|
|
|
|
|
|
|
/* adapter should be down at this point */
|
|
|
|
if (adapter->state != ADAPT_DOWN) {
|
|
|
|
DBG_ERROR("sxg_if_init adapter->state != ADAPT_DOWN\n");
|
|
|
|
return (-EIO);
|
|
|
|
}
|
|
|
|
ASSERT(adapter->linkstate == LINK_DOWN);
|
|
|
|
|
|
|
|
adapter->devflags_prev = dev->flags;
|
|
|
|
adapter->macopts = MAC_DIRECTED;
|
|
|
|
if (dev->flags) {
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s (%s) Set MAC options: ", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->netdev->name);
|
|
|
|
if (dev->flags & IFF_BROADCAST) {
|
|
|
|
adapter->macopts |= MAC_BCAST;
|
|
|
|
DBG_ERROR("BCAST ");
|
|
|
|
}
|
|
|
|
if (dev->flags & IFF_PROMISC) {
|
|
|
|
adapter->macopts |= MAC_PROMISC;
|
|
|
|
DBG_ERROR("PROMISC ");
|
|
|
|
}
|
|
|
|
if (dev->flags & IFF_ALLMULTI) {
|
|
|
|
adapter->macopts |= MAC_ALLMCAST;
|
|
|
|
DBG_ERROR("ALL_MCAST ");
|
|
|
|
}
|
|
|
|
if (dev->flags & IFF_MULTICAST) {
|
|
|
|
adapter->macopts |= MAC_MCAST;
|
|
|
|
DBG_ERROR("MCAST ");
|
|
|
|
}
|
|
|
|
DBG_ERROR("\n");
|
|
|
|
}
|
|
|
|
status = sxg_register_interrupt(adapter);
|
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
DBG_ERROR("sxg_if_init: sxg_register_interrupt FAILED %x\n",
|
|
|
|
status);
|
|
|
|
sxg_deregister_interrupt(adapter);
|
|
|
|
return (status);
|
|
|
|
}
|
|
|
|
|
|
|
|
adapter->state = ADAPT_UP;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* clear any pending events, then enable interrupts
|
|
|
|
*/
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sxg_entry_open(p_net_device dev)
|
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
|
2008-08-21 21:04:55 +00:00
|
|
|
int status;
|
|
|
|
|
|
|
|
ASSERT(adapter);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s adapter->activated[%d]\n", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->activated);
|
|
|
|
DBG_ERROR
|
|
|
|
("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter->netdev->name, jiffies, smp_processor_id(),
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->netdev, adapter, adapter->port);
|
|
|
|
|
|
|
|
netif_stop_queue(adapter->netdev);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
|
|
|
|
if (!adapter->activated) {
|
|
|
|
sxg_global.num_sxg_ports_active++;
|
|
|
|
adapter->activated = 1;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize the adapter */
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
status = sxg_initialize_adapter(adapter);
|
|
|
|
DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, status);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
if (status == STATUS_SUCCESS) {
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
status = sxg_if_init(adapter);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
status);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
if (adapter->activated) {
|
|
|
|
sxg_global.num_sxg_ports_active--;
|
|
|
|
adapter->activated = 0;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&sxg_global.driver_lock,
|
|
|
|
sxg_global.flags);
|
|
|
|
return (status);
|
|
|
|
}
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Enable interrupts */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_ENABLE_ALL_INTERRUPTS(adapter);
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __devexit sxg_entry_remove(struct pci_dev *pcidev)
|
|
|
|
{
|
|
|
|
p_net_device dev = pci_get_drvdata(pcidev);
|
|
|
|
u32 mmio_start = 0;
|
|
|
|
unsigned int mmio_len = 0;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
ASSERT(adapter);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER dev[%p] adapter[%p]\n", __func__, dev,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter);
|
|
|
|
sxg_deregister_interrupt(adapter);
|
|
|
|
sxg_unmap_mmio_space(adapter);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s unregister_netdev\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
unregister_netdev(dev);
|
|
|
|
|
|
|
|
mmio_start = pci_resource_start(pcidev, 0);
|
|
|
|
mmio_len = pci_resource_len(pcidev, 0);
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
mmio_start, mmio_len);
|
|
|
|
release_mem_region(mmio_start, mmio_len);
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s iounmap dev->base_addr[%x]\n", __func__,
|
2008-10-06 00:38:52 +00:00
|
|
|
(unsigned int)dev->base_addr);
|
2008-08-21 21:04:55 +00:00
|
|
|
iounmap((char *)dev->base_addr);
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s deallocate device\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
kfree(dev);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int sxg_entry_halt(p_net_device dev)
|
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&sxg_global.driver_lock, sxg_global.flags);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s (%s) ENTER\n", __func__, dev->name);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
netif_stop_queue(adapter->netdev);
|
|
|
|
adapter->state = ADAPT_DOWN;
|
|
|
|
adapter->linkstate = LINK_DOWN;
|
|
|
|
adapter->devflags_prev = 0;
|
|
|
|
DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, dev->name, adapter, adapter->state);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s (%s) EXIT\n", __func__, dev->name);
|
|
|
|
DBG_ERROR("sxg: %s EXIT\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_unlock_irqrestore(&sxg_global.driver_lock, sxg_global.flags);
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sxg_ioctl(p_net_device dev, struct ifreq *rq, int cmd)
|
|
|
|
{
|
|
|
|
ASSERT(rq);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __func__, cmd, rq, dev); */
|
2008-08-21 21:04:55 +00:00
|
|
|
switch (cmd) {
|
|
|
|
case SIOCSLICSETINTAGG:
|
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
/* struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev); */
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 data[7];
|
|
|
|
u32 intagg;
|
|
|
|
|
|
|
|
if (copy_from_user(data, rq->ifr_data, 28)) {
|
|
|
|
DBG_ERROR
|
|
|
|
("copy_from_user FAILED getting initial params\n");
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
intagg = data[0];
|
|
|
|
printk(KERN_EMERG
|
|
|
|
"%s: set interrupt aggregation to %d\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, intagg);
|
2008-08-21 21:04:55 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
default:
|
2008-10-20 23:28:58 +00:00
|
|
|
/* DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __func__, cmd); */
|
2008-08-21 21:04:55 +00:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define NORMAL_ETHFRAME 0
|
|
|
|
|
|
|
|
/*
|
|
|
|
*
|
|
|
|
* sxg_send_packets - Send a skb packet
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
* skb - The packet to send
|
|
|
|
* dev - Our linux net device that refs our adapter
|
|
|
|
*
|
|
|
|
* Return:
|
|
|
|
* 0 regardless of outcome XXXTODO refer to e1000 driver
|
|
|
|
*/
|
|
|
|
static int sxg_send_packets(struct sk_buff *skb, p_net_device dev)
|
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 status = STATUS_SUCCESS;
|
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
//DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __FUNCTION__,
|
|
|
|
// skb);
|
|
|
|
printk("ASK:sxg_send_packets: skb[%p]\n", skb);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Check the adapter state */
|
2008-08-21 21:04:55 +00:00
|
|
|
switch (adapter->State) {
|
|
|
|
case SXG_STATE_INITIALIZING:
|
|
|
|
case SXG_STATE_HALTED:
|
|
|
|
case SXG_STATE_SHUTDOWN:
|
2008-10-20 23:28:58 +00:00
|
|
|
ASSERT(0); /* unexpected */
|
|
|
|
/* fall through */
|
2008-08-21 21:04:55 +00:00
|
|
|
case SXG_STATE_RESETTING:
|
|
|
|
case SXG_STATE_SLEEP:
|
|
|
|
case SXG_STATE_BOOTDIAG:
|
|
|
|
case SXG_STATE_DIAG:
|
|
|
|
case SXG_STATE_HALTING:
|
|
|
|
status = STATUS_FAILURE;
|
|
|
|
break;
|
|
|
|
case SXG_STATE_RUNNING:
|
|
|
|
if (adapter->LinkState != SXG_LINK_UP) {
|
|
|
|
status = STATUS_FAILURE;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ASSERT(0);
|
|
|
|
status = STATUS_FAILURE;
|
|
|
|
}
|
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
goto xmit_fail;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* send a packet */
|
2008-08-21 21:04:55 +00:00
|
|
|
status = sxg_transmit_packet(adapter, skb);
|
|
|
|
if (status == STATUS_SUCCESS) {
|
|
|
|
goto xmit_done;
|
|
|
|
}
|
|
|
|
|
|
|
|
xmit_fail:
|
2008-10-20 23:28:58 +00:00
|
|
|
/* reject & complete all the packets if they cant be sent */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
#if XXXTODO
|
2008-10-20 23:28:58 +00:00
|
|
|
/* sxg_send_packets_fail(adapter, skb, status); */
|
2008-08-21 21:04:55 +00:00
|
|
|
#else
|
|
|
|
SXG_DROP_DUMB_SEND(adapter, skb);
|
|
|
|
adapter->stats.tx_dropped++;
|
|
|
|
#endif
|
|
|
|
}
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
status);
|
|
|
|
|
|
|
|
xmit_done:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_transmit_packet
|
|
|
|
*
|
|
|
|
* This function transmits a single packet.
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - Pointer to our adapter structure
|
|
|
|
* skb - The packet to be sent
|
|
|
|
*
|
|
|
|
* Return -
|
|
|
|
* STATUS of send
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_transmit_packet(struct adapter_t *adapter, struct sk_buff *skb)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2009-01-05 15:43:23 +00:00
|
|
|
struct SXG_X64_SGL *pSgl;
|
|
|
|
struct SXG_SCATTER_GATHER *SxgSgl;
|
2008-10-06 00:38:52 +00:00
|
|
|
void *SglBuffer;
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 SglBufferLength;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* The vast majority of work is done in the shared */
|
|
|
|
/* sxg_dumb_sgl routine. */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSend",
|
|
|
|
adapter, skb, 0, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Allocate a SGL buffer */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_GET_SGL_BUFFER(adapter, SxgSgl);
|
|
|
|
if (!SxgSgl) {
|
|
|
|
adapter->Stats.NoSglBuf++;
|
|
|
|
adapter->Stats.XmtErrors++;
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "SndPktF1",
|
|
|
|
adapter, skb, 0, 0);
|
|
|
|
return (STATUS_RESOURCES);
|
|
|
|
}
|
|
|
|
ASSERT(SxgSgl->adapter == adapter);
|
|
|
|
SglBuffer = SXG_SGL_BUFFER(SxgSgl);
|
|
|
|
SglBufferLength = SXG_SGL_BUF_SIZE;
|
|
|
|
SxgSgl->VlanTag.VlanTci = 0;
|
|
|
|
SxgSgl->VlanTag.VlanTpid = 0;
|
|
|
|
SxgSgl->Type = SXG_SGL_DUMB;
|
|
|
|
SxgSgl->DumbPacket = skb;
|
|
|
|
pSgl = NULL;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Call the common sxg_dumb_sgl routine to complete the send. */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_dumb_sgl(pSgl, SxgSgl);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Return success sxg_dumb_sgl (or something later) will complete it. */
|
2008-08-21 21:04:55 +00:00
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_dumb_sgl
|
|
|
|
*
|
|
|
|
* Arguments:
|
|
|
|
* pSgl -
|
|
|
|
* SxgSgl - SXG_SCATTER_GATHER
|
|
|
|
*
|
|
|
|
* Return Value:
|
|
|
|
* None.
|
|
|
|
*/
|
2009-01-05 15:43:23 +00:00
|
|
|
static void sxg_dumb_sgl(struct SXG_X64_SGL *pSgl, struct SXG_SCATTER_GATHER *SxgSgl)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = SxgSgl->adapter;
|
2008-08-21 21:04:55 +00:00
|
|
|
struct sk_buff *skb = SxgSgl->DumbPacket;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* For now, all dumb-nic sends go on RSS queue zero */
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_XMT_RING *XmtRing = &adapter->XmtRings[0];
|
|
|
|
struct SXG_RING_INFO *XmtRingInfo = &adapter->XmtRingZeroInfo;
|
|
|
|
struct SXG_CMD *XmtCmd = NULL;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* u32 Index = 0; */
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 DataLength = skb->len;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* unsigned int BufLen; */
|
|
|
|
/* u32 SglOffset; */
|
2008-08-21 21:04:55 +00:00
|
|
|
u64 phys_addr;
|
2009-01-05 15:43:23 +00:00
|
|
|
unsigned char*data;
|
|
|
|
int i;
|
|
|
|
char dstr[128];
|
|
|
|
char *dptr = dstr;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbSgl",
|
|
|
|
pSgl, SxgSgl, 0, 0);
|
2009-01-05 15:43:23 +00:00
|
|
|
data = skb->data;
|
|
|
|
for (i = 0; i < 32; i++)
|
|
|
|
dptr += sprintf(dptr, "%02x ", (unsigned)data[i]);
|
|
|
|
printk("ASK:sxg_dumb_sgl: data %s\n", dstr);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set aside a pointer to the sgl */
|
2008-08-21 21:04:55 +00:00
|
|
|
SxgSgl->pSgl = pSgl;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Sanity check that our SGL format is as we expect. */
|
2009-01-05 15:43:23 +00:00
|
|
|
ASSERT(sizeof(struct SXG_X64_SGE) == sizeof(struct SXG_X64_SGE));
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Shouldn't be a vlan tag on this frame */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT(SxgSgl->VlanTag.VlanTci == 0);
|
|
|
|
ASSERT(SxgSgl->VlanTag.VlanTpid == 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* From here below we work with the SGL placed in our */
|
|
|
|
/* buffer. */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SxgSgl->Sgl.NumberOfElements = 1;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Grab the spinlock and acquire a command */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock(&adapter->XmtZeroLock);
|
|
|
|
SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
|
|
|
|
if (XmtCmd == NULL) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Call sxg_complete_slow_send to see if we can */
|
|
|
|
/* free up any XmtRingZero entries and then try again */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_unlock(&adapter->XmtZeroLock);
|
|
|
|
sxg_complete_slow_send(adapter);
|
|
|
|
spin_lock(&adapter->XmtZeroLock);
|
|
|
|
SXG_GET_CMD(XmtRing, XmtRingInfo, XmtCmd, SxgSgl);
|
|
|
|
if (XmtCmd == NULL) {
|
|
|
|
adapter->Stats.XmtZeroFull++;
|
|
|
|
goto abortcmd;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbCmd",
|
|
|
|
XmtCmd, XmtRingInfo->Head, XmtRingInfo->Tail, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Update stats */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.DumbXmtPkts++;
|
|
|
|
adapter->Stats.DumbXmtBytes += DataLength;
|
2008-10-20 23:28:58 +00:00
|
|
|
#if XXXTODO /* Stats stuff */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (SXG_MULTICAST_PACKET(EtherHdr)) {
|
|
|
|
if (SXG_BROADCAST_PACKET(EtherHdr)) {
|
|
|
|
adapter->Stats.DumbXmtBcastPkts++;
|
|
|
|
adapter->Stats.DumbXmtBcastBytes += DataLength;
|
|
|
|
} else {
|
|
|
|
adapter->Stats.DumbXmtMcastPkts++;
|
|
|
|
adapter->Stats.DumbXmtMcastBytes += DataLength;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
adapter->Stats.DumbXmtUcastPkts++;
|
|
|
|
adapter->Stats.DumbXmtUcastBytes += DataLength;
|
|
|
|
}
|
|
|
|
#endif
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Fill in the command */
|
|
|
|
/* Copy out the first SGE to the command and adjust for offset */
|
2008-10-06 00:38:52 +00:00
|
|
|
phys_addr =
|
|
|
|
pci_map_single(adapter->pcidev, skb->data, skb->len,
|
|
|
|
PCI_DMA_TODEVICE);
|
2009-01-05 15:43:23 +00:00
|
|
|
memset(XmtCmd, '\0', sizeof(*XmtCmd));
|
|
|
|
XmtCmd->Buffer.FirstSgeAddress = phys_addr;
|
2008-08-21 21:04:55 +00:00
|
|
|
XmtCmd->Buffer.FirstSgeLength = DataLength;
|
|
|
|
XmtCmd->Buffer.SgeOffset = 0;
|
|
|
|
XmtCmd->Buffer.TotalLength = DataLength;
|
2009-01-05 15:43:23 +00:00
|
|
|
XmtCmd->SgEntries = 1;
|
2008-08-21 21:04:55 +00:00
|
|
|
XmtCmd->Flags = 0;
|
2009-01-05 15:43:23 +00:00
|
|
|
printk("ASK:sxg_dumb_sgl: wrote to xmit register\n");
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Advance transmit cmd descripter by 1. */
|
|
|
|
/* NOTE - See comments in SxgTcpOutput where we write */
|
|
|
|
/* to the XmtCmd register regarding CPU ID values and/or */
|
|
|
|
/* multiple commands. */
|
|
|
|
/* */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(adapter->UcodeRegs[0].XmtCmd, 1, TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* */
|
|
|
|
adapter->Stats.XmtQLen++; /* Stats within lock */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_unlock(&adapter->XmtZeroLock);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XDumSgl2",
|
|
|
|
XmtCmd, pSgl, SxgSgl, 0);
|
|
|
|
return;
|
|
|
|
|
|
|
|
abortcmd:
|
2008-10-20 23:28:58 +00:00
|
|
|
/* NOTE - Only jump to this label AFTER grabbing the */
|
|
|
|
/* XmtZeroLock, and DO NOT DROP IT between the */
|
|
|
|
/* command allocation and the following abort. */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (XmtCmd) {
|
|
|
|
SXG_ABORT_CMD(XmtRingInfo);
|
|
|
|
}
|
|
|
|
spin_unlock(&adapter->XmtZeroLock);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* failsgl: */
|
|
|
|
/* Jump to this label if failure occurs before the */
|
|
|
|
/* XmtZeroLock is grabbed */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.XmtErrors++;
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "DumSGFal",
|
|
|
|
pSgl, SxgSgl, XmtRingInfo->Head, XmtRingInfo->Tail);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket); /* SxgSgl->DumbPacket is the skb */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************
|
|
|
|
* Link management functions
|
|
|
|
***************************************************************/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_initialize_link - Initialize the link stuff
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* status
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_initialize_link(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_HW_REGS *HwRegs = adapter->HwRegs;
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 Value;
|
|
|
|
u32 ConfigData;
|
|
|
|
u32 MaxFrame;
|
|
|
|
int status;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset PHY and XGXS module */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->LinkStatus, LS_SERDES_POWER_DOWN, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset transmit configuration register */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_RESET, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset receive configuration register */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->RcvConfig, RCV_CONFIG_RESET, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset all MAC modules */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacConfig0, AXGMAC_CFG0_SUB_RESET, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Link address 0 */
|
|
|
|
/* XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f) */
|
|
|
|
/* is stored with the first nibble (0a) in the byte 0 */
|
|
|
|
/* of the Mac address. Possibly reverse? */
|
2009-01-05 15:43:23 +00:00
|
|
|
Value = *(u32 *) adapter->macaddr;
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->LinkAddress0Low, Value, TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* also write the MAC address to the MAC. Endian is reversed. */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAddressLow, ntohl(Value), TRUE);
|
2009-01-05 15:43:23 +00:00
|
|
|
Value = (*(u16 *) & adapter->macaddr[4] & 0x0000FFFF);
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->LinkAddress0High, Value | LINK_ADDRESS_ENABLE, TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* endian swap for the MAC (put high bytes in bits [31:16], swapped) */
|
2008-08-21 21:04:55 +00:00
|
|
|
Value = ntohl(Value);
|
|
|
|
WRITE_REG(HwRegs->MacAddressHigh, Value, TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Link address 1 */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->LinkAddress1Low, 0, TRUE);
|
|
|
|
WRITE_REG(HwRegs->LinkAddress1High, 0, TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Link address 2 */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->LinkAddress2Low, 0, TRUE);
|
|
|
|
WRITE_REG(HwRegs->LinkAddress2High, 0, TRUE);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Link address 3 */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->LinkAddress3Low, 0, TRUE);
|
|
|
|
WRITE_REG(HwRegs->LinkAddress3High, 0, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Enable MAC modules */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacConfig0, 0, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Configure MAC */
|
|
|
|
WRITE_REG(HwRegs->MacConfig1, (AXGMAC_CFG1_XMT_PAUSE | /* Allow sending of pause */
|
|
|
|
AXGMAC_CFG1_XMT_EN | /* Enable XMT */
|
|
|
|
AXGMAC_CFG1_RCV_PAUSE | /* Enable detection of pause */
|
|
|
|
AXGMAC_CFG1_RCV_EN | /* Enable receive */
|
|
|
|
AXGMAC_CFG1_SHORT_ASSERT | /* short frame detection */
|
|
|
|
AXGMAC_CFG1_CHECK_LEN | /* Verify frame length */
|
|
|
|
AXGMAC_CFG1_GEN_FCS | /* Generate FCS */
|
|
|
|
AXGMAC_CFG1_PAD_64), /* Pad frames to 64 bytes */
|
2008-08-21 21:04:55 +00:00
|
|
|
TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set AXGMAC max frame length if jumbo. Not needed for standard MTU */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->JumboEnabled) {
|
|
|
|
WRITE_REG(HwRegs->MacMaxFrameLen, AXGMAC_MAXFRAME_JUMBO, TRUE);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* AMIIM Configuration Register - */
|
|
|
|
/* The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion */
|
|
|
|
/* (bottom bits) of this register is used to determine the */
|
|
|
|
/* MDC frequency as specified in the A-XGMAC Design Document. */
|
|
|
|
/* This value must not be zero. The following value (62 or 0x3E) */
|
|
|
|
/* is based on our MAC transmit clock frequency (MTCLK) of 312.5 MHz. */
|
|
|
|
/* Given a maximum MDIO clock frequency of 2.5 MHz (see the PHY spec), */
|
|
|
|
/* we get: 312.5/(2*(X+1)) < 2.5 ==> X = 62. */
|
|
|
|
/* This value happens to be the default value for this register, */
|
|
|
|
/* so we really don't have to do this. */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Power up and enable PHY and XAUI/XGXS/Serdes logic */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->LinkStatus,
|
|
|
|
(LS_PHY_CLR_RESET |
|
|
|
|
LS_XGXS_ENABLE |
|
|
|
|
LS_XGXS_CTL | LS_PHY_CLK_EN | LS_ATTN_ALARM), TRUE);
|
|
|
|
DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n");
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Per information given by Aeluros, wait 100 ms after removing reset. */
|
|
|
|
/* It's not enough to wait for the self-clearing reset bit in reg 0 to clear. */
|
2008-08-21 21:04:55 +00:00
|
|
|
mdelay(100);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Verify the PHY has come up by checking that the Reset bit has cleared. */
|
|
|
|
status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
|
|
|
|
PHY_PMA_CONTROL1, /* PMA/PMD control register */
|
2008-08-21 21:04:55 +00:00
|
|
|
&Value);
|
2009-01-05 15:43:23 +00:00
|
|
|
DBG_ERROR("After sxg_read_mdio_reg Value[%x] fail=%x\n", Value, (Value & PMA_CONTROL1_RESET));
|
2008-08-21 21:04:55 +00:00
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
return (STATUS_FAILURE);
|
2008-10-20 23:28:58 +00:00
|
|
|
if (Value & PMA_CONTROL1_RESET) /* reset complete if bit is 0 */
|
2008-08-21 21:04:55 +00:00
|
|
|
return (STATUS_FAILURE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* The SERDES should be initialized by now - confirm */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->LinkStatus, Value);
|
2008-10-20 23:28:58 +00:00
|
|
|
if (Value & LS_SERDES_DOWN) /* verify SERDES is initialized */
|
2008-08-21 21:04:55 +00:00
|
|
|
return (STATUS_FAILURE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* The XAUI link should also be up - confirm */
|
|
|
|
if (!(Value & LS_XAUI_LINK_UP)) /* verify XAUI link is up */
|
2008-08-21 21:04:55 +00:00
|
|
|
return (STATUS_FAILURE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize the PHY */
|
2008-08-21 21:04:55 +00:00
|
|
|
status = sxg_phy_init(adapter);
|
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Enable the Link Alarm */
|
|
|
|
status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
|
|
|
|
LASI_CONTROL, /* LASI control register */
|
|
|
|
LASI_CTL_LS_ALARM_ENABLE); /* enable link alarm bit */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* XXXTODO - temporary - verify bit is set */
|
|
|
|
status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
|
|
|
|
LASI_CONTROL, /* LASI control register */
|
2008-08-21 21:04:55 +00:00
|
|
|
&Value);
|
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
if (!(Value & LASI_CTL_LS_ALARM_ENABLE)) {
|
|
|
|
DBG_ERROR("Error! LASI Control Alarm Enable bit not set!\n");
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Enable receive */
|
2008-08-21 21:04:55 +00:00
|
|
|
MaxFrame = adapter->JumboEnabled ? JUMBOMAXFRAME : ETHERMAXFRAME;
|
|
|
|
ConfigData = (RCV_CONFIG_ENABLE |
|
|
|
|
RCV_CONFIG_ENPARSE |
|
|
|
|
RCV_CONFIG_RCVBAD |
|
|
|
|
RCV_CONFIG_RCVPAUSE |
|
|
|
|
RCV_CONFIG_TZIPV6 |
|
|
|
|
RCV_CONFIG_TZIPV4 |
|
|
|
|
RCV_CONFIG_HASH_16 |
|
|
|
|
RCV_CONFIG_SOCKET | RCV_CONFIG_BUFSIZE(MaxFrame));
|
|
|
|
WRITE_REG(HwRegs->RcvConfig, ConfigData, TRUE);
|
|
|
|
|
|
|
|
WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Mark the link as down. We'll get a link event when it comes up. */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_link_state(adapter, SXG_LINK_DOWN);
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInitLnk",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_phy_init - Initialize the PHY
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* status
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_phy_init(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
u32 Value;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct PHY_UCODE *p;
|
2008-08-21 21:04:55 +00:00
|
|
|
int status;
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("ENTER %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Read a register to identify the PHY type */
|
|
|
|
status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
|
|
|
|
0xC205, /* PHY ID register (?) */
|
|
|
|
&Value); /* XXXTODO - add def */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
if (Value == 0x0012) { /* 0x0012 == AEL2005C PHY(?) - XXXTODO - add def */
|
2008-08-21 21:04:55 +00:00
|
|
|
DBG_ERROR
|
|
|
|
("AEL2005C PHY detected. Downloading PHY microcode.\n");
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize AEL2005C PHY and download PHY microcode */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (p = PhyUcode; p->Addr != 0xFFFF; p++) {
|
|
|
|
if (p->Addr == 0) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* if address == 0, data == sleep time in ms */
|
2008-08-21 21:04:55 +00:00
|
|
|
mdelay(p->Data);
|
|
|
|
} else {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* write the given data to the specified address */
|
|
|
|
status = sxg_write_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
|
|
|
|
p->Addr, /* PHY address */
|
|
|
|
p->Data); /* PHY data */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("EXIT %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_link_event - Process a link event notification from the card
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* None
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_link_event(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_HW_REGS *HwRegs = adapter->HwRegs;
|
|
|
|
enum SXG_LINK_STATE LinkState;
|
2008-08-21 21:04:55 +00:00
|
|
|
int status;
|
|
|
|
u32 Value;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "LinkEvnt",
|
|
|
|
adapter, 0, 0, 0);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("ENTER %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Check the Link Status register. We should have a Link Alarm. */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->LinkStatus, Value);
|
|
|
|
if (Value & LS_LINK_ALARM) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* We got a Link Status alarm. First, pause to let the */
|
|
|
|
/* link state settle (it can bounce a number of times) */
|
2008-08-21 21:04:55 +00:00
|
|
|
mdelay(10);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now clear the alarm by reading the LASI status register. */
|
|
|
|
status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
|
|
|
|
LASI_STATUS, /* LASI status register */
|
2008-08-21 21:04:55 +00:00
|
|
|
&Value);
|
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
DBG_ERROR("Error reading LASI Status MDIO register!\n");
|
|
|
|
sxg_link_state(adapter, SXG_LINK_DOWN);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* ASSERT(0); */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
|
|
|
ASSERT(Value & LASI_STATUS_LS_ALARM);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now get and set the link state */
|
2008-08-21 21:04:55 +00:00
|
|
|
LinkState = sxg_get_link_state(adapter);
|
|
|
|
sxg_link_state(adapter, LinkState);
|
|
|
|
DBG_ERROR("SXG: Link Alarm occurred. Link is %s\n",
|
|
|
|
((LinkState == SXG_LINK_UP) ? "UP" : "DOWN"));
|
|
|
|
} else {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* XXXTODO - Assuming Link Attention is only being generated for the */
|
|
|
|
/* Link Alarm pin (and not for a XAUI Link Status change), then it's */
|
|
|
|
/* impossible to get here. Yet we've gotten here twice (under extreme */
|
|
|
|
/* conditions - bouncing the link up and down many times a second). */
|
|
|
|
/* Needs further investigation. */
|
2008-08-21 21:04:55 +00:00
|
|
|
DBG_ERROR("SXG: sxg_link_event: Can't get here!\n");
|
|
|
|
DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* ASSERT(0); */
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("EXIT %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_get_link_state - Determine if the link is up or down
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* Link State
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static enum SXG_LINK_STATE sxg_get_link_state(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
int status;
|
|
|
|
u32 Value;
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("ENTER %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "GetLink",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if */
|
|
|
|
/* the following 3 bits (from 3 different MDIO registers) are all true. */
|
|
|
|
status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PMA, /* PHY PMA/PMD module */
|
|
|
|
PHY_PMA_RCV_DET, /* PMA/PMD Receive Signal Detect register */
|
2008-08-21 21:04:55 +00:00
|
|
|
&Value);
|
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
goto bad;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* If PMA/PMD receive signal detect is 0, then the link is down */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!(Value & PMA_RCV_DETECT))
|
|
|
|
return (SXG_LINK_DOWN);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_PCS, /* PHY PCS module */
|
|
|
|
PHY_PCS_10G_STATUS1, /* PCS 10GBASE-R Status 1 register */
|
2008-08-21 21:04:55 +00:00
|
|
|
&Value);
|
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
goto bad;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* If PCS is not locked to receive blocks, then the link is down */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!(Value & PCS_10B_BLOCK_LOCK))
|
|
|
|
return (SXG_LINK_DOWN);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
status = sxg_read_mdio_reg(adapter, MIIM_DEV_PHY_XS, /* PHY XS module */
|
|
|
|
PHY_XS_LANE_STATUS, /* XS Lane Status register */
|
2008-08-21 21:04:55 +00:00
|
|
|
&Value);
|
|
|
|
if (status != STATUS_SUCCESS)
|
|
|
|
goto bad;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* If XS transmit lanes are not aligned, then the link is down */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!(Value & XS_LANE_ALIGN))
|
|
|
|
return (SXG_LINK_DOWN);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* All 3 bits are true, so the link is up */
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("EXIT %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
return (SXG_LINK_UP);
|
|
|
|
|
|
|
|
bad:
|
2008-10-20 23:28:58 +00:00
|
|
|
/* An error occurred reading an MDIO register. This shouldn't happen. */
|
2008-08-21 21:04:55 +00:00
|
|
|
DBG_ERROR("Error reading an MDIO register!\n");
|
|
|
|
ASSERT(0);
|
|
|
|
return (SXG_LINK_DOWN);
|
|
|
|
}
|
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_indicate_link_state(struct adapter_t *adapter,
|
|
|
|
enum SXG_LINK_STATE LinkState)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
if (adapter->LinkState == SXG_LINK_UP) {
|
|
|
|
DBG_ERROR("%s: LINK now UP, call netif_start_queue\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
netif_start_queue(adapter->netdev);
|
|
|
|
} else {
|
|
|
|
DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
netif_stop_queue(adapter->netdev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_link_state - Set the link state and if necessary, indicate.
|
|
|
|
* This routine the central point of processing for all link state changes.
|
|
|
|
* Nothing else in the driver should alter the link state or perform
|
|
|
|
* link state indications
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* LinkState - The link state
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* None
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_link_state(struct adapter_t *adapter, enum SXG_LINK_STATE LinkState)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "LnkINDCT",
|
|
|
|
adapter, LinkState, adapter->LinkState, adapter->State);
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("ENTER %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Hold the adapter lock during this routine. Maybe move */
|
|
|
|
/* the lock to the caller. */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock(&adapter->AdapterLock);
|
|
|
|
if (LinkState == adapter->LinkState) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Nothing changed.. */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_unlock(&adapter->AdapterLock);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("EXIT #0 %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
return;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Save the adapter state */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->LinkState = LinkState;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Drop the lock and indicate link state */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_unlock(&adapter->AdapterLock);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("EXIT #1 %s\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
sxg_indicate_link_state(adapter, LinkState);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_write_mdio_reg - Write to a register on the MDIO bus
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* DevAddr - MDIO device number being addressed
|
|
|
|
* RegAddr - register address for the specified MDIO device
|
|
|
|
* Value - value to write to the MDIO register
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* status
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_write_mdio_reg(struct adapter_t *adapter,
|
2008-10-06 00:38:52 +00:00
|
|
|
u32 DevAddr, u32 RegAddr, u32 Value)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_HW_REGS *HwRegs = adapter->HwRegs;
|
2008-10-20 23:28:58 +00:00
|
|
|
u32 AddrOp; /* Address operation (written to MIIM field reg) */
|
|
|
|
u32 WriteOp; /* Write operation (written to MIIM field reg) */
|
|
|
|
u32 Cmd; /* Command (written to MIIM command reg) */
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 ValueRead;
|
|
|
|
u32 Timeout;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* DBG_ERROR("ENTER %s\n", __func__); */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Ensure values don't exceed field width */
|
|
|
|
DevAddr &= 0x001F; /* 5-bit field */
|
|
|
|
RegAddr &= 0xFFFF; /* 16-bit field */
|
|
|
|
Value &= 0xFFFF; /* 16-bit field */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set MIIM field register bits for an MIIM address operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
|
|
|
|
(DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
|
|
|
|
(MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
|
|
|
|
(MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set MIIM field register bits for an MIIM write operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
WriteOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
|
|
|
|
(DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
|
|
|
|
(MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
|
|
|
|
(MIIM_OP_WRITE << AXGMAC_AMIIM_FIELD_OP_SHIFT) | Value;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set MIIM command register bits to execute an MIIM command */
|
2008-08-21 21:04:55 +00:00
|
|
|
Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset the command register command bit (in case it's not 0) */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* MIIM write to set the address of the specified MDIO register */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write to MIIM Command Register to execute to address operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Poll AMIIM Indicator register to wait for completion */
|
2008-08-21 21:04:55 +00:00
|
|
|
Timeout = SXG_LINK_TIMEOUT;
|
|
|
|
do {
|
2008-10-20 23:28:58 +00:00
|
|
|
udelay(100); /* Timeout in 100us units */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
|
|
|
|
if (--Timeout == 0) {
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
}
|
|
|
|
} while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset the command register command bit */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* MIIM write to set up an MDIO write operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimField, WriteOp, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write to MIIM Command Register to execute the write operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Poll AMIIM Indicator register to wait for completion */
|
2008-08-21 21:04:55 +00:00
|
|
|
Timeout = SXG_LINK_TIMEOUT;
|
|
|
|
do {
|
2008-10-20 23:28:58 +00:00
|
|
|
udelay(100); /* Timeout in 100us units */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
|
|
|
|
if (--Timeout == 0) {
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
}
|
|
|
|
} while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* DBG_ERROR("EXIT %s\n", __func__); */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_read_mdio_reg - Read a register on the MDIO bus
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* DevAddr - MDIO device number being addressed
|
|
|
|
* RegAddr - register address for the specified MDIO device
|
|
|
|
* pValue - pointer to where to put data read from the MDIO register
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* status
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_read_mdio_reg(struct adapter_t *adapter,
|
2008-10-06 00:38:52 +00:00
|
|
|
u32 DevAddr, u32 RegAddr, u32 *pValue)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_HW_REGS *HwRegs = adapter->HwRegs;
|
2008-10-20 23:28:58 +00:00
|
|
|
u32 AddrOp; /* Address operation (written to MIIM field reg) */
|
|
|
|
u32 ReadOp; /* Read operation (written to MIIM field reg) */
|
|
|
|
u32 Cmd; /* Command (written to MIIM command reg) */
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 ValueRead;
|
|
|
|
u32 Timeout;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "WrtMDIO",
|
|
|
|
adapter, 0, 0, 0);
|
2009-01-05 15:43:23 +00:00
|
|
|
DBG_ERROR("ENTER %s\n", __FUNCTION__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Ensure values don't exceed field width */
|
|
|
|
DevAddr &= 0x001F; /* 5-bit field */
|
|
|
|
RegAddr &= 0xFFFF; /* 16-bit field */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set MIIM field register bits for an MIIM address operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
AddrOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
|
|
|
|
(DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
|
|
|
|
(MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
|
|
|
|
(MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT) | RegAddr;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set MIIM field register bits for an MIIM read operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
ReadOp = (MIIM_PORT_NUM << AXGMAC_AMIIM_FIELD_PORT_SHIFT) |
|
|
|
|
(DevAddr << AXGMAC_AMIIM_FIELD_DEV_SHIFT) |
|
|
|
|
(MIIM_TA_10GB << AXGMAC_AMIIM_FIELD_TA_SHIFT) |
|
|
|
|
(MIIM_OP_READ << AXGMAC_AMIIM_FIELD_OP_SHIFT);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set MIIM command register bits to execute an MIIM command */
|
2008-08-21 21:04:55 +00:00
|
|
|
Cmd = AXGMAC_AMIIM_CMD_START | AXGMAC_AMIIM_CMD_10G_OPERATION;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset the command register command bit (in case it's not 0) */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* MIIM write to set the address of the specified MDIO register */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimField, AddrOp, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write to MIIM Command Register to execute to address operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Poll AMIIM Indicator register to wait for completion */
|
2008-08-21 21:04:55 +00:00
|
|
|
Timeout = SXG_LINK_TIMEOUT;
|
|
|
|
do {
|
2008-10-20 23:28:58 +00:00
|
|
|
udelay(100); /* Timeout in 100us units */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
|
|
|
|
if (--Timeout == 0) {
|
2009-01-05 15:43:23 +00:00
|
|
|
DBG_ERROR("EXIT %s with STATUS_FAILURE 1\n", __FUNCTION__);
|
|
|
|
|
2008-08-21 21:04:55 +00:00
|
|
|
return (STATUS_FAILURE);
|
|
|
|
}
|
|
|
|
} while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Reset the command register command bit */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, 0, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* MIIM write to set up an MDIO register read operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimField, ReadOp, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Write to MIIM Command Register to execute the read operation */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(HwRegs->MacAmiimCmd, Cmd, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Poll AMIIM Indicator register to wait for completion */
|
2008-08-21 21:04:55 +00:00
|
|
|
Timeout = SXG_LINK_TIMEOUT;
|
|
|
|
do {
|
2008-10-20 23:28:58 +00:00
|
|
|
udelay(100); /* Timeout in 100us units */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->MacAmiimIndicator, ValueRead);
|
|
|
|
if (--Timeout == 0) {
|
2009-01-05 15:43:23 +00:00
|
|
|
DBG_ERROR("EXIT %s with STATUS_FAILURE 2\n", __FUNCTION__);
|
|
|
|
|
2008-08-21 21:04:55 +00:00
|
|
|
return (STATUS_FAILURE);
|
|
|
|
}
|
|
|
|
} while (ValueRead & AXGMAC_AMIIM_INDC_BUSY);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Read the MDIO register data back from the field register */
|
2008-08-21 21:04:55 +00:00
|
|
|
READ_REG(HwRegs->MacAmiimField, *pValue);
|
2008-10-20 23:28:58 +00:00
|
|
|
*pValue &= 0xFFFF; /* data is in the lower 16 bits */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2009-01-05 15:43:23 +00:00
|
|
|
DBG_ERROR("EXIT %s\n", __FUNCTION__);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Functions to obtain the CRC corresponding to the destination mac address.
|
|
|
|
* This is a standard ethernet CRC in that it is a 32-bit, reflected CRC using
|
|
|
|
* the polynomial:
|
|
|
|
* x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1.
|
|
|
|
*
|
|
|
|
* After the CRC for the 6 bytes is generated (but before the value is complemented),
|
|
|
|
* we must then transpose the value and return bits 30-23.
|
|
|
|
*
|
|
|
|
*/
|
2008-10-06 00:38:52 +00:00
|
|
|
static u32 sxg_crc_table[256]; /* Table of CRC's for all possible byte values */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Contruct the CRC32 table
|
|
|
|
*/
|
|
|
|
static void sxg_mcast_init_crc32(void)
|
|
|
|
{
|
2008-10-06 00:38:52 +00:00
|
|
|
u32 c; /* CRC shit reg */
|
2008-08-21 21:04:55 +00:00
|
|
|
u32 e = 0; /* Poly X-or pattern */
|
|
|
|
int i; /* counter */
|
|
|
|
int k; /* byte being shifted into crc */
|
|
|
|
|
|
|
|
static int p[] = { 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26 };
|
|
|
|
|
|
|
|
for (i = 0; i < sizeof(p) / sizeof(int); i++) {
|
|
|
|
e |= 1L << (31 - p[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 1; i < 256; i++) {
|
|
|
|
c = i;
|
|
|
|
for (k = 8; k; k--) {
|
|
|
|
c = c & 1 ? (c >> 1) ^ e : c >> 1;
|
|
|
|
}
|
|
|
|
sxg_crc_table[i] = c;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-21 17:41:45 +00:00
|
|
|
static u32 sxg_crc_init; /* Is table initialized */
|
2008-08-21 21:04:55 +00:00
|
|
|
/*
|
|
|
|
* Return the MAC hast as described above.
|
|
|
|
*/
|
|
|
|
static unsigned char sxg_mcast_get_mac_hash(char *macaddr)
|
|
|
|
{
|
|
|
|
u32 crc;
|
|
|
|
char *p;
|
|
|
|
int i;
|
|
|
|
unsigned char machash = 0;
|
|
|
|
|
|
|
|
if (!sxg_crc_init) {
|
|
|
|
sxg_mcast_init_crc32();
|
|
|
|
sxg_crc_init = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
crc = 0xFFFFFFFF; /* Preload shift register, per crc-32 spec */
|
|
|
|
for (i = 0, p = macaddr; i < 6; ++p, ++i) {
|
|
|
|
crc = (crc >> 8) ^ sxg_crc_table[(crc ^ *p) & 0xFF];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return bits 1-8, transposed */
|
|
|
|
for (i = 1; i < 9; i++) {
|
|
|
|
machash |= (((crc >> i) & 1) << (8 - i));
|
|
|
|
}
|
|
|
|
|
|
|
|
return (machash);
|
|
|
|
}
|
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_mcast_set_mask(struct adapter_t *adapter)
|
2008-10-21 17:41:45 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_UCODE_REGS *sxg_regs = adapter->UcodeRegs;
|
2008-10-21 17:41:45 +00:00
|
|
|
|
|
|
|
DBG_ERROR("%s ENTER (%s) macopts[%x] mask[%llx]\n", __func__,
|
|
|
|
adapter->netdev->name, (unsigned int)adapter->MacFilter,
|
|
|
|
adapter->MulticastMask);
|
|
|
|
|
|
|
|
if (adapter->MacFilter & (MAC_ALLMCAST | MAC_PROMISC)) {
|
|
|
|
/* Turn on all multicast addresses. We have to do this for promiscuous
|
|
|
|
* mode as well as ALLMCAST mode. It saves the Microcode from having
|
|
|
|
* to keep state about the MAC configuration.
|
|
|
|
*/
|
|
|
|
/* DBG_ERROR("sxg: %s macopts = MAC_ALLMCAST | MAC_PROMISC\n SLUT MODE!!!\n",__func__); */
|
|
|
|
WRITE_REG(sxg_regs->McastLow, 0xFFFFFFFF, FLUSH);
|
|
|
|
WRITE_REG(sxg_regs->McastHigh, 0xFFFFFFFF, FLUSH);
|
|
|
|
/* DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high 0xFFFFFFFF\n",__func__, adapter->netdev->name); */
|
|
|
|
|
|
|
|
} else {
|
|
|
|
/* Commit our multicast mast to the SLIC by writing to the multicast
|
|
|
|
* address mask registers
|
|
|
|
*/
|
|
|
|
DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n",
|
|
|
|
__func__, adapter->netdev->name,
|
|
|
|
((ulong) (adapter->MulticastMask & 0xFFFFFFFF)),
|
|
|
|
((ulong)
|
|
|
|
((adapter->MulticastMask >> 32) & 0xFFFFFFFF)));
|
|
|
|
|
|
|
|
WRITE_REG(sxg_regs->McastLow,
|
|
|
|
(u32) (adapter->MulticastMask & 0xFFFFFFFF), FLUSH);
|
|
|
|
WRITE_REG(sxg_regs->McastHigh,
|
|
|
|
(u32) ((adapter->
|
|
|
|
MulticastMask >> 32) & 0xFFFFFFFF), FLUSH);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate a mcast_address structure to hold the multicast address.
|
|
|
|
* Link it in.
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_mcast_add_list(struct adapter_t *adapter, char *address)
|
2008-10-21 17:41:45 +00:00
|
|
|
{
|
2009-01-05 15:43:23 +00:00
|
|
|
struct mcast_address_t *mcaddr, *mlist;
|
2008-10-21 17:41:45 +00:00
|
|
|
bool equaladdr;
|
|
|
|
|
|
|
|
/* Check to see if it already exists */
|
|
|
|
mlist = adapter->mcastaddrs;
|
|
|
|
while (mlist) {
|
|
|
|
ETHER_EQ_ADDR(mlist->address, address, equaladdr);
|
|
|
|
if (equaladdr) {
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
mlist = mlist->next;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Doesn't already exist. Allocate a structure to hold it */
|
2009-01-05 15:43:23 +00:00
|
|
|
mcaddr = kmalloc(sizeof(struct mcast_address_t), GFP_ATOMIC);
|
2008-10-21 17:41:45 +00:00
|
|
|
if (mcaddr == NULL)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
memcpy(mcaddr->address, address, 6);
|
|
|
|
|
|
|
|
mcaddr->next = adapter->mcastaddrs;
|
|
|
|
adapter->mcastaddrs = mcaddr;
|
|
|
|
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_mcast_set_bit(struct adapter_t *adapter, char *address)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
unsigned char crcpoly;
|
|
|
|
|
|
|
|
/* Get the CRC polynomial for the mac address */
|
|
|
|
crcpoly = sxg_mcast_get_mac_hash(address);
|
|
|
|
|
|
|
|
/* We only have space on the SLIC for 64 entries. Lop
|
|
|
|
* off the top two bits. (2^6 = 64)
|
|
|
|
*/
|
|
|
|
crcpoly &= 0x3F;
|
|
|
|
|
|
|
|
/* OR in the new bit into our 64 bit mask. */
|
|
|
|
adapter->MulticastMask |= (u64) 1 << crcpoly;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sxg_mcast_set_list(p_net_device dev)
|
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
|
2008-08-21 21:04:55 +00:00
|
|
|
int status = STATUS_SUCCESS;
|
|
|
|
int i;
|
|
|
|
char *addresses;
|
|
|
|
struct dev_mc_list *mc_list = dev->mc_list;
|
|
|
|
int mc_count = dev->mc_count;
|
|
|
|
|
|
|
|
ASSERT(adapter);
|
2009-01-05 15:43:23 +00:00
|
|
|
if (dev->flags & IFF_PROMISC) {
|
|
|
|
adapter->MacFilter |= MAC_PROMISC;
|
|
|
|
}
|
|
|
|
//XXX handle other flags as well
|
|
|
|
sxg_mcast_set_mask(adapter);
|
|
|
|
|
|
|
|
#if 0
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
for (i = 1; i <= mc_count; i++) {
|
2008-10-06 00:38:52 +00:00
|
|
|
addresses = (char *)&mc_list->dmi_addr;
|
2008-08-21 21:04:55 +00:00
|
|
|
if (mc_list->dmi_addrlen == 6) {
|
|
|
|
status = sxg_mcast_add_list(adapter, addresses);
|
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
status = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
sxg_mcast_set_bit(adapter, addresses);
|
|
|
|
mc_list = mc_list->next;
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG_ERROR("%s a->devflags_prev[%x] dev->flags[%x] status[%x]\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter->devflags_prev, dev->flags, status);
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->devflags_prev != dev->flags) {
|
|
|
|
adapter->macopts = MAC_DIRECTED;
|
|
|
|
if (dev->flags) {
|
|
|
|
if (dev->flags & IFF_BROADCAST) {
|
|
|
|
adapter->macopts |= MAC_BCAST;
|
|
|
|
}
|
|
|
|
if (dev->flags & IFF_PROMISC) {
|
|
|
|
adapter->macopts |= MAC_PROMISC;
|
|
|
|
}
|
|
|
|
if (dev->flags & IFF_ALLMULTI) {
|
|
|
|
adapter->macopts |= MAC_ALLMCAST;
|
|
|
|
}
|
|
|
|
if (dev->flags & IFF_MULTICAST) {
|
|
|
|
adapter->macopts |= MAC_MCAST;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
adapter->devflags_prev = dev->flags;
|
|
|
|
DBG_ERROR("%s call sxg_config_set adapter->macopts[%x]\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter->macopts);
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_config_set(adapter, TRUE);
|
|
|
|
} else {
|
|
|
|
if (status == STATUS_SUCCESS) {
|
|
|
|
sxg_mcast_set_mask(adapter);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
2008-10-21 17:41:45 +00:00
|
|
|
#endif
|
2009-01-05 15:43:23 +00:00
|
|
|
}
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_unmap_mmio_space(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
#if LINUX_FREES_ADAPTER_RESOURCES
|
2008-10-20 23:28:58 +00:00
|
|
|
/* if (adapter->Regs) { */
|
|
|
|
/* iounmap(adapter->Regs); */
|
|
|
|
/* } */
|
|
|
|
/* adapter->slic_regs = NULL; */
|
2008-08-21 21:04:55 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#if XXXTODO
|
|
|
|
/*
|
|
|
|
* SxgFreeResources - Free everything allocated in SxgAllocateResources
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* none
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
void SxgFreeResources(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
u32 RssIds, IsrCount;
|
|
|
|
PTCP_OBJECT TcpObject;
|
|
|
|
u32 i;
|
|
|
|
BOOLEAN TimerCancelled;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FreeRes",
|
|
|
|
adapter, adapter->MaxTcbs, 0, 0);
|
|
|
|
|
|
|
|
RssIds = SXG_RSS_CPU_COUNT(adapter);
|
|
|
|
IsrCount = adapter->MsiEnabled ? RssIds : 1;
|
|
|
|
|
|
|
|
if (adapter->BasicAllocations == FALSE) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* No allocations have been made, including spinlocks, */
|
|
|
|
/* or listhead initializations. Return. */
|
2008-08-21 21:04:55 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(IsListEmpty(&adapter->AllRcvBlocks))) {
|
|
|
|
SxgFreeRcvBlocks(adapter);
|
|
|
|
}
|
|
|
|
if (!(IsListEmpty(&adapter->AllSglBuffers))) {
|
|
|
|
SxgFreeSglBuffers(adapter);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Free event queues. */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->EventRings) {
|
|
|
|
pci_free_consistent(adapter->pcidev,
|
2008-10-28 22:42:02 +00:00
|
|
|
sizeof(struct SXG_EVENT_RING) * RssIds,
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->EventRings, adapter->PEventRings);
|
|
|
|
}
|
|
|
|
if (adapter->Isr) {
|
|
|
|
pci_free_consistent(adapter->pcidev,
|
|
|
|
sizeof(u32) * IsrCount,
|
|
|
|
adapter->Isr, adapter->PIsr);
|
|
|
|
}
|
|
|
|
if (adapter->XmtRingZeroIndex) {
|
|
|
|
pci_free_consistent(adapter->pcidev,
|
|
|
|
sizeof(u32),
|
|
|
|
adapter->XmtRingZeroIndex,
|
|
|
|
adapter->PXmtRingZeroIndex);
|
|
|
|
}
|
|
|
|
if (adapter->IndirectionTable) {
|
|
|
|
pci_free_consistent(adapter->pcidev,
|
|
|
|
SXG_MAX_RSS_TABLE_SIZE,
|
|
|
|
adapter->IndirectionTable,
|
|
|
|
adapter->PIndirectionTable);
|
|
|
|
}
|
|
|
|
|
|
|
|
SXG_FREE_PACKET_POOL(adapter->PacketPoolHandle);
|
|
|
|
SXG_FREE_BUFFER_POOL(adapter->BufferPoolHandle);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Unmap register spaces */
|
2008-08-21 21:04:55 +00:00
|
|
|
SxgUnmapResources(adapter);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Deregister DMA */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (adapter->DmaHandle) {
|
|
|
|
SXG_DEREGISTER_DMA(adapter->DmaHandle);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Deregister interrupt */
|
2008-08-21 21:04:55 +00:00
|
|
|
SxgDeregisterInterrupt(adapter);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Possibly free system info (5.2 only) */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RELEASE_SYSTEM_INFO(adapter);
|
|
|
|
|
|
|
|
SxgDiagFreeResources(adapter);
|
|
|
|
|
|
|
|
SxgFreeMCastAddrs(adapter);
|
|
|
|
|
|
|
|
if (SXG_TIMER_ALLOCATED(adapter->ResetTimer)) {
|
|
|
|
SXG_CANCEL_TIMER(adapter->ResetTimer, TimerCancelled);
|
|
|
|
SXG_FREE_TIMER(adapter->ResetTimer);
|
|
|
|
}
|
|
|
|
if (SXG_TIMER_ALLOCATED(adapter->RssTimer)) {
|
|
|
|
SXG_CANCEL_TIMER(adapter->RssTimer, TimerCancelled);
|
|
|
|
SXG_FREE_TIMER(adapter->RssTimer);
|
|
|
|
}
|
|
|
|
if (SXG_TIMER_ALLOCATED(adapter->OffloadTimer)) {
|
|
|
|
SXG_CANCEL_TIMER(adapter->OffloadTimer, TimerCancelled);
|
|
|
|
SXG_FREE_TIMER(adapter->OffloadTimer);
|
|
|
|
}
|
|
|
|
|
|
|
|
adapter->BasicAllocations = FALSE;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFreeRes",
|
|
|
|
adapter, adapter->MaxTcbs, 0, 0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_allocate_complete -
|
|
|
|
*
|
|
|
|
* This routine is called when a memory allocation has completed.
|
|
|
|
*
|
|
|
|
* Arguments -
|
2008-10-28 22:42:02 +00:00
|
|
|
* struct adapter_t * - Our adapter structure
|
2008-08-21 21:04:55 +00:00
|
|
|
* VirtualAddress - Memory virtual address
|
|
|
|
* PhysicalAddress - Memory physical address
|
|
|
|
* Length - Length of memory allocated (or 0)
|
|
|
|
* Context - The type of buffer allocated
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* None.
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_allocate_complete(struct adapter_t *adapter,
|
2008-10-06 00:38:52 +00:00
|
|
|
void *VirtualAddress,
|
|
|
|
dma_addr_t PhysicalAddress,
|
2008-10-28 22:42:02 +00:00
|
|
|
u32 Length, enum SXG_BUFFER_TYPE Context)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocCmp",
|
|
|
|
adapter, VirtualAddress, Length, Context);
|
|
|
|
ASSERT(adapter->AllocationsPending);
|
|
|
|
--adapter->AllocationsPending;
|
|
|
|
|
|
|
|
switch (Context) {
|
|
|
|
|
|
|
|
case SXG_BUFFER_TYPE_RCV:
|
|
|
|
sxg_allocate_rcvblock_complete(adapter,
|
|
|
|
VirtualAddress,
|
|
|
|
PhysicalAddress, Length);
|
|
|
|
break;
|
|
|
|
case SXG_BUFFER_TYPE_SGL:
|
2008-10-28 22:42:02 +00:00
|
|
|
sxg_allocate_sgl_buffer_complete(adapter, (struct SXG_SCATTER_GATHER*)
|
2008-08-21 21:04:55 +00:00
|
|
|
VirtualAddress,
|
|
|
|
PhysicalAddress, Length);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocCmp",
|
|
|
|
adapter, VirtualAddress, Length, Context);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_allocate_buffer_memory - Shared memory allocation routine used for
|
|
|
|
* synchronous and asynchronous buffer allocations
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* Size - block size to allocate
|
|
|
|
* BufferType - Type of buffer to allocate
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* int
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_allocate_buffer_memory(struct adapter_t *adapter,
|
|
|
|
u32 Size, enum SXG_BUFFER_TYPE BufferType)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
int status;
|
2008-10-06 00:38:52 +00:00
|
|
|
void *Buffer;
|
2008-08-21 21:04:55 +00:00
|
|
|
dma_addr_t pBuffer;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AllocMem",
|
|
|
|
adapter, Size, BufferType, 0);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Grab the adapter lock and check the state. */
|
|
|
|
/* If we're in anything other than INITIALIZING or */
|
|
|
|
/* RUNNING state, fail. This is to prevent */
|
|
|
|
/* allocations in an improper driver state */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock(&adapter->AdapterLock);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Increment the AllocationsPending count while holding */
|
|
|
|
/* the lock. Pause processing relies on this */
|
2008-08-21 21:04:55 +00:00
|
|
|
++adapter->AllocationsPending;
|
|
|
|
spin_unlock(&adapter->AdapterLock);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* At initialization time allocate resources synchronously. */
|
2008-08-21 21:04:55 +00:00
|
|
|
Buffer = pci_alloc_consistent(adapter->pcidev, Size, &pBuffer);
|
|
|
|
if (Buffer == NULL) {
|
|
|
|
spin_lock(&adapter->AdapterLock);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Decrement the AllocationsPending count while holding */
|
|
|
|
/* the lock. Pause processing relies on this */
|
2008-08-21 21:04:55 +00:00
|
|
|
--adapter->AllocationsPending;
|
|
|
|
spin_unlock(&adapter->AdapterLock);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlcMemF1",
|
|
|
|
adapter, Size, BufferType, 0);
|
|
|
|
return (STATUS_RESOURCES);
|
|
|
|
}
|
|
|
|
sxg_allocate_complete(adapter, Buffer, pBuffer, Size, BufferType);
|
|
|
|
status = STATUS_SUCCESS;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlocMem",
|
|
|
|
adapter, Size, BufferType, status);
|
|
|
|
return (status);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_allocate_rcvblock_complete - Complete a receive descriptor block allocation
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* RcvBlock - receive block virtual address
|
|
|
|
* PhysicalAddress - Physical address
|
|
|
|
* Length - Memory length
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
*
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_allocate_rcvblock_complete(struct adapter_t *adapter,
|
2008-10-06 00:38:52 +00:00
|
|
|
void *RcvBlock,
|
|
|
|
dma_addr_t PhysicalAddress,
|
|
|
|
u32 Length)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
u32 i;
|
|
|
|
u32 BufferSize = adapter->ReceiveBufferSize;
|
|
|
|
u64 Paddr;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_RCV_BLOCK_HDR *RcvBlockHdr;
|
2008-08-21 21:04:55 +00:00
|
|
|
unsigned char *RcvDataBuffer;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_RCV_DATA_BUFFER_HDR *RcvDataBufferHdr;
|
|
|
|
struct SXG_RCV_DESCRIPTOR_BLOCK *RcvDescriptorBlock;
|
|
|
|
struct SXG_RCV_DESCRIPTOR_BLOCK_HDR *RcvDescriptorBlockHdr;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlRcvBlk",
|
|
|
|
adapter, RcvBlock, Length, 0);
|
|
|
|
if (RcvBlock == NULL) {
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
memset(RcvBlock, 0, Length);
|
|
|
|
ASSERT((BufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
|
|
|
|
(BufferSize == SXG_RCV_JUMBO_BUFFER_SIZE));
|
|
|
|
ASSERT(Length == SXG_RCV_BLOCK_SIZE(BufferSize));
|
2008-10-20 23:28:58 +00:00
|
|
|
/* First, initialize the contained pool of receive data */
|
|
|
|
/* buffers. This initialization requires NBL/NB/MDL allocations, */
|
|
|
|
/* If any of them fail, free the block and return without */
|
|
|
|
/* queueing the shared memory */
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDataBuffer = RcvBlock;
|
|
|
|
#if 0
|
|
|
|
for (i = 0, Paddr = *PhysicalAddress;
|
|
|
|
i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
|
|
|
|
i++, Paddr.LowPart += BufferSize, RcvDataBuffer += BufferSize)
|
|
|
|
#endif
|
|
|
|
for (i = 0, Paddr = PhysicalAddress;
|
|
|
|
i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
|
|
|
|
i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDataBufferHdr =
|
2008-10-28 22:42:02 +00:00
|
|
|
(struct SXG_RCV_DATA_BUFFER_HDR*) (RcvDataBuffer +
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RCV_DATA_BUFFER_HDR_OFFSET
|
|
|
|
(BufferSize));
|
|
|
|
RcvDataBufferHdr->VirtualAddress = RcvDataBuffer;
|
2008-10-20 23:28:58 +00:00
|
|
|
RcvDataBufferHdr->State = SXG_BUFFER_UPSTREAM; /* For FREE macro assertion */
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDataBufferHdr->Size =
|
|
|
|
SXG_RCV_BUFFER_DATA_SIZE(BufferSize);
|
|
|
|
|
|
|
|
SXG_ALLOCATE_RCV_PACKET(adapter, RcvDataBufferHdr);
|
2009-01-05 15:43:23 +00:00
|
|
|
//ASK hardcoded 2048
|
|
|
|
RcvDataBufferHdr->PhysicalAddress = pci_map_single(adapter->pcidev,
|
|
|
|
RcvDataBufferHdr->SxgDumbRcvPacket->data,
|
|
|
|
2048,
|
|
|
|
PCI_DMA_FROMDEVICE);
|
2008-08-21 21:04:55 +00:00
|
|
|
if (RcvDataBufferHdr->SxgDumbRcvPacket == NULL)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Place this entire block of memory on the AllRcvBlocks queue so it can be */
|
|
|
|
/* free later */
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvBlockHdr =
|
2008-10-28 22:42:02 +00:00
|
|
|
(struct SXG_RCV_BLOCK_HDR*) ((unsigned char *)RcvBlock +
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RCV_BLOCK_HDR_OFFSET(BufferSize));
|
|
|
|
RcvBlockHdr->VirtualAddress = RcvBlock;
|
|
|
|
RcvBlockHdr->PhysicalAddress = PhysicalAddress;
|
|
|
|
spin_lock(&adapter->RcvQLock);
|
|
|
|
adapter->AllRcvBlockCount++;
|
|
|
|
InsertTailList(&adapter->AllRcvBlocks, &RcvBlockHdr->AllList);
|
|
|
|
spin_unlock(&adapter->RcvQLock);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now free the contained receive data buffers that we initialized above */
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDataBuffer = RcvBlock;
|
|
|
|
for (i = 0, Paddr = PhysicalAddress;
|
|
|
|
i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
|
|
|
|
i++, Paddr += BufferSize, RcvDataBuffer += BufferSize) {
|
2008-10-28 22:42:02 +00:00
|
|
|
RcvDataBufferHdr = (struct SXG_RCV_DATA_BUFFER_HDR*) (RcvDataBuffer +
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RCV_DATA_BUFFER_HDR_OFFSET
|
|
|
|
(BufferSize));
|
|
|
|
spin_lock(&adapter->RcvQLock);
|
|
|
|
SXG_FREE_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
|
|
|
|
spin_unlock(&adapter->RcvQLock);
|
|
|
|
}
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Locate the descriptor block and put it on a separate free queue */
|
2008-10-06 00:38:52 +00:00
|
|
|
RcvDescriptorBlock =
|
2008-10-28 22:42:02 +00:00
|
|
|
(struct SXG_RCV_DESCRIPTOR_BLOCK*) ((unsigned char *)RcvBlock +
|
2008-10-06 00:38:52 +00:00
|
|
|
SXG_RCV_DESCRIPTOR_BLOCK_OFFSET
|
|
|
|
(BufferSize));
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDescriptorBlockHdr =
|
2008-10-28 22:42:02 +00:00
|
|
|
(struct SXG_RCV_DESCRIPTOR_BLOCK_HDR*) ((unsigned char *)RcvBlock +
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET
|
|
|
|
(BufferSize));
|
|
|
|
RcvDescriptorBlockHdr->VirtualAddress = RcvDescriptorBlock;
|
|
|
|
RcvDescriptorBlockHdr->PhysicalAddress = Paddr;
|
|
|
|
spin_lock(&adapter->RcvQLock);
|
|
|
|
SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter, RcvDescriptorBlockHdr);
|
|
|
|
spin_unlock(&adapter->RcvQLock);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlRBlk",
|
|
|
|
adapter, RcvBlock, Length, 0);
|
|
|
|
return;
|
|
|
|
fail:
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Free any allocated resources */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (RcvBlock) {
|
|
|
|
RcvDataBuffer = RcvBlock;
|
|
|
|
for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK;
|
|
|
|
i++, RcvDataBuffer += BufferSize) {
|
|
|
|
RcvDataBufferHdr =
|
2008-10-28 22:42:02 +00:00
|
|
|
(struct SXG_RCV_DATA_BUFFER_HDR*) (RcvDataBuffer +
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RCV_DATA_BUFFER_HDR_OFFSET
|
|
|
|
(BufferSize));
|
|
|
|
SXG_FREE_RCV_PACKET(RcvDataBufferHdr);
|
|
|
|
}
|
|
|
|
pci_free_consistent(adapter->pcidev,
|
|
|
|
Length, RcvBlock, PhysicalAddress);
|
|
|
|
}
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s: OUT OF RESOURCES\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_IMPORTANT, "RcvAFail",
|
|
|
|
adapter, adapter->FreeRcvBufferCount,
|
|
|
|
adapter->FreeRcvBlockCount, adapter->AllRcvBlockCount);
|
|
|
|
adapter->Stats.NoMem++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_allocate_sgl_buffer_complete - Complete a SGL buffer allocation
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* SxgSgl - SXG_SCATTER_GATHER buffer
|
|
|
|
* PhysicalAddress - Physical address
|
|
|
|
* Length - Memory length
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
*
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_allocate_sgl_buffer_complete(struct adapter_t *adapter,
|
|
|
|
struct SXG_SCATTER_GATHER *SxgSgl,
|
2008-10-06 00:38:52 +00:00
|
|
|
dma_addr_t PhysicalAddress,
|
|
|
|
u32 Length)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "AlSglCmp",
|
|
|
|
adapter, SxgSgl, Length, 0);
|
|
|
|
spin_lock(&adapter->SglQLock);
|
|
|
|
adapter->AllSglBufferCount++;
|
2008-10-28 22:42:02 +00:00
|
|
|
memset(SxgSgl, 0, sizeof(struct SXG_SCATTER_GATHER*));
|
2008-08-21 21:04:55 +00:00
|
|
|
SxgSgl->PhysicalAddress = PhysicalAddress; /* *PhysicalAddress; */
|
2008-10-20 23:28:58 +00:00
|
|
|
SxgSgl->adapter = adapter; /* Initialize backpointer once */
|
2008-08-21 21:04:55 +00:00
|
|
|
InsertTailList(&adapter->AllSglBuffers, &SxgSgl->AllList);
|
|
|
|
spin_unlock(&adapter->SglQLock);
|
|
|
|
SxgSgl->State = SXG_BUFFER_BUSY;
|
|
|
|
SXG_FREE_SGL_BUFFER(adapter, SxgSgl, NULL);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XAlSgl",
|
|
|
|
adapter, SxgSgl, Length, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_adapter_set_hwaddr(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-20 23:28:58 +00:00
|
|
|
/* DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] funct#[%d]\n", __func__, */
|
|
|
|
/* card->config_set, adapter->port, adapter->physport, adapter->functionnumber); */
|
|
|
|
/* */
|
|
|
|
/* sxg_dbg_macaddrs(adapter); */
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-28 22:42:02 +00:00
|
|
|
memcpy(adapter->macaddr, temp_mac_address, sizeof(struct SXG_CONFIG_MAC));
|
2008-10-20 23:28:58 +00:00
|
|
|
/* DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n", __func__); */
|
|
|
|
/* sxg_dbg_macaddrs(adapter); */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (!(adapter->currmacaddr[0] ||
|
|
|
|
adapter->currmacaddr[1] ||
|
|
|
|
adapter->currmacaddr[2] ||
|
|
|
|
adapter->currmacaddr[3] ||
|
|
|
|
adapter->currmacaddr[4] || adapter->currmacaddr[5])) {
|
|
|
|
memcpy(adapter->currmacaddr, adapter->macaddr, 6);
|
|
|
|
}
|
|
|
|
if (adapter->netdev) {
|
|
|
|
memcpy(adapter->netdev->dev_addr, adapter->currmacaddr, 6);
|
2009-01-05 15:43:23 +00:00
|
|
|
memcpy(adapter->netdev->perm_addr, adapter->currmacaddr, 6);
|
2008-08-21 21:04:55 +00:00
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* DBG_ERROR ("%s EXIT port %d\n", __func__, adapter->port); */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_dbg_macaddrs(adapter);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2008-10-21 17:41:45 +00:00
|
|
|
#if XXXTODO
|
2008-10-06 00:38:52 +00:00
|
|
|
static int sxg_mac_set_address(p_net_device dev, void *ptr)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct adapter_t *adapter = (struct adapter_t *) netdev_priv(dev);
|
2008-08-21 21:04:55 +00:00
|
|
|
struct sockaddr *addr = ptr;
|
|
|
|
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("%s ENTER (%s)\n", __func__, adapter->netdev->name);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
if (netif_running(dev)) {
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
if (!adapter) {
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter->netdev->name, adapter->currmacaddr[0],
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->currmacaddr[1], adapter->currmacaddr[2],
|
|
|
|
adapter->currmacaddr[3], adapter->currmacaddr[4],
|
|
|
|
adapter->currmacaddr[5]);
|
|
|
|
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
|
|
|
|
memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
|
|
|
|
DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
|
2008-10-17 21:46:10 +00:00
|
|
|
__func__, adapter->netdev->name, adapter->currmacaddr[0],
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->currmacaddr[1], adapter->currmacaddr[2],
|
|
|
|
adapter->currmacaddr[3], adapter->currmacaddr[4],
|
|
|
|
adapter->currmacaddr[5]);
|
|
|
|
|
|
|
|
sxg_config_set(adapter, TRUE);
|
|
|
|
return 0;
|
|
|
|
}
|
2008-10-21 17:41:45 +00:00
|
|
|
#endif
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
/*****************************************************************************/
|
|
|
|
/************* SXG DRIVER FUNCTIONS (below) ********************************/
|
|
|
|
/*****************************************************************************/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_initialize_adapter - Initialize adapter
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* int
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_initialize_adapter(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
u32 RssIds, IsrCount;
|
|
|
|
u32 i;
|
|
|
|
int status;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitAdpt",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
RssIds = 1; /* XXXTODO SXG_RSS_CPU_COUNT(adapter); */
|
2008-08-21 21:04:55 +00:00
|
|
|
IsrCount = adapter->MsiEnabled ? RssIds : 1;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Sanity check SXG_UCODE_REGS structure definition to */
|
|
|
|
/* make sure the length is correct */
|
2008-10-28 22:42:02 +00:00
|
|
|
ASSERT(sizeof(struct SXG_UCODE_REGS) == SXG_REGISTER_SIZE_PER_CPU);
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Disable interrupts */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_DISABLE_ALL_INTERRUPTS(adapter);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set MTU */
|
2008-08-21 21:04:55 +00:00
|
|
|
ASSERT((adapter->FrameSize == ETHERMAXFRAME) ||
|
|
|
|
(adapter->FrameSize == JUMBOMAXFRAME));
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].LinkMtu, adapter->FrameSize, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set event ring base address and size */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG64(adapter,
|
|
|
|
adapter->UcodeRegs[0].EventBase, adapter->PEventRings, 0);
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].EventSize, EVENT_RING_SIZE, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Per-ISR initialization */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (i = 0; i < IsrCount; i++) {
|
|
|
|
u64 Addr;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Set interrupt status pointer */
|
2008-08-21 21:04:55 +00:00
|
|
|
Addr = adapter->PIsr + (i * sizeof(u32));
|
|
|
|
WRITE_REG64(adapter, adapter->UcodeRegs[i].Isp, Addr, i);
|
|
|
|
}
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* XMT ring zero index */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG64(adapter,
|
|
|
|
adapter->UcodeRegs[0].SPSendIndex,
|
|
|
|
adapter->PXmtRingZeroIndex, 0);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Per-RSS initialization */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (i = 0; i < RssIds; i++) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Release all event ring entries to the Microcode */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(adapter->UcodeRegs[i].EventRelease, EVENT_RING_SIZE,
|
|
|
|
TRUE);
|
|
|
|
}
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Transmit ring base and size */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG64(adapter,
|
|
|
|
adapter->UcodeRegs[0].XmtBase, adapter->PXmtRings, 0);
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].XmtSize, SXG_XMT_RING_SIZE, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Receive ring base and size */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG64(adapter,
|
|
|
|
adapter->UcodeRegs[0].RcvBase, adapter->PRcvRings, 0);
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].RcvSize, SXG_RCV_RING_SIZE, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Populate the card with receive buffers */
|
2008-08-21 21:04:55 +00:00
|
|
|
sxg_stock_rcv_buffers(adapter);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize checksum offload capabilities. At the moment */
|
|
|
|
/* we always enable IP and TCP receive checksums on the card. */
|
|
|
|
/* Depending on the checksum configuration specified by the */
|
|
|
|
/* user, we can choose to report or ignore the checksum */
|
|
|
|
/* information provided by the card. */
|
2008-08-21 21:04:55 +00:00
|
|
|
WRITE_REG(adapter->UcodeRegs[0].ReceiveChecksum,
|
|
|
|
SXG_RCV_TCP_CSUM_ENABLED | SXG_RCV_IP_CSUM_ENABLED, TRUE);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize the MAC, XAUI */
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __func__);
|
2008-08-21 21:04:55 +00:00
|
|
|
status = sxg_initialize_link(adapter);
|
2008-10-17 21:46:10 +00:00
|
|
|
DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __func__,
|
2008-08-21 21:04:55 +00:00
|
|
|
status);
|
|
|
|
if (status != STATUS_SUCCESS) {
|
|
|
|
return (status);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Initialize Dead to FALSE. */
|
|
|
|
/* SlicCheckForHang or SlicDumpThread will take it from here. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Dead = FALSE;
|
|
|
|
adapter->PingOutstanding = FALSE;
|
2009-01-05 15:43:23 +00:00
|
|
|
adapter->State = SXG_STATE_RUNNING;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInit",
|
|
|
|
adapter, 0, 0, 0);
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_fill_descriptor_block - Populate a descriptor block and give it to
|
|
|
|
* the card. The caller should hold the RcvQLock
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* RcvDescriptorBlockHdr - Descriptor block to fill
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* status
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static int sxg_fill_descriptor_block(struct adapter_t *adapter,
|
|
|
|
struct SXG_RCV_DESCRIPTOR_BLOCK_HDR
|
|
|
|
*RcvDescriptorBlockHdr)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
|
|
|
u32 i;
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_RING_INFO *RcvRingInfo = &adapter->RcvRingZeroInfo;
|
|
|
|
struct SXG_RCV_DATA_BUFFER_HDR *RcvDataBufferHdr;
|
|
|
|
struct SXG_RCV_DESCRIPTOR_BLOCK *RcvDescriptorBlock;
|
|
|
|
struct SXG_CMD *RingDescriptorCmd;
|
|
|
|
struct SXG_RCV_RING *RingZero = &adapter->RcvRings[0];
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "FilBlk",
|
|
|
|
adapter, adapter->RcvBuffersOnCard,
|
|
|
|
adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
|
|
|
|
|
|
|
|
ASSERT(RcvDescriptorBlockHdr);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* If we don't have the resources to fill the descriptor block, */
|
|
|
|
/* return failure */
|
2008-08-21 21:04:55 +00:00
|
|
|
if ((adapter->FreeRcvBufferCount < SXG_RCV_DESCRIPTORS_PER_BLOCK) ||
|
|
|
|
SXG_RING_FULL(RcvRingInfo)) {
|
|
|
|
adapter->Stats.NoMem++;
|
|
|
|
return (STATUS_FAILURE);
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Get a ring descriptor command */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_GET_CMD(RingZero,
|
|
|
|
RcvRingInfo, RingDescriptorCmd, RcvDescriptorBlockHdr);
|
|
|
|
ASSERT(RingDescriptorCmd);
|
|
|
|
RcvDescriptorBlockHdr->State = SXG_BUFFER_ONCARD;
|
|
|
|
RcvDescriptorBlock =
|
2008-10-28 22:42:02 +00:00
|
|
|
(struct SXG_RCV_DESCRIPTOR_BLOCK*) RcvDescriptorBlockHdr->VirtualAddress;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Fill in the descriptor block */
|
2008-08-21 21:04:55 +00:00
|
|
|
for (i = 0; i < SXG_RCV_DESCRIPTORS_PER_BLOCK; i++) {
|
|
|
|
SXG_GET_RCV_DATA_BUFFER(adapter, RcvDataBufferHdr);
|
|
|
|
ASSERT(RcvDataBufferHdr);
|
2009-01-05 15:43:23 +00:00
|
|
|
ASSERT(RcvDataBufferHdr->SxgDumbRcvPacket);
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_REINIATIALIZE_PACKET(RcvDataBufferHdr->SxgDumbRcvPacket);
|
|
|
|
RcvDataBufferHdr->State = SXG_BUFFER_ONCARD;
|
2008-10-06 00:38:52 +00:00
|
|
|
RcvDescriptorBlock->Descriptors[i].VirtualAddress =
|
|
|
|
(void *)RcvDataBufferHdr;
|
2009-01-05 15:43:23 +00:00
|
|
|
if (i == 0)
|
|
|
|
printk("ASK:sxg_fill_descriptor_block: first virt address %p\n", RcvDataBufferHdr);
|
|
|
|
if (i == (SXG_RCV_DESCRIPTORS_PER_BLOCK - 1))
|
|
|
|
printk("ASK:sxg_fill_descriptor_block: last virt address %p\n", RcvDataBufferHdr);
|
|
|
|
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDescriptorBlock->Descriptors[i].PhysicalAddress =
|
|
|
|
RcvDataBufferHdr->PhysicalAddress;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Add the descriptor block to receive descriptor ring 0 */
|
2008-08-21 21:04:55 +00:00
|
|
|
RingDescriptorCmd->Sgl = RcvDescriptorBlockHdr->PhysicalAddress;
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* RcvBuffersOnCard is not protected via the receive lock (see */
|
|
|
|
/* sxg_process_event_queue) We don't want to grap a lock every time a */
|
|
|
|
/* buffer is returned to us, so we use atomic interlocked functions */
|
|
|
|
/* instead. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->RcvBuffersOnCard += SXG_RCV_DESCRIPTORS_PER_BLOCK;
|
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DscBlk",
|
|
|
|
RcvDescriptorBlockHdr,
|
|
|
|
RingDescriptorCmd, RcvRingInfo->Head, RcvRingInfo->Tail);
|
|
|
|
|
|
|
|
WRITE_REG(adapter->UcodeRegs[0].RcvCmd, 1, true);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlk",
|
|
|
|
adapter, adapter->RcvBuffersOnCard,
|
|
|
|
adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
|
|
|
|
return (STATUS_SUCCESS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_stock_rcv_buffers - Stock the card with receive buffers
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* None
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_stock_rcv_buffers(struct adapter_t *adapter)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_RCV_DESCRIPTOR_BLOCK_HDR *RcvDescriptorBlockHdr;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "StockBuf",
|
|
|
|
adapter, adapter->RcvBuffersOnCard,
|
|
|
|
adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* First, see if we've got less than our minimum threshold of */
|
|
|
|
/* receive buffers, there isn't an allocation in progress, and */
|
|
|
|
/* we haven't exceeded our maximum.. get another block of buffers */
|
|
|
|
/* None of this needs to be SMP safe. It's round numbers. */
|
2008-08-21 21:04:55 +00:00
|
|
|
if ((adapter->FreeRcvBufferCount < SXG_MIN_RCV_DATA_BUFFERS) &&
|
|
|
|
(adapter->AllRcvBlockCount < SXG_MAX_RCV_BLOCKS) &&
|
|
|
|
(adapter->AllocationsPending == 0)) {
|
|
|
|
sxg_allocate_buffer_memory(adapter,
|
|
|
|
SXG_RCV_BLOCK_SIZE(adapter->
|
|
|
|
ReceiveBufferSize),
|
|
|
|
SXG_BUFFER_TYPE_RCV);
|
|
|
|
}
|
2009-01-05 15:43:23 +00:00
|
|
|
printk("ASK:sxg_stock_rcv_buffers: RcvBuffersOnCard %d\n", adapter->RcvBuffersOnCard);
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now grab the RcvQLock lock and proceed */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock(&adapter->RcvQLock);
|
|
|
|
while (adapter->RcvBuffersOnCard < SXG_RCV_DATA_BUFFERS) {
|
2008-10-28 22:42:02 +00:00
|
|
|
struct LIST_ENTRY *_ple;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Get a descriptor block */
|
2008-08-21 21:04:55 +00:00
|
|
|
RcvDescriptorBlockHdr = NULL;
|
|
|
|
if (adapter->FreeRcvBlockCount) {
|
|
|
|
_ple = RemoveHeadList(&adapter->FreeRcvBlocks);
|
2008-10-06 00:38:52 +00:00
|
|
|
RcvDescriptorBlockHdr =
|
2008-10-28 22:42:02 +00:00
|
|
|
container_of(_ple, struct SXG_RCV_DESCRIPTOR_BLOCK_HDR,
|
2008-10-06 00:38:52 +00:00
|
|
|
FreeList);
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->FreeRcvBlockCount--;
|
|
|
|
RcvDescriptorBlockHdr->State = SXG_BUFFER_BUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (RcvDescriptorBlockHdr == NULL) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Bail out.. */
|
2008-08-21 21:04:55 +00:00
|
|
|
adapter->Stats.NoMem++;
|
|
|
|
break;
|
|
|
|
}
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Fill in the descriptor block and give it to the card */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
|
|
|
|
STATUS_FAILURE) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Free the descriptor block */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
|
|
|
|
RcvDescriptorBlockHdr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock(&adapter->RcvQLock);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XFilBlks",
|
|
|
|
adapter, adapter->RcvBuffersOnCard,
|
|
|
|
adapter->FreeRcvBufferCount, adapter->AllRcvBlockCount);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* sxg_complete_descriptor_blocks - Return descriptor blocks that have been
|
|
|
|
* completed by the microcode
|
|
|
|
*
|
|
|
|
* Arguments -
|
|
|
|
* adapter - A pointer to our adapter structure
|
|
|
|
* Index - Where the microcode is up to
|
|
|
|
*
|
|
|
|
* Return
|
|
|
|
* None
|
|
|
|
*/
|
2008-10-28 22:42:02 +00:00
|
|
|
static void sxg_complete_descriptor_blocks(struct adapter_t *adapter,
|
2008-10-06 00:38:52 +00:00
|
|
|
unsigned char Index)
|
2008-08-21 21:04:55 +00:00
|
|
|
{
|
2008-10-28 22:42:02 +00:00
|
|
|
struct SXG_RCV_RING *RingZero = &adapter->RcvRings[0];
|
|
|
|
struct SXG_RING_INFO *RcvRingInfo = &adapter->RcvRingZeroInfo;
|
|
|
|
struct SXG_RCV_DESCRIPTOR_BLOCK_HDR *RcvDescriptorBlockHdr;
|
|
|
|
struct SXG_CMD *RingDescriptorCmd;
|
2008-08-21 21:04:55 +00:00
|
|
|
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlks",
|
|
|
|
adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Now grab the RcvQLock lock and proceed */
|
2008-08-21 21:04:55 +00:00
|
|
|
spin_lock(&adapter->RcvQLock);
|
|
|
|
ASSERT(Index != RcvRingInfo->Tail);
|
|
|
|
while (RcvRingInfo->Tail != Index) {
|
2008-10-20 23:28:58 +00:00
|
|
|
/* */
|
|
|
|
/* Locate the current Cmd (ring descriptor entry), and */
|
|
|
|
/* associated receive descriptor block, and advance */
|
|
|
|
/* the tail */
|
|
|
|
/* */
|
2008-08-21 21:04:55 +00:00
|
|
|
SXG_RETURN_CMD(RingZero,
|
|
|
|
RcvRingInfo,
|
|
|
|
RingDescriptorCmd, RcvDescriptorBlockHdr);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "CmpRBlk",
|
|
|
|
RcvRingInfo->Head, RcvRingInfo->Tail,
|
|
|
|
RingDescriptorCmd, RcvDescriptorBlockHdr);
|
|
|
|
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Clear the SGL field */
|
2008-08-21 21:04:55 +00:00
|
|
|
RingDescriptorCmd->Sgl = 0;
|
2008-10-20 23:28:58 +00:00
|
|
|
/* Attempt to refill it and hand it right back to the */
|
|
|
|
/* card. If we fail to refill it, free the descriptor block */
|
|
|
|
/* header. The card will be restocked later via the */
|
|
|
|
/* RcvBuffersOnCard test */
|
2008-08-21 21:04:55 +00:00
|
|
|
if (sxg_fill_descriptor_block(adapter, RcvDescriptorBlockHdr) ==
|
|
|
|
STATUS_FAILURE) {
|
|
|
|
SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter,
|
|
|
|
RcvDescriptorBlockHdr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock(&adapter->RcvQLock);
|
|
|
|
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XCRBlks",
|
|
|
|
adapter, Index, RcvRingInfo->Head, RcvRingInfo->Tail);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_driver sxg_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = sxg_pci_tbl,
|
|
|
|
.probe = sxg_entry_probe,
|
|
|
|
.remove = sxg_entry_remove,
|
|
|
|
#if SXG_POWER_MANAGEMENT_ENABLED
|
|
|
|
.suspend = sxgpm_suspend,
|
|
|
|
.resume = sxgpm_resume,
|
|
|
|
#endif
|
|
|
|
/* .shutdown = slic_shutdown, MOOK_INVESTIGATE */
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init sxg_module_init(void)
|
|
|
|
{
|
|
|
|
sxg_init_driver();
|
|
|
|
|
|
|
|
if (debug >= 0)
|
|
|
|
sxg_debug = debug;
|
|
|
|
|
|
|
|
return pci_register_driver(&sxg_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit sxg_module_cleanup(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&sxg_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(sxg_module_init);
|
|
|
|
module_exit(sxg_module_cleanup);
|