Mock Version: 2.15
Mock Version: 2.15
Mock Version: 2.15
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target riscv64 --nodeps /builddir/build/SPECS/yosys.spec'], chrootPath='/var/lib/mock/f40-build-769274-125504/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0x3f8d6adc10>timeout=604800uid=991gid=135user='mockbuild'nspawn_args=[]unshare_net=TrueprintOutput=False)
Executing command: ['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target riscv64 --nodeps /builddir/build/SPECS/yosys.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'} and shell False
Building target platforms: riscv64
Building for target riscv64
setting SOURCE_DATE_EPOCH=1702857600
Wrote: /builddir/build/SRPMS/yosys-0.36-1.20231218gitd87bd7c.fc40.src.rpm
Child return code was: 0
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target riscv64 --nodeps /builddir/build/SPECS/yosys.spec'], chrootPath='/var/lib/mock/f40-build-769274-125504/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0x3f8d6adc10>timeout=604800uid=991gid=135user='mockbuild'nspawn_args=[]unshare_net=TrueprintOutput=False)
Executing command: ['bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target riscv64 --nodeps /builddir/build/SPECS/yosys.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'} and shell False
Building target platforms: riscv64
Building for target riscv64
setting SOURCE_DATE_EPOCH=1702857600
Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.sAsvPv
+ umask 022
+ cd /builddir/build/BUILD
+ cd /builddir/build/BUILD
+ rm -rf yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ /usr/lib/rpm/rpmuncompress -x /builddir/build/SOURCES/yosys-d87bd7c.tar.gz
+ STATUS=0
+ '[' 0 -ne 0 ']'
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ rm -rf /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544-SPECPARTS
+ /usr/bin/mkdir -p /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544-SPECPARTS
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
+ echo 'Patch #1 (yosys-cfginc.patch):'
Patch #1 (yosys-cfginc.patch):
+ /usr/bin/patch --no-backup-if-mismatch -f -p1 -b --suffix .cfginc --fuzz=0
patching file Makefile
Hunk #1 succeeded at 791 (offset 1 line).
patching file tests/various/plugin.sh
+ echo 'Patch #2 (yosys-mancfginc.patch):'
Patch #2 (yosys-mancfginc.patch):
+ /usr/bin/patch --no-backup-if-mismatch -f -p1 -b --suffix .mancfginc --fuzz=0
patching file manual/PRESENTATION_Prog.tex
patching file manual/PRESENTATION_Prog/Makefile
+ cp /builddir/build/SOURCES/viz.js .
+ cd /builddir/build/BUILD
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ rm -rf /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544-SPECPARTS
+ /usr/bin/mkdir -p /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544-SPECPARTS
+ /usr/lib/rpm/rpmuncompress -x /builddir/build/SOURCES/yosys_0.9-1.debian.tar.xz
+ STATUS=0
+ '[' 0 -ne 0 ']'
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
++ find . -name '*.py'
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/tools/txt2tikztiming.py
+ touch -r ./tests/tools/txt2tikztiming.py ./tests/tools/txt2tikztiming.py.new
+ mv ./tests/tools/txt2tikztiming.py.new ./tests/tools/txt2tikztiming.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/bram/generate.py
+ touch -r ./tests/bram/generate.py ./tests/bram/generate.py.new
+ mv ./tests/bram/generate.py.new ./tests/bram/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/opt_share/generate.py
+ touch -r ./tests/opt_share/generate.py ./tests/opt_share/generate.py.new
+ mv ./tests/opt_share/generate.py.new ./tests/opt_share/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/rpc/frontend.py
+ touch -r ./tests/rpc/frontend.py ./tests/rpc/frontend.py.new
+ mv ./tests/rpc/frontend.py.new ./tests/rpc/frontend.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/xprop/generate.py
+ touch -r ./tests/xprop/generate.py ./tests/xprop/generate.py.new
+ mv ./tests/xprop/generate.py.new ./tests/xprop/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/xprop/test.py
+ touch -r ./tests/xprop/test.py ./tests/xprop/test.py.new
+ mv ./tests/xprop/test.py.new ./tests/xprop/test.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/arch/gatemate/gen_luttrees.py
+ touch -r ./tests/arch/gatemate/gen_luttrees.py ./tests/arch/gatemate/gen_luttrees.py.new
+ mv ./tests/arch/gatemate/gen_luttrees.py.new ./tests/arch/gatemate/gen_luttrees.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py
+ touch -r ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py.new
+ mv ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py.new ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/memlib/generate.py
+ touch -r ./tests/memlib/generate.py ./tests/memlib/generate.py.new
+ mv ./tests/memlib/generate.py.new ./tests/memlib/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/realmath/generate.py
+ touch -r ./tests/realmath/generate.py ./tests/realmath/generate.py.new
+ mv ./tests/realmath/generate.py.new ./tests/realmath/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/share/generate.py
+ touch -r ./tests/share/generate.py ./tests/share/generate.py.new
+ mv ./tests/share/generate.py.new ./tests/share/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/fsm/generate.py
+ touch -r ./tests/fsm/generate.py ./tests/fsm/generate.py.new
+ mv ./tests/fsm/generate.py.new ./tests/fsm/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/source/conf.py
+ touch -r ./docs/source/conf.py ./docs/source/conf.py.new
+ mv ./docs/source/conf.py.new ./docs/source/conf.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/util/RtlilLexer.py
+ touch -r ./docs/util/RtlilLexer.py ./docs/util/RtlilLexer.py.new
+ mv ./docs/util/RtlilLexer.py.new ./docs/util/RtlilLexer.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/util/YoscryptLexer.py
+ touch -r ./docs/util/YoscryptLexer.py ./docs/util/YoscryptLexer.py.new
+ mv ./docs/util/YoscryptLexer.py.new ./docs/util/YoscryptLexer.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./misc/py_wrap_generator.py
+ touch -r ./misc/py_wrap_generator.py ./misc/py_wrap_generator.py.new
+ mv ./misc/py_wrap_generator.py.new ./misc/py_wrap_generator.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./misc/__init__.py
+ touch -r ./misc/__init__.py ./misc/__init__.py.new
+ mv ./misc/__init__.py.new ./misc/__init__.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/gatemate/make_lut_tree_lib.py
+ touch -r ./techlibs/gatemate/make_lut_tree_lib.py ./techlibs/gatemate/make_lut_tree_lib.py.new
+ mv ./techlibs/gatemate/make_lut_tree_lib.py.new ./techlibs/gatemate/make_lut_tree_lib.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/xilinx/cells_xtra.py
+ touch -r ./techlibs/xilinx/cells_xtra.py ./techlibs/xilinx/cells_xtra.py.new
+ mv ./techlibs/xilinx/cells_xtra.py.new ./techlibs/xilinx/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/lattice/cells_xtra.py
+ touch -r ./techlibs/lattice/cells_xtra.py ./techlibs/lattice/cells_xtra.py.new
+ mv ./techlibs/lattice/cells_xtra.py.new ./techlibs/lattice/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/nexus/cells_xtra.py
+ touch -r ./techlibs/nexus/cells_xtra.py ./techlibs/nexus/cells_xtra.py.new
+ mv ./techlibs/nexus/cells_xtra.py.new ./techlibs/nexus/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
+ touch -r ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py.new
+ mv ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py.new ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/gowin/cells_xtra.py
+ touch -r ./techlibs/gowin/cells_xtra.py ./techlibs/gowin/cells_xtra.py.new
+ mv ./techlibs/gowin/cells_xtra.py.new ./techlibs/gowin/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/common/cellhelp.py
+ touch -r ./techlibs/common/cellhelp.py ./techlibs/common/cellhelp.py.new
+ mv ./techlibs/common/cellhelp.py.new ./techlibs/common/cellhelp.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/common/gen_fine_ffs.py
+ touch -r ./techlibs/common/gen_fine_ffs.py ./techlibs/common/gen_fine_ffs.py.new
+ mv ./techlibs/common/gen_fine_ffs.py.new ./techlibs/common/gen_fine_ffs.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/ecp5/tests/test_diamond_ffs.py
+ touch -r ./techlibs/ecp5/tests/test_diamond_ffs.py ./techlibs/ecp5/tests/test_diamond_ffs.py.new
+ mv ./techlibs/ecp5/tests/test_diamond_ffs.py.new ./techlibs/ecp5/tests/test_diamond_ffs.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./examples/python-api/pass.py
+ touch -r ./examples/python-api/pass.py ./examples/python-api/pass.py.new
+ mv ./examples/python-api/pass.py.new ./examples/python-api/pass.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./examples/python-api/script.py
+ touch -r ./examples/python-api/script.py ./examples/python-api/script.py.new
+ mv ./examples/python-api/script.py.new ./examples/python-api/script.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/ywio.py
+ touch -r ./backends/smt2/ywio.py ./backends/smt2/ywio.py.new
+ mv ./backends/smt2/ywio.py.new ./backends/smt2/ywio.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/smtbmc.py
+ touch -r ./backends/smt2/smtbmc.py ./backends/smt2/smtbmc.py.new
+ mv ./backends/smt2/smtbmc.py.new ./backends/smt2/smtbmc.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/smtio.py
+ touch -r ./backends/smt2/smtio.py ./backends/smt2/smtio.py.new
+ mv ./backends/smt2/smtio.py.new ./backends/smt2/smtio.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/smtbmc_incremental.py
+ touch -r ./backends/smt2/smtbmc_incremental.py ./backends/smt2/smtbmc_incremental.py.new
+ mv ./backends/smt2/smtbmc_incremental.py.new ./backends/smt2/smtbmc_incremental.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/witness.py
+ touch -r ./backends/smt2/witness.py ./backends/smt2/witness.py.new
+ mv ./backends/smt2/witness.py.new ./backends/smt2/witness.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/edif/runtest.py
+ touch -r ./backends/edif/runtest.py ./backends/edif/runtest.py.new
+ mv ./backends/edif/runtest.py.new ./backends/edif/runtest.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./passes/pmgen/pmgen.py
+ touch -r ./passes/pmgen/pmgen.py ./passes/pmgen/pmgen.py.new
+ mv ./passes/pmgen/pmgen.py.new ./passes/pmgen/pmgen.py
+ make config-gcc
/bin/sh: line 1: clang: command not found
rm -rf share
rm -rf kernel/*.pyh
rm -f kernel/version_d87bd7ca3fc.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/viz.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/splitcells.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/cmds/xprop.o passes/cmds/dft_tag.o passes/cmds/future.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_rom.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/formalff.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/recover_names.o passes/sat/qbfsat.o passes/sat/synthprop.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/booth.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/bwmuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/intersynth/intersynth.o backends/jny/jny.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/fabulous/synth_fabulous.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/lattice/synth_lattice.o techlibs/lattice/lattice_gsr.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/quicklogic/ql_bram_merge.o techlibs/quicklogic/ql_bram_types.o techlibs/quicklogic/ql_dsp_simd.o techlibs/quicklogic/ql_dsp_io_regs.o techlibs/quicklogic/ql_dsp_macc.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o frontends/rtlil/rtlil_parser.tab.cc frontends/rtlil/rtlil_parser.tab.hh frontends/rtlil/rtlil_parser.output frontends/rtlil/rtlil_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc techlibs/quicklogic/ql_dsp_macc_pm.h techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc yosys-witness share/include/kernel/binding.h share/include/kernel/cellaigs.h share/include/kernel/celledges.h share/include/kernel/celltypes.h share/include/kernel/consteval.h share/include/kernel/constids.inc share/include/kernel/cost.h share/include/kernel/ff.h share/include/kernel/ffinit.h share/include/kernel/ffmerge.h share/include/kernel/fmt.h share/include/kernel/fstdata.h share/include/kernel/hashlib.h share/include/kernel/json.h share/include/kernel/log.h share/include/kernel/macc.h share/include/kernel/modtools.h share/include/kernel/mem.h share/include/kernel/qcsat.h share/include/kernel/register.h share/include/kernel/rtlil.h share/include/kernel/satgen.h share/include/kernel/sigtools.h share/include/kernel/timinginfo.h share/include/kernel/utils.h share/include/kernel/yosys.h share/include/kernel/yw.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/fst/fstapi.h share/include/libs/sha1/sha1.h share/include/libs/json11/json11.hpp share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/frontends/ast/ast_binding.h share/include/frontends/blif/blifparse.h share/include/backends/rtlil/rtlil_backend.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h share/python3/smtio.py share/python3/ywio.py share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/anlogic/cells_map.v share/anlogic/arith_map.v share/anlogic/cells_sim.v share/anlogic/eagle_bb.v share/anlogic/lutrams.txt share/anlogic/lutrams_map.v share/anlogic/brams.txt share/anlogic/brams_map.v share/simlib.v share/simcells.v share/techmap.v share/smtmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/gate2lut.v share/cmp2lut.v share/cells.lib share/mul2dsp.v share/abc9_model.v share/abc9_map.v share/abc9_unmap.v share/cmp2lcu.v share/cmp2softlogic.v share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/cells_counter_map.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/ecp5/cells_ff.vh share/ecp5/cells_io.vh share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/cells_bb.v share/ecp5/lutrams_map.v share/ecp5/lutrams.txt share/ecp5/brams_map.v share/ecp5/brams.txt share/ecp5/arith_map.v share/ecp5/latches_map.v share/ecp5/dsp_map.v share/efinix/cells_map.v share/efinix/arith_map.v share/efinix/cells_sim.v share/efinix/brams_map.v share/efinix/gbuf_map.v share/efinix/brams.txt share/fabulous/cells_map.v share/fabulous/prims.v share/fabulous/latches_map.v share/fabulous/ff_map.v share/fabulous/ram_regfile.txt share/fabulous/regfile_map.v share/fabulous/io_map.v share/fabulous/arith_map.v share/gatemate/reg_map.v share/gatemate/mux_map.v share/gatemate/lut_map.v share/gatemate/mul_map.v share/gatemate/arith_map.v share/gatemate/cells_sim.v share/gatemate/cells_bb.v share/gatemate/brams_map.v share/gatemate/brams.txt share/gatemate/brams_init_20.vh share/gatemate/brams_init_40.vh share/gatemate/inv_map.v share/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_map.v share/gowin/cells_map.v share/gowin/cells_sim.v share/gowin/cells_xtra.v share/gowin/arith_map.v share/gowin/brams_map.v share/gowin/brams.txt share/gowin/lutrams_map.v share/gowin/lutrams.txt share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/ff_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/spram.txt share/ice40/spram_map.v share/ice40/dsp_map.v share/ice40/abc9_model.v share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams_m9k.txt share/intel/common/brams_map_m9k.v share/intel/common/ff_map.v share/intel/max10/cells_sim.v share/intel/cyclone10lp/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/cyclone10lp/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_model.v share/intel_alm/common/alm_map.v share/intel_alm/common/alm_sim.v share/intel_alm/common/arith_alm_map.v share/intel_alm/common/dff_map.v share/intel_alm/common/dff_sim.v share/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_map.v share/intel_alm/common/mem_sim.v share/intel_alm/common/misc_sim.v share/intel_alm/cyclonev/cells_sim.v share/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k_map.v share/intel_alm/common/lutram_mlab.txt share/intel_alm/common/megafunction_bb.v share/intel_alm/common/quartus_rename.v share/lattice/cells_ff.vh share/lattice/cells_io.vh share/lattice/cells_map.v share/lattice/common_sim.vh share/lattice/ccu2d_sim.vh share/lattice/ccu2c_sim.vh share/lattice/cells_sim_ecp5.v share/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3d.v share/lattice/cells_bb_ecp5.v share/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3d.v share/lattice/lutrams_map.v share/lattice/lutrams.txt share/lattice/brams_map_16kd.v share/lattice/brams_16kd.txt share/lattice/brams_map_8kc.v share/lattice/brams_8kc.txt share/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2d.v share/lattice/latches_map.v share/lattice/dsp_map_18x18.v share/nexus/cells_map.v share/nexus/cells_sim.v share/nexus/parse_init.vh share/nexus/cells_xtra.v share/nexus/lutrams_map.v share/nexus/lutrams.txt share/nexus/brams_map.v share/nexus/brams.txt share/nexus/lrams_map.v share/nexus/lrams.txt share/nexus/arith_map.v share/nexus/latches_map.v share/nexus/dsp_map.v share/quicklogic/common/cells_sim.v share/quicklogic/pp3/ffs_map.v share/quicklogic/pp3/lut_map.v share/quicklogic/pp3/latches_map.v share/quicklogic/pp3/cells_map.v share/quicklogic/pp3/cells_sim.v share/quicklogic/pp3/abc9_model.v share/quicklogic/pp3/abc9_map.v share/quicklogic/pp3/abc9_unmap.v share/quicklogic/qlf_k6n10f/arith_map.v share/quicklogic/qlf_k6n10f/libmap_brams.txt share/quicklogic/qlf_k6n10f/libmap_brams_map.v share/quicklogic/qlf_k6n10f/brams_map.v share/quicklogic/qlf_k6n10f/brams_sim.v share/quicklogic/qlf_k6n10f/bram_types_sim.v share/quicklogic/qlf_k6n10f/cells_sim.v share/quicklogic/qlf_k6n10f/ffs_map.v share/quicklogic/qlf_k6n10f/dsp_sim.v share/quicklogic/qlf_k6n10f/dsp_map.v share/quicklogic/qlf_k6n10f/dsp_final_map.v share/quicklogic/qlf_k6n10f/TDP18K_FIFO.v share/quicklogic/qlf_k6n10f/ufifo_ctl.v share/quicklogic/qlf_k6n10f/sram1024x18_mem.v share/sf2/arith_map.v share/sf2/cells_map.v share/sf2/cells_sim.v share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xc5v_map.v share/xilinx/brams_xcv.txt share/xilinx/brams_xcv_map.v share/xilinx/brams_defs.vh share/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v_map.v share/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v_map.v share/xilinx/brams_xc5v_map.v share/xilinx/brams_xc6v_map.v share/xilinx/brams_xcu_map.v share/xilinx/urams.txt share/xilinx/urams_map.v share/xilinx/arith_map.v share/xilinx/ff_map.v share/xilinx/lut_map.v share/xilinx/mux_map.v share/xilinx/xc3s_mult_map.v share/xilinx/xc3sda_dsp_map.v share/xilinx/xc6s_dsp_map.v share/xilinx/xc4v_dsp_map.v share/xilinx/xc5v_dsp_map.v share/xilinx/xc7_dsp_map.v share/xilinx/xcu_dsp_map.v share/xilinx/abc9_model.v passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h passes/techmap/filterlib.o techlibs/gatemate/lut_tree_lib.mk techlibs/quicklogic/ql_dsp_macc_pm.h  .cc
rm -f kernel/version_*.o kernel/version_*.cc
rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d
rm -rf tests/asicworld/*.out tests/asicworld/*.log
rm -rf tests/hana/*.out tests/hana/*.log
rm -rf tests/simple/*.out tests/simple/*.log
rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp
rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log
rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp tests/various/temp
rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_*
rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff
rm -f  tests/tools/cmp_tbdata
make -C docs clean
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/docs'
rm -rf build/*
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/docs'
make -C docs/images clean
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/docs/images'
rm -f *.log
rm -f *.aux
rm -f  011/*.log 011/*.aux
rm -f *.pdf
rm -f *.svg
rm -f 011/*.pdf 011/*.svg
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/docs/images'
rm -rf docs/source/cmd docs/util/__pycache__
echo 'CONFIG := gcc' > Makefile.conf
++ find manual -name '*.tex' -exec grep -l '{luximono}' '{}' ';'
+ for f in `find manual -name \*.tex -exec grep -l {luximono} {} \;`
+ sed -i 's|{luximono}|{libertine}|' manual/presentation.tex
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.uZPqJt
+ umask 022
+ cd /builddir/build/BUILD
+ CFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Werror=implicit-function-declaration -Werror=implicit-int -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CFLAGS
+ CXXFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CXXFLAGS
+ FFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FFLAGS
+ FCFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FCFLAGS
+ VALAFLAGS=-g
+ export VALAFLAGS
+ RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn'
+ export RUSTFLAGS
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ export LDFLAGS
+ LT_SYS_LIBRARY_PATH=/usr/lib64:
+ export LT_SYS_LIBRARY_PATH
+ CC=gcc
+ export CC
+ CXX=g++
+ export CXX
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ CFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Werror=implicit-function-declaration -Werror=implicit-int -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CFLAGS
+ CXXFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CXXFLAGS
+ FFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FFLAGS
+ FCFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FCFLAGS
+ VALAFLAGS=-g
+ export VALAFLAGS
+ RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn'
+ export RUSTFLAGS
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ export LDFLAGS
+ LT_SYS_LIBRARY_PATH=/usr/lib64:
+ export LT_SYS_LIBRARY_PATH
+ CC=gcc
+ export CC
+ CXX=g++
+ export CXX
+ make -j4 PREFIX=/usr ABCEXTERNAL=/usr/bin/abc PRETTY=0 all
[Makefile.conf] CONFIG := gcc
rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc
mkdir -p kernel/
mkdir -p techlibs/common
gcc -o kernel/driver.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc
python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new
mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)\"; }" > kernel/version_d87bd7ca3fc.cc
mkdir -p techlibs/common
python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new
mkdir -p kernel/
gcc -o kernel/rtlil.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc
mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc
mkdir -p kernel/
gcc -o kernel/log.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_SRC='"./"' kernel/log.cc
mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc
mkdir -p kernel/
gcc -o kernel/calc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/calc.cc
mkdir -p kernel/
gcc -o kernel/yosys.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_DATDIR='"/usr/share/yosys"' -DYOSYS_PROGRAM_PREFIX='""' -DABCEXTERNAL='"/usr/bin/abc"' kernel/yosys.cc
mkdir -p kernel/
gcc -o kernel/binding.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/binding.cc
mkdir -p kernel/
gcc -o kernel/cellaigs.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cellaigs.cc
mkdir -p kernel/
gcc -o kernel/celledges.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/celledges.cc
mkdir -p kernel/
gcc -o kernel/satgen.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/satgen.cc
mkdir -p kernel/
gcc -o kernel/qcsat.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/qcsat.cc
mkdir -p kernel/
gcc -o kernel/mem.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/mem.cc
mkdir -p kernel/
gcc -o kernel/ffmerge.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ffmerge.cc
mkdir -p kernel/
gcc -o kernel/ff.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ff.cc
mkdir -p kernel/
gcc -o kernel/yw.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/yw.cc
mkdir -p kernel/
gcc -o kernel/json.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/json.cc
mkdir -p kernel/
gcc -o kernel/fmt.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/fmt.cc
mkdir -p kernel/
gcc -o kernel/fstdata.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/fstdata.cc
mkdir -p libs/bigint/
gcc -o libs/bigint/BigIntegerAlgorithms.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerAlgorithms.cc
mkdir -p libs/bigint/
gcc -o libs/bigint/BigInteger.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigInteger.cc
mkdir -p libs/bigint/
gcc -o libs/bigint/BigIntegerUtils.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerUtils.cc
mkdir -p libs/bigint/
gcc -o libs/bigint/BigUnsigned.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsigned.cc
mkdir -p libs/bigint/
gcc -o libs/bigint/BigUnsignedInABase.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsignedInABase.cc
mkdir -p libs/sha1/
gcc -o libs/sha1/sha1.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/sha1/sha1.cpp
mkdir -p libs/json11/
gcc -o libs/json11/json11.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/json11/json11.cpp
mkdir -p libs/subcircuit/
gcc -o libs/subcircuit/subcircuit.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/subcircuit/subcircuit.cc
mkdir -p libs/ezsat/
gcc -o libs/ezsat/ezsat.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezsat.cc
mkdir -p libs/ezsat/
gcc -o libs/ezsat/ezminisat.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezminisat.cc
mkdir -p libs/minisat/
gcc -o libs/minisat/Options.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Options.cc
mkdir -p libs/minisat/
gcc -o libs/minisat/SimpSolver.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/SimpSolver.cc
In file included from libs/minisat/Sort.h:24,
                 from libs/minisat/SimpSolver.cc:27:
libs/minisat/Vec.h: In instantiation of ‘void Minisat::vec<T, _Size>::capacity(Size) [with T = Minisat::vec<unsigned int>; _Size = int; Size = int]’:
libs/minisat/Vec.h:119:13:   required from ‘void Minisat::vec<T, _Size>::growTo(Size) [with T = Minisat::vec<unsigned int>; _Size = int; Size = int]’
libs/minisat/IntMap.h:48:58:   required from ‘void Minisat::IntMap<K, V, MkIndex>::reserve(K) [with K = int; V = Minisat::vec<unsigned int>; MkIndex = Minisat::MkIndexDefault<int>]’
libs/minisat/SolverTypes.h:338:49:   required from ‘void Minisat::OccLists<K, Vec, Deleted, MkIndex>::init(const K&) [with K = int; Vec = Minisat::vec<unsigned int>; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault<int>]’
libs/minisat/SimpSolver.cc:92:26:   required from here
libs/minisat/Vec.h:103:33: warning: ‘void* realloc(void*, size_t)’ moving an object of non-trivially copyable type ‘class Minisat::vec<unsigned int>’; use ‘new’ and ‘delete’ instead [-Wclass-memaccess]
  103 |     ||   (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) )
      |                        ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
libs/minisat/Vec.h:39:7: note: ‘class Minisat::vec<unsigned int>’ declared here
   39 | class vec {
      |       ^~~
mkdir -p libs/minisat/
gcc -o libs/minisat/Solver.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Solver.cc
In file included from libs/minisat/Alg.h:24,
                 from libs/minisat/Solver.cc:29:
libs/minisat/Vec.h: In instantiation of ‘void Minisat::vec<T, _Size>::capacity(Size) [with T = Minisat::vec<Minisat::Solver::Watcher>; _Size = int; Size = int]’:
libs/minisat/Vec.h:119:13:   required from ‘void Minisat::vec<T, _Size>::growTo(Size) [with T = Minisat::vec<Minisat::Solver::Watcher>; _Size = int; Size = int]’
libs/minisat/IntMap.h:48:58:   required from ‘void Minisat::IntMap<K, V, MkIndex>::reserve(K) [with K = Minisat::Lit; V = Minisat::vec<Minisat::Solver::Watcher>; MkIndex = Minisat::MkIndexLit]’
libs/minisat/SolverTypes.h:338:49:   required from ‘void Minisat::OccLists<K, Vec, Deleted, MkIndex>::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec<Minisat::Solver::Watcher>; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]’
libs/minisat/Solver.cc:134:19:   required from here
libs/minisat/Vec.h:103:33: warning: ‘void* realloc(void*, size_t)’ moving an object of non-trivially copyable type ‘class Minisat::vec<Minisat::Solver::Watcher>’; use ‘new’ and ‘delete’ instead [-Wclass-memaccess]
  103 |     ||   (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) )
      |                        ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
libs/minisat/Vec.h:39:7: note: ‘class Minisat::vec<Minisat::Solver::Watcher>’ declared here
   39 | class vec {
      |       ^~~
mkdir -p libs/minisat/
gcc -o libs/minisat/System.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/System.cc
mkdir -p libs/fst/
gcc -o libs/fst/fstapi.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fstapi.cc
mkdir -p libs/fst/
gcc -o libs/fst/fastlz.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fastlz.cc
mkdir -p libs/fst/
gcc -o libs/fst/lz4.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/lz4.cc
mkdir -p frontends/aiger/
gcc -o frontends/aiger/aigerparse.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/aiger/aigerparse.cc
mkdir -p frontends/ast/
gcc -o frontends/ast/ast.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast.cc
mkdir -p frontends/ast/
gcc -o frontends/ast/simplify.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/simplify.cc
kernel/satgen.cc: In member function ‘bool Yosys::SatGen::importCell(Yosys::RTLIL::Cell*, int)’:
kernel/satgen.cc:1240:67: warning: ‘undef_srst’ may be used uninitialized [-Wmaybe-uninitialized]
 1240 |                                         std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d);
      |                                                                ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
kernel/satgen.cc:1231:37: note: ‘undef_srst’ was declared here
 1231 |                                 int undef_srst;
      |                                     ^~~~~~~~~~
kernel/satgen.cc:1254:67: warning: ‘undef_ce’ may be used uninitialized [-Wmaybe-uninitialized]
 1254 |                                         std::tie(d, undef_d) = mux(ce, undef_ce, d, undef_d, old_q, undef_old_q);
      |                                                                ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
kernel/satgen.cc:1245:37: note: ‘undef_ce’ was declared here
 1245 |                                 int undef_ce;
      |                                     ^~~~~~~~
kernel/satgen.cc:1268:67: warning: ‘undef_srst’ may be used uninitialized [-Wmaybe-uninitialized]
 1268 |                                         std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d);
      |                                                                ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
kernel/satgen.cc:1259:37: note: ‘undef_srst’ was declared here
 1259 |                                 int undef_srst;
      |                                     ^~~~~~~~~~
mkdir -p frontends/ast/
gcc -o frontends/ast/genrtlil.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/genrtlil.cc
mkdir -p frontends/ast/
gcc -o frontends/ast/dpicall.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/dpicall.cc
mkdir -p frontends/ast/
gcc -o frontends/ast/ast_binding.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast_binding.cc
mkdir -p frontends/blif/
gcc -o frontends/blif/blifparse.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/blif/blifparse.cc
mkdir -p frontends/json/
gcc -o frontends/json/jsonparse.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/json/jsonparse.cc
mkdir -p frontends/liberty/
gcc -o frontends/liberty/liberty.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/liberty/liberty.cc
mkdir -p frontends/rpc/
gcc -o frontends/rpc/rpc_frontend.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rpc/rpc_frontend.cc
mkdir -p frontends/rtlil/
bison -o frontends/rtlil/rtlil_parser.tab.cc -d -r all -b frontends/rtlil/rtlil_parser frontends/rtlil/rtlil_parser.y
mkdir -p frontends/rtlil/
flex -o frontends/rtlil/rtlil_lexer.cc frontends/rtlil/rtlil_lexer.l
mkdir -p frontends/rtlil/
gcc -o frontends/rtlil/rtlil_frontend.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_frontend.cc
mkdir -p frontends/verific/
gcc -o frontends/verific/verific.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verific/verific.cc
mkdir -p frontends/verilog/
bison -Wall -Werror -o frontends/verilog/verilog_parser.tab.cc -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y
mkdir -p frontends/verilog/
gcc -o frontends/verilog/preproc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/preproc.cc
mkdir -p frontends/verilog/
gcc -o frontends/verilog/verilog_frontend.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc
mkdir -p frontends/verilog/
gcc -o frontends/verilog/const2ast.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/exec.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/exec.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/add.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/add.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/delete.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/delete.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/design.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/design.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/select.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/select.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/show.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/show.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/viz.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/viz.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/rename.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/rename.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/autoname.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/autoname.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/connect.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connect.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/scatter.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scatter.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/setundef.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setundef.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/splitnets.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitnets.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/splitcells.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitcells.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/stat.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/stat.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/setattr.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setattr.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/copy.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/copy.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/splice.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splice.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/scc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scc.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/glift.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/glift.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/torder.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/torder.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/logcmd.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logcmd.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/tee.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/tee.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/write_file.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/write_file.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/connwrappers.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connwrappers.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/cover.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/cover.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/trace.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/trace.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/plugin.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/plugin.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/check.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/check.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/qwp.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/qwp.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/edgetypes.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/edgetypes.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/portlist.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/portlist.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/chformal.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chformal.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/chtype.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chtype.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/blackbox.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/blackbox.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/ltp.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/ltp.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/bugpoint.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/bugpoint.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/scratchpad.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scratchpad.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/logger.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logger.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/printattrs.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/printattrs.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/sta.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/sta.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/clean_zerowidth.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/clean_zerowidth.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/xprop.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/xprop.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/dft_tag.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/dft_tag.cc
mkdir -p passes/cmds/
gcc -o passes/cmds/future.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/future.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_make.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_make.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_miter.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_miter.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_simple.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_simple.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_status.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_status.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_add.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_add.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_remove.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_remove.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_induct.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_induct.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_struct.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_struct.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_purge.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_purge.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_mark.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_mark.cc
mkdir -p passes/equiv/
gcc -o passes/equiv/equiv_opt.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_opt.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_detect.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_detect.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_extract.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_extract.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_opt.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_opt.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_expand.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_expand.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_recode.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_recode.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_info.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_info.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_export.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_export.cc
mkdir -p passes/fsm/
gcc -o passes/fsm/fsm_map.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_map.cc
mkdir -p passes/hierarchy/
gcc -o passes/hierarchy/hierarchy.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/hierarchy.cc
mkdir -p passes/hierarchy/
gcc -o passes/hierarchy/uniquify.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/uniquify.cc
mkdir -p passes/hierarchy/
gcc -o passes/hierarchy/submod.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/submod.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_dff.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_dff.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_share.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_share.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_collect.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_collect.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_unpack.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_unpack.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_bram.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bram.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_map.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_map.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_memx.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_memx.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_nordff.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_nordff.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_narrow.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_narrow.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_libmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_libmap.cc
mkdir -p passes/memory/
gcc -o passes/memory/memory_bmux2rom.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bmux2rom.cc
mkdir -p passes/memory/
gcc -o passes/memory/memlib.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memlib.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_merge.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_merge.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_mem.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_mem_feedback.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_feedback.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_mem_priority.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_priority.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_mem_widen.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_widen.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_muxtree.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_muxtree.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_reduce.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_reduce.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_dff.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_dff.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_share.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_share.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_clean.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_clean.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_expr.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_expr.cc
mkdir -p passes/opt/
gcc -o passes/opt/share.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/share.cc
mkdir -p passes/opt/
gcc -o passes/opt/wreduce.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/wreduce.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_demorgan.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_demorgan.cc
mkdir -p passes/opt/
gcc -o passes/opt/rmports.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/rmports.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_lut.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_lut_ins.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut_ins.cc
mkdir -p passes/opt/
gcc -o passes/opt/opt_ffinv.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_ffinv.cc
mkdir -p passes/opt/
gcc -o passes/opt/pmux2shiftx.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/pmux2shiftx.cc
mkdir -p passes/opt/
gcc -o passes/opt/muxpack.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/muxpack.cc
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/test_pmgen_pm.h -p test_pmgen passes/pmgen/test_pmgen.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_dsp_pm.h -p ice40_dsp passes/pmgen/ice40_dsp.pmg
mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/peepopt_pm.h -p peepopt passes/pmgen/peepopt_shiftmul_right.pmg passes/pmgen/peepopt_shiftmul_left.pmg passes/pmgen/peepopt_shiftadd.pmg passes/pmgen/peepopt_muldiv.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_srl_pm.h -p xilinx_srl passes/pmgen/xilinx_srl.pmg
mkdir -p passes/pmgen/
gcc -o passes/pmgen/ice40_dsp.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_dsp.cc
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_wrapcarry_pm.h -p ice40_wrapcarry passes/pmgen/ice40_wrapcarry.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_pm.h -p xilinx_dsp passes/pmgen/xilinx_dsp.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp48a_pm.h -p xilinx_dsp48a passes/pmgen/xilinx_dsp48a.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_CREG_pm.h -p xilinx_dsp_CREG passes/pmgen/xilinx_dsp_CREG.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_cascade_pm.h -p xilinx_dsp_cascade passes/pmgen/xilinx_dsp_cascade.pmg
mkdir -p passes/pmgen/
gcc -o passes/pmgen/peepopt.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/peepopt.cc
mkdir -p passes/pmgen/
gcc -o passes/pmgen/xilinx_srl.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_srl.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_prune.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_prune.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_clean.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_clean.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_rmdead.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rmdead.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_init.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_init.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_arst.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_arst.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_rom.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rom.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_mux.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_mux.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_dlatch.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dlatch.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_dff.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dff.cc
mkdir -p passes/proc/
gcc -o passes/proc/proc_memwr.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_memwr.cc
mkdir -p passes/sat/
gcc -o passes/sat/sat.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sat.cc
mkdir -p passes/sat/
gcc -o passes/sat/freduce.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/freduce.cc
mkdir -p passes/sat/
gcc -o passes/sat/eval.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/eval.cc
mkdir -p passes/sat/
gcc -o passes/sat/sim.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sim.cc
mkdir -p passes/sat/
gcc -o passes/sat/miter.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/miter.cc
mkdir -p passes/sat/
gcc -o passes/sat/expose.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/expose.cc
mkdir -p passes/sat/
gcc -o passes/sat/assertpmux.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/assertpmux.cc
mkdir -p passes/sat/
gcc -o passes/sat/clk2fflogic.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/clk2fflogic.cc
mkdir -p passes/sat/
gcc -o passes/sat/async2sync.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/async2sync.cc
mkdir -p passes/sat/
gcc -o passes/sat/formalff.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/formalff.cc
mkdir -p passes/sat/
gcc -o passes/sat/supercover.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/supercover.cc
mkdir -p passes/sat/
gcc -o passes/sat/fmcombine.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fmcombine.cc
mkdir -p passes/sat/
gcc -o passes/sat/mutate.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/mutate.cc
mkdir -p passes/sat/
gcc -o passes/sat/cutpoint.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/cutpoint.cc
mkdir -p passes/sat/
gcc -o passes/sat/fminit.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fminit.cc
mkdir -p passes/sat/
gcc -o passes/sat/recover_names.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/recover_names.cc
mkdir -p passes/sat/
gcc -o passes/sat/qbfsat.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/qbfsat.cc
mkdir -p passes/sat/
gcc -o passes/sat/synthprop.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/synthprop.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/flatten.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flatten.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/techmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/techmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/simplemap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/simplemap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/dfflibmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflibmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/maccmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/maccmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/booth.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/booth.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/libparse.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/libparse.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/abc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"/usr/bin/abc"' passes/techmap/abc.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/abc9.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"/usr/bin/abc"' passes/techmap/abc9.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/abc9_exe.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"/usr/bin/abc"' passes/techmap/abc9_exe.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/abc9_ops.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/abc9_ops.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/iopadmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/iopadmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/clkbufmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/clkbufmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/hilomap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/hilomap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/extract.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/extract_fa.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_fa.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/extract_counter.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_counter.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/extract_reduce.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_reduce.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/alumacc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/alumacc.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/dffinit.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffinit.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/pmuxtree.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/bmuxmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bmuxmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/demuxmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/demuxmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/bwmuxmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bwmuxmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/muxcover.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/muxcover.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/aigmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/aigmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/tribuf.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/tribuf.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/lut2mux.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/lut2mux.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/nlutmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/nlutmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/shregmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/shregmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/deminout.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/deminout.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/insbuf.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/insbuf.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/attrmvcp.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmvcp.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/attrmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/zinit.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/zinit.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/dfflegalize.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflegalize.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/dffunmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffunmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/flowmap.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flowmap.cc
mkdir -p passes/techmap/
gcc -o passes/techmap/extractinv.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extractinv.cc
mkdir -p passes/tests/
gcc -o passes/tests/test_autotb.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_autotb.cc
mkdir -p passes/tests/
gcc -o passes/tests/test_cell.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_cell.cc
mkdir -p passes/tests/
gcc -o passes/tests/test_abcloop.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_abcloop.cc
mkdir -p backends/aiger/
gcc -o backends/aiger/aiger.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/aiger.cc
mkdir -p backends/aiger/
gcc -o backends/aiger/xaiger.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/xaiger.cc
mkdir -p backends/blif/
gcc -o backends/blif/blif.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/blif/blif.cc
mkdir -p backends/btor/
gcc -o backends/btor/btor.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/btor/btor.cc
mkdir -p backends/cxxrtl/
gcc -o backends/cxxrtl/cxxrtl_backend.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/cxxrtl/cxxrtl_backend.cc
mkdir -p backends/edif/
gcc -o backends/edif/edif.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/edif/edif.cc
mkdir -p backends/firrtl/
gcc -o backends/firrtl/firrtl.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/firrtl/firrtl.cc
mkdir -p backends/intersynth/
gcc -o backends/intersynth/intersynth.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/intersynth/intersynth.cc
mkdir -p backends/jny/
gcc -o backends/jny/jny.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/jny/jny.cc
mkdir -p backends/json/
gcc -o backends/json/json.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/json/json.cc
mkdir -p backends/rtlil/
gcc -o backends/rtlil/rtlil_backend.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/rtlil/rtlil_backend.cc
mkdir -p backends/simplec/
gcc -o backends/simplec/simplec.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/simplec/simplec.cc
mkdir -p backends/smt2/
gcc -o backends/smt2/smt2.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smt2/smt2.cc
mkdir -p backends/smv/
gcc -o backends/smv/smv.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smv/smv.cc
mkdir -p backends/spice/
gcc -o backends/spice/spice.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/spice/spice.cc
mkdir -p backends/table/
gcc -o backends/table/table.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/table/table.cc
mkdir -p backends/verilog/
gcc -o backends/verilog/verilog_backend.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/verilog/verilog_backend.cc
mkdir -p techlibs/achronix/
gcc -o techlibs/achronix/synth_achronix.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/achronix/synth_achronix.cc
mkdir -p techlibs/anlogic/
gcc -o techlibs/anlogic/synth_anlogic.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/synth_anlogic.cc
mkdir -p techlibs/anlogic/
gcc -o techlibs/anlogic/anlogic_eqn.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_eqn.cc
mkdir -p techlibs/anlogic/
gcc -o techlibs/anlogic/anlogic_fixcarry.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_fixcarry.cc
mkdir -p techlibs/common/
gcc -o techlibs/common/synth.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/synth.cc
mkdir -p techlibs/common/
gcc -o techlibs/common/prep.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/prep.cc
mkdir -p techlibs/coolrunner2/
gcc -o techlibs/coolrunner2/synth_coolrunner2.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/synth_coolrunner2.cc
mkdir -p techlibs/coolrunner2/
gcc -o techlibs/coolrunner2/coolrunner2_sop.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_sop.cc
mkdir -p techlibs/coolrunner2/
gcc -o techlibs/coolrunner2/coolrunner2_fixup.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_fixup.cc
mkdir -p techlibs/easic/
gcc -o techlibs/easic/synth_easic.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/easic/synth_easic.cc
mkdir -p techlibs/ecp5/
gcc -o techlibs/ecp5/synth_ecp5.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/synth_ecp5.cc
mkdir -p techlibs/efinix/
gcc -o techlibs/efinix/synth_efinix.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/synth_efinix.cc
mkdir -p techlibs/efinix/
gcc -o techlibs/efinix/efinix_fixcarry.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/efinix_fixcarry.cc
mkdir -p techlibs/fabulous/
gcc -o techlibs/fabulous/synth_fabulous.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/fabulous/synth_fabulous.cc
mkdir -p techlibs/gatemate/
gcc -o techlibs/gatemate/synth_gatemate.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gatemate/synth_gatemate.cc
mkdir -p techlibs/gatemate/
gcc -o techlibs/gatemate/gatemate_foldinv.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gatemate/gatemate_foldinv.cc
mkdir -p techlibs/gowin/
gcc -o techlibs/gowin/synth_gowin.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gowin/synth_gowin.cc
mkdir -p techlibs/greenpak4/
gcc -o techlibs/greenpak4/synth_greenpak4.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/synth_greenpak4.cc
mkdir -p techlibs/greenpak4/
gcc -o techlibs/greenpak4/greenpak4_dffinv.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/greenpak4_dffinv.cc
mkdir -p techlibs/ice40/
gcc -o techlibs/ice40/synth_ice40.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/synth_ice40.cc
mkdir -p techlibs/ice40/
gcc -o techlibs/ice40/ice40_braminit.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_braminit.cc
mkdir -p techlibs/ice40/
gcc -o techlibs/ice40/ice40_opt.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_opt.cc
mkdir -p techlibs/intel/
gcc -o techlibs/intel/synth_intel.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel/synth_intel.cc
mkdir -p techlibs/intel_alm/
gcc -o techlibs/intel_alm/synth_intel_alm.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel_alm/synth_intel_alm.cc
mkdir -p techlibs/lattice/
gcc -o techlibs/lattice/synth_lattice.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/lattice/synth_lattice.cc
mkdir -p techlibs/lattice/
gcc -o techlibs/lattice/lattice_gsr.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/lattice/lattice_gsr.cc
mkdir -p techlibs/nexus/
gcc -o techlibs/nexus/synth_nexus.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/nexus/synth_nexus.cc
mkdir -p techlibs/quicklogic/
gcc -o techlibs/quicklogic/synth_quicklogic.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/synth_quicklogic.cc
mkdir -p techlibs/quicklogic/
gcc -o techlibs/quicklogic/ql_bram_merge.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_bram_merge.cc
mkdir -p techlibs/quicklogic/
gcc -o techlibs/quicklogic/ql_bram_types.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_bram_types.cc
mkdir -p techlibs/quicklogic/
gcc -o techlibs/quicklogic/ql_dsp_simd.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_simd.cc
mkdir -p techlibs/quicklogic/
gcc -o techlibs/quicklogic/ql_dsp_io_regs.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_io_regs.cc
mkdir -p techlibs/quicklogic/ && python3 passes/pmgen/pmgen.py -o techlibs/quicklogic/ql_dsp_macc_pm.h -p ql_dsp_macc techlibs/quicklogic/ql_dsp_macc.pmg
mkdir -p techlibs/sf2/
gcc -o techlibs/sf2/synth_sf2.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/sf2/synth_sf2.cc
mkdir -p techlibs/xilinx/
gcc -o techlibs/xilinx/synth_xilinx.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/synth_xilinx.cc
mkdir -p techlibs/xilinx/
gcc -o techlibs/xilinx/xilinx_dffopt.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/xilinx_dffopt.cc
sed -e 's#@CXXFLAGS@#-O2 -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -fasynchronous-unwind-tables -fno-omit-frame-pointer -Wall -Wextra -ggdb -I"/usr/include/yosys" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER#;' \
		-e 's#@CXX@#gcc#;' -e 's#@LDFLAGS@#-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes -rdynamic#;' -e 's#@LDLIBS@#-lstdc++ -lm -lrt -lreadline -L/usr/lib64/../lib64/lp64d -lffi -ldl -lz -ltcl8.6 -ltclstub8.6#;' \
		-e 's#@BINDIR@#/usr/bin#;' -e 's#@DATDIR@#/usr/share/yosys#;' < misc/yosys-config.in > yosys-config
chmod +x yosys-config
mkdir -p passes/techmap/
gcc -o passes/techmap/filterlib.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/filterlib.cc
sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < backends/smt2/smtbmc.py > yosys-smtbmc.new
chmod +x yosys-smtbmc.new
mv yosys-smtbmc.new yosys-smtbmc
sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < backends/smt2/witness.py > yosys-witness.new
chmod +x yosys-witness.new
mv yosys-witness.new yosys-witness
mkdir -p share/include/kernel/
cp "./"/kernel/binding.h share/include/kernel/binding.h
mkdir -p share/include/kernel/
cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h
mkdir -p share/include/kernel/
cp "./"/kernel/celledges.h share/include/kernel/celledges.h
mkdir -p share/include/kernel/
cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h
mkdir -p share/include/kernel/
cp "./"/kernel/consteval.h share/include/kernel/consteval.h
mkdir -p share/include/kernel/
cp "./"/kernel/constids.inc share/include/kernel/constids.inc
mkdir -p share/include/kernel/
cp "./"/kernel/cost.h share/include/kernel/cost.h
mkdir -p share/include/kernel/
cp "./"/kernel/ff.h share/include/kernel/ff.h
mkdir -p share/include/kernel/
cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h
mkdir -p share/include/kernel/
cp "./"/kernel/ffmerge.h share/include/kernel/ffmerge.h
mkdir -p share/include/kernel/
cp "./"/kernel/fmt.h share/include/kernel/fmt.h
mkdir -p share/include/kernel/
cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h
mkdir -p share/include/kernel/
cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h
mkdir -p share/include/kernel/
cp "./"/kernel/json.h share/include/kernel/json.h
mkdir -p share/include/kernel/
cp "./"/kernel/log.h share/include/kernel/log.h
mkdir -p share/include/kernel/
cp "./"/kernel/macc.h share/include/kernel/macc.h
mkdir -p share/include/kernel/
cp "./"/kernel/modtools.h share/include/kernel/modtools.h
mkdir -p share/include/kernel/
cp "./"/kernel/mem.h share/include/kernel/mem.h
mkdir -p share/include/kernel/
cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h
mkdir -p share/include/kernel/
cp "./"/kernel/register.h share/include/kernel/register.h
mkdir -p share/include/kernel/
cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h
mkdir -p share/include/kernel/
cp "./"/kernel/satgen.h share/include/kernel/satgen.h
mkdir -p share/include/kernel/
cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h
mkdir -p share/include/kernel/
cp "./"/kernel/timinginfo.h share/include/kernel/timinginfo.h
mkdir -p share/include/kernel/
cp "./"/kernel/utils.h share/include/kernel/utils.h
mkdir -p share/include/kernel/
cp "./"/kernel/yosys.h share/include/kernel/yosys.h
mkdir -p share/include/kernel/
cp "./"/kernel/yw.h share/include/kernel/yw.h
mkdir -p share/include/libs/ezsat/
cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h
mkdir -p share/include/libs/ezsat/
cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h
mkdir -p share/include/libs/fst/
cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h
mkdir -p share/include/libs/sha1/
cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h
mkdir -p share/include/libs/json11/
cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp
mkdir -p share/include/passes/fsm/
cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h
mkdir -p share/include/frontends/ast/
cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h
mkdir -p share/include/frontends/ast/
cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h
mkdir -p share/include/frontends/blif/
cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h
mkdir -p share/include/backends/rtlil/
cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/
cp "./"/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/
cp "./"/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
mkdir -p share/python3
cp "./"/backends/smt2/smtio.py share/python3/smtio.py
mkdir -p share/python3
cp "./"/backends/smt2/ywio.py share/python3/ywio.py
mkdir -p share/achronix/speedster22i/
cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v
mkdir -p share/achronix/speedster22i/
cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/lutrams.txt share/anlogic/lutrams.txt
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/lutrams_map.v share/anlogic/lutrams_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/brams.txt share/anlogic/brams.txt
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/brams_map.v share/anlogic/brams_map.v
mkdir -p share
cp "./"/techlibs/common/simlib.v share/simlib.v
mkdir -p share
cp "./"/techlibs/common/simcells.v share/simcells.v
mkdir -p share
cp "./"/techlibs/common/techmap.v share/techmap.v
mkdir -p share
cp "./"/techlibs/common/smtmap.v share/smtmap.v
mkdir -p share
cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v
mkdir -p share
cp "./"/techlibs/common/adff2dff.v share/adff2dff.v
mkdir -p share
cp "./"/techlibs/common/dff2ff.v share/dff2ff.v
mkdir -p share
cp "./"/techlibs/common/gate2lut.v share/gate2lut.v
mkdir -p share
cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v
mkdir -p share
cp "./"/techlibs/common/cells.lib share/cells.lib
mkdir -p share
cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v
mkdir -p share
cp "./"/techlibs/common/abc9_model.v share/abc9_model.v
mkdir -p share
cp "./"/techlibs/common/abc9_map.v share/abc9_map.v
mkdir -p share
cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v
mkdir -p share
cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v
mkdir -p share
cp "./"/techlibs/common/cmp2softlogic.v share/cmp2softlogic.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v
mkdir -p techlibs/gatemate
python3 techlibs/gatemate/make_lut_tree_lib.py
touch techlibs/gatemate/lut_tree_lib.mk
mkdir -p share/gowin
cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt
mkdir -p share/gowin
cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib
mkdir -p share/ice40
cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt
mkdir -p share/ice40
cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt
mkdir -p share/ice40
cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v
mkdir -p share/intel/max10
cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v
mkdir -p share/intel/cyclone10lp
cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v
mkdir -p share/intel/cycloneiv
cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v
mkdir -p share/intel/cycloneive
cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v
mkdir -p share/intel/max10
cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v
mkdir -p share/intel/cyclone10lp
cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v
mkdir -p share/intel/cycloneiv
cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v
mkdir -p share/intel/cycloneive
cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v
mkdir -p share/intel_alm/cyclonev
cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt
mkdir -p share/lattice
cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh
mkdir -p share/nexus
cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt
mkdir -p share/nexus
cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt
mkdir -p share/nexus
cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt
mkdir -p share/nexus
cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v
mkdir -p share/quicklogic/common
cp "./"/techlibs/quicklogic/common/cells_sim.v share/quicklogic/common/cells_sim.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/ffs_map.v share/quicklogic/pp3/ffs_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/lut_map.v share/quicklogic/pp3/lut_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/latches_map.v share/quicklogic/pp3/latches_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/cells_map.v share/quicklogic/pp3/cells_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/cells_sim.v share/quicklogic/pp3/cells_sim.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/abc9_model.v share/quicklogic/pp3/abc9_model.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/abc9_map.v share/quicklogic/pp3/abc9_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/abc9_unmap.v share/quicklogic/pp3/abc9_unmap.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/arith_map.v share/quicklogic/qlf_k6n10f/arith_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt share/quicklogic/qlf_k6n10f/libmap_brams.txt
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v share/quicklogic/qlf_k6n10f/libmap_brams_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/brams_map.v share/quicklogic/qlf_k6n10f/brams_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/brams_sim.v share/quicklogic/qlf_k6n10f/brams_sim.v
mkdir -p techlibs/quicklogic/qlf_k6n10f/ && python3 techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/cells_sim.v share/quicklogic/qlf_k6n10f/cells_sim.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/ffs_map.v share/quicklogic/qlf_k6n10f/ffs_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v share/quicklogic/qlf_k6n10f/dsp_sim.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/dsp_map.v share/quicklogic/qlf_k6n10f/dsp_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v share/quicklogic/qlf_k6n10f/dsp_final_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v share/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v share/quicklogic/qlf_k6n10f/ufifo_ctl.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v share/quicklogic/qlf_k6n10f/sram1024x18_mem.v
mkdir -p share/sf2
cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v
mkdir -p share/sf2
cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v
mkdir -p share/sf2
cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v
mkdir -p kernel/
gcc -o kernel/version_d87bd7ca3fc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_d87bd7ca3fc.cc
mkdir -p kernel/
gcc -o kernel/register.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc
mkdir -p frontends/rtlil/
gcc -o frontends/rtlil/rtlil_parser.tab.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_parser.tab.cc
mkdir -p frontends/rtlil/
gcc -o frontends/rtlil/rtlil_lexer.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_lexer.cc
mkdir -p frontends/verilog/
gcc -o frontends/verilog/verilog_parser.tab.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYYMAXDEPTH=10000000 frontends/verilog/verilog_parser.tab.cc
mkdir -p frontends/verilog/
flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l
mkdir -p passes/pmgen/
gcc -o passes/pmgen/test_pmgen.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/test_pmgen.cc
mkdir -p passes/pmgen/
gcc -o passes/pmgen/ice40_wrapcarry.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_wrapcarry.cc
mkdir -p passes/pmgen/
gcc -o passes/pmgen/xilinx_dsp.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_dsp.cc
mkdir -p techlibs/quicklogic/
gcc -o techlibs/quicklogic/ql_dsp_macc.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_macc.cc
mkdir -p ./
gcc -o yosys-filterlib -Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes  -rdynamic passes/techmap/filterlib.o  -lstdc++ -lm -lrt -lreadline -L/usr/lib64/../lib64/lp64d -lffi -ldl -lz -ltcl8.6 -ltclstub8.6
mkdir -p share/gatemate
cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib
mkdir -p share/gatemate
cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v share/quicklogic/qlf_k6n10f/bram_types_sim.v
mkdir -p frontends/verilog/
gcc -o frontends/verilog/verilog_lexer.o -c  -O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB  -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc
gcc -o yosys  -Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes  -rdynamic kernel/version_d87bd7ca3fc.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/viz.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/splitcells.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/cmds/xprop.o passes/cmds/dft_tag.o passes/cmds/future.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_rom.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/formalff.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/recover_names.o passes/sat/qbfsat.o passes/sat/synthprop.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/booth.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/bwmuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/intersynth/intersynth.o backends/jny/jny.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/fabulous/synth_fabulous.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/lattice/synth_lattice.o techlibs/lattice/lattice_gsr.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/quicklogic/ql_bram_merge.o techlibs/quicklogic/ql_bram_types.o techlibs/quicklogic/ql_dsp_simd.o techlibs/quicklogic/ql_dsp_io_regs.o techlibs/quicklogic/ql_dsp_macc.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o  -lstdc++ -lm -lrt -lreadline -L/usr/lib64/../lib64/lp64d -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 
  Build successful.
+ touch manual/empty.pdf
++ stat -c %y debian/man/yosys-smtbmc.txt
++ awk '{ print $1 }'
+ txt2man -d 2019-10-18 -t YOSYS-SMTBMC debian/man/yosys-smtbmc.txt
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.ivLdiy
+ umask 022
+ cd /builddir/build/BUILD
+ '[' /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64 '!=' / ']'
+ rm -rf /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64
++ dirname /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64
+ mkdir -p /builddir/build/BUILDROOT
+ mkdir /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64
+ CFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Werror=implicit-function-declaration -Werror=implicit-int -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CFLAGS
+ CXXFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CXXFLAGS
+ FFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FFLAGS
+ FCFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FCFLAGS
+ VALAFLAGS=-g
+ export VALAFLAGS
+ RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn'
+ export RUSTFLAGS
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ export LDFLAGS
+ LT_SYS_LIBRARY_PATH=/usr/lib64:
+ export LT_SYS_LIBRARY_PATH
+ CC=gcc
+ export CC
+ CXX=g++
+ export CXX
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ /usr/bin/make install DESTDIR=/builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64 'INSTALL=/usr/bin/install -p' PREFIX=/usr ABCEXTERNAL=/usr/bin/abc STRIP=/bin/true
[Makefile.conf] CONFIG := gcc
mkdir -p /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/bin
cp yosys yosys-config yosys-filterlib yosys-smtbmc yosys-witness /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/bin
/bin/true -S /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/bin/yosys
/bin/true /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/bin/yosys-filterlib
mkdir -p /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/yosys
cp -r share/. /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/yosys/.
+ install -d -m0755 /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/include
+ mv /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/yosys/include /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/include/yosys
+ install -d -m0755 /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/man/man1
+ install -m 0644 yosys-smtbmc.1 debian/yosys.1 debian/yosys-config.1 debian/yosys-filterlib.1 /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/man/man1
+ install -d -m0755 /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/doc/yosys
+ install -m 0644 manual/empty.pdf /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/doc/yosys
+ /usr/bin/find-debuginfo -j4 --strict-build-id -m -i --build-id-seed 0.36-1.20231218gitd87bd7c.fc40 --unique-debug-suffix -0.36-1.20231218gitd87bd7c.fc40.riscv64 --unique-debug-src-base yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64 --run-dwz --dwz-low-mem-die-limit 10000000 --dwz-max-die-limit 50000000 -S debugsourcefiles.list /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
find-debuginfo: starting
Extracting debug info from 2 files
DWARF-compressing 2 files
dwz: Too few files for multifile optimization
sepdebugcrcfix: Updated 2 CRC32s, 0 CRC32s did match.
Creating .debug symlinks for symlinks to ELF files
Copying sources found by 'debugedit -l' to /usr/src/debug/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64
14009 blocks
find-debuginfo: done
+ /usr/lib/rpm/check-buildroot
+ /usr/lib/rpm/redhat/brp-ldconfig
+ /usr/lib/rpm/brp-compress
+ /usr/lib/rpm/redhat/brp-strip-lto /usr/bin/strip
+ /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip
+ /usr/lib/rpm/check-rpaths
+ /usr/lib/rpm/redhat/brp-mangle-shebangs
mangling shebang in /usr/bin/yosys-config from /usr/bin/env bash to #!/usr/bin/bash
+ /usr/lib/rpm/brp-remove-la-files
+ env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j4
+ /usr/lib/rpm/redhat/brp-python-hardlink
Executing(%check): /bin/sh -e /var/tmp/rpm-tmp.l67FwN
+ umask 022
+ cd /builddir/build/BUILD
+ CFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Werror=implicit-function-declaration -Werror=implicit-int -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CFLAGS
+ CXXFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer '
+ export CXXFLAGS
+ FFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FFLAGS
+ FCFLAGS='-O2  -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -fasynchronous-unwind-tables -fno-omit-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FCFLAGS
+ VALAFLAGS=-g
+ export VALAFLAGS
+ RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn'
+ export RUSTFLAGS
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ export LDFLAGS
+ LT_SYS_LIBRARY_PATH=/usr/lib64:
+ export LT_SYS_LIBRARY_PATH
+ CC=gcc
+ export CC
+ CXX=g++
+ export CXX
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ make test ABCEXTERNAL=/usr/bin/abc SEED=314159265359
[Makefile.conf] CONFIG := gcc
cd tests/simple && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/simple'
+ gcc -Wall -o /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/tools/cmp_tbdata /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/tools/cmp_tbdata.c
Test: arrays02 -> ok
Test: asgn_binop -> ok
Test: case_expr_extend -> ok
Test: case_expr_query -> ok
Test: defvalue -> ok
Test: implicit_ports -> ok
Test: lesser_size_cast -> ok
Test: local_loop_var -> ok
Test: macro_arg_spaces -> ok
Test: matching_end_labels -> ok
Test: memwr_port_connection -> ok
Test: unnamed_block_decl -> ok
Test: aes_kexp128 -> ok
Test: always01 -> ok
Test: always02 -> ok
Test: always03 -> ok
Test: arraycells -> ok
Test: arrays01 -> ok
Test: attrib01_module -> ok
Test: attrib02_port_decl -> ok
Test: attrib03_parameter -> ok
Test: attrib04_net_var -> ok
Test: attrib06_operator_suffix -> ok
Test: attrib08_mod_inst -> ok
Test: attrib09_case -> ok
Test: carryadd -> ok
Test: case_expr_const -> ok
Test: case_expr_non_const -> ok
Test: case_large -> ok
Test: const_branch_finish -> ok
Test: const_fold_func -> ok
Test: const_func_shadow -> ok
Test: constmuldivmod -> ok
Test: constpower -> ok
Test: dff_different_styles -> ok
Test: dff_init -> ok
Test: dynslice -> ok
Test: fiedler-cooley -> ok
Test: forgen01 -> ok
Test: forgen02 -> ok
Test: forloops -> ok
Test: fsm -> ok
Test: func_block -> ok
Test: func_recurse -> ok
Test: func_width_scope -> ok
Test: genblk_collide -> ok
Test: genblk_dive -> ok
Test: genblk_order -> ok
Test: genblk_port_shadow -> ok
Test: generate -> ok
Test: graphtest -> ok
Test: hierarchy -> ok
Test: hierdefparam -> ok
Test: i2c_master_tests -> ok
Test: ifdef_1 -> ok
Test: ifdef_2 -> ok
Test: localparam_attr -> ok
Test: loop_prefix_case -> ok
Test: loop_var_shadow -> ok
Test: loops -> ok
Test: macro_arg_surrounding_spaces -> ok
Test: macros -> ok
Test: mem2reg -> ok
Test: mem2reg_bounds_tern -> ok
Test: mem_arst -> ok
Test: memory -> ok
Test: module_scope -> ok
Test: module_scope_case -> ok
Test: module_scope_func -> ok
Test: multiplier -> ok
Test: muxtree -> ok
Test: named_genblk -> ok
Test: nested_genblk_resolve -> ok
Test: omsp_dbg_uart -> ok
Test: operators -> ok
Test: param_attr -> ok
Test: paramods -> ok
Test: partsel -> ok
Test: process -> ok
Test: realexpr -> ok
Test: repwhile -> ok
Test: retime -> ok
Test: rotate -> ok
Test: scopes -> ok
Test: signed_full_slice -> ok
Test: signedexpr -> ok
Test: sincos -> ok
Test: specify -> ok
Test: string_format -> ok
Test: subbytes -> ok
Test: task_func -> ok
Test: undef_eqx_nex -> ok
Test: usb_phy_tests -> ok
Test: values -> ok
Test: verilog_primitives -> ok
Test: vloghammer -> ok
Test: wandwor -> ok
Test: wreduce -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/simple'
cd tests/simple_abc9 && bash run-test.sh "-S 314159265359"
ls: cannot access '*.sv': No such file or directory
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/simple_abc9'
Test: abc9 -> ok
Test: aes_kexp128 -> ok
Test: always01 -> ok
Test: always02 -> ok
Test: always03 -> ok
Test: arraycells -> ok
Test: arrays01 -> ok
Test: attrib01_module -> ok
Test: attrib02_port_decl -> ok
Test: attrib03_parameter -> ok
Test: attrib04_net_var -> ok
Test: attrib06_operator_suffix -> ok
Test: attrib08_mod_inst -> ok
Test: attrib09_case -> ok
Test: carryadd -> ok
Test: case_expr_const -> ok
Test: case_expr_non_const -> ok
Test: case_large -> ok
Test: const_branch_finish -> ok
Test: const_fold_func -> ok
Test: const_func_shadow -> ok
Test: constmuldivmod -> ok
Test: constpower -> ok
Test: dff_different_styles -> ok
Test: dff_init -> ok
Test: dynslice -> ok
Test: fiedler-cooley -> ok
Test: forgen01 -> ok
Test: forgen02 -> ok
Test: forloops -> ok
Test: fsm -> ok
Test: func_block -> ok
Test: func_recurse -> ok
Test: func_width_scope -> ok
Test: genblk_collide -> ok
Test: genblk_dive -> ok
Test: genblk_order -> ok
Test: genblk_port_shadow -> ok
Test: generate -> ok
Test: graphtest -> ok
Test: hierarchy -> ok
Test: hierdefparam -> ok
Test: i2c_master_tests -> ok
Test: ifdef_1 -> ok
Test: ifdef_2 -> ok
Test: localparam_attr -> ok
Test: loop_prefix_case -> ok
Test: loop_var_shadow -> ok
Test: loops -> ok
Test: macro_arg_surrounding_spaces -> ok
Test: macros -> ok
Test: mem2reg -> ok
Test: mem2reg_bounds_tern -> ok
Test: mem_arst -> ok
Test: memory -> ok
Test: module_scope -> ok
Test: module_scope_case -> ok
Test: module_scope_func -> ok
Test: multiplier -> ok
Test: muxtree -> ok
Test: named_genblk -> ok
Test: nested_genblk_resolve -> ok
Test: omsp_dbg_uart -> ok
Test: operators -> ok
Test: param_attr -> ok
Test: paramods -> ok
Test: partsel -> ok
Test: process -> ok
Test: realexpr -> ok
Test: repwhile -> ok
Test: retime -> ok
Test: rotate -> ok
Test: scopes -> ok
Test: signed_full_slice -> ok
Test: signedexpr -> ok
Test: sincos -> ok
Test: string_format -> ok
Test: subbytes -> ok
Test: task_func -> ok
Test: undef_eqx_nex -> ok
Test: usb_phy_tests -> ok
Test: values -> ok
Test: verilog_primitives -> ok
Test: vloghammer -> ok
Test: wandwor -> ok
Test: wreduce -> ok
Test: arrays02 -> ok
Test: asgn_binop -> ok
Test: case_expr_extend -> ok
Test: case_expr_query -> ok
Test: defvalue -> ok
Test: implicit_ports -> ok
Test: lesser_size_cast -> ok
Test: local_loop_var -> ok
Test: macro_arg_spaces -> ok
Test: matching_end_labels -> ok
Test: memwr_port_connection -> ok
Test: unnamed_block_decl -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/simple_abc9'
cd tests/hana && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/hana'
Test: test_intermout -> ok
Test: test_parse2synthtrans -> ok
Test: test_parser -> ok
Test: test_simulation_always -> ok
Test: test_simulation_and -> ok
Test: test_simulation_buffer -> ok
Test: test_simulation_decoder -> ok
Test: test_simulation_inc -> ok
Test: test_simulation_mux -> ok
Test: test_simulation_nand -> ok
Test: test_simulation_nor -> ok
Test: test_simulation_or -> ok
Test: test_simulation_seq -> ok
Test: test_simulation_shifter -> ok
Test: test_simulation_sop -> ok
Test: test_simulation_techmap -> ok
Test: test_simulation_techmap_tech -> ok
Test: test_simulation_vlib -> ok
Test: test_simulation_xnor -> ok
Test: test_simulation_xor -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/hana'
cd tests/asicworld && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/asicworld'
Test: code_hdl_models_GrayCounter -> ok
Test: code_hdl_models_arbiter -> ok
Test: code_hdl_models_cam -> ok
Test: code_hdl_models_clk_div -> ok
Test: code_hdl_models_clk_div_45 -> ok
Test: code_hdl_models_d_ff_gates -> ok
Test: code_hdl_models_d_latch_gates -> ok
Test: code_hdl_models_decoder_2to4_gates -> ok
Test: code_hdl_models_decoder_using_assign -> ok
Test: code_hdl_models_decoder_using_case -> ok
Test: code_hdl_models_dff_async_reset -> ok
Test: code_hdl_models_dff_sync_reset -> ok
Test: code_hdl_models_encoder_4to2_gates -> ok
Test: code_hdl_models_encoder_using_case -> ok
Test: code_hdl_models_encoder_using_if -> ok
Test: code_hdl_models_full_adder_gates -> ok
Test: code_hdl_models_full_subtracter_gates -> ok
Test: code_hdl_models_gray_counter -> ok
Test: code_hdl_models_half_adder_gates -> ok
Test: code_hdl_models_lfsr -> ok
Test: code_hdl_models_lfsr_updown -> ok
Test: code_hdl_models_mux_2to1_gates -> ok
Test: code_hdl_models_mux_using_assign -> ok
Test: code_hdl_models_mux_using_case -> ok
Test: code_hdl_models_mux_using_if -> ok
Test: code_hdl_models_one_hot_cnt -> ok
Test: code_hdl_models_parallel_crc -> ok
Test: code_hdl_models_parity_using_assign -> ok
Test: code_hdl_models_parity_using_bitwise -> ok
Test: code_hdl_models_parity_using_function -> ok
Test: code_hdl_models_pri_encoder_using_assign -> ok
Test: code_hdl_models_rom_using_case -> ok
Test: code_hdl_models_serial_crc -> ok
Test: code_hdl_models_tff_async_reset -> ok
Test: code_hdl_models_tff_sync_reset -> ok
Test: code_hdl_models_uart -> ok
Test: code_hdl_models_up_counter -> ok
Test: code_hdl_models_up_counter_load -> ok
Test: code_hdl_models_up_down_counter -> ok
Test: code_specman_switch_fabric -> ok
Test: code_tidbits_asyn_reset -> ok
Test: code_tidbits_blocking -> ok
Test: code_tidbits_fsm_using_always -> ok
Test: code_tidbits_fsm_using_function -> ok
Test: code_tidbits_fsm_using_single_always -> ok
Test: code_tidbits_nonblocking -> ok
Test: code_tidbits_reg_combo_example -> ok
Test: code_tidbits_reg_seq_example -> ok
Test: code_tidbits_syn_reset -> ok
Test: code_tidbits_wire_example -> ok
Test: code_verilog_tutorial_addbit -> ok
Test: code_verilog_tutorial_always_example -> ok
Test: code_verilog_tutorial_bus_con -> ok
Test: code_verilog_tutorial_comment -> ok
Test: code_verilog_tutorial_counter -> ok
Test: code_verilog_tutorial_d_ff -> ok
Test: code_verilog_tutorial_decoder -> ok
Test: code_verilog_tutorial_decoder_always -> ok
Test: code_verilog_tutorial_escape_id -> ok
Test: code_verilog_tutorial_explicit -> ok
Test: code_verilog_tutorial_first_counter -> ok
Test: code_verilog_tutorial_flip_flop -> ok
Test: code_verilog_tutorial_fsm_full -> ok
Test: code_verilog_tutorial_good_code -> ok
Test: code_verilog_tutorial_if_else -> ok
Test: code_verilog_tutorial_multiply -> ok
Test: code_verilog_tutorial_mux_21 -> ok
Test: code_verilog_tutorial_n_out_primitive -> ok
Test: code_verilog_tutorial_parallel_if -> ok
Test: code_verilog_tutorial_parity -> ok
Test: code_verilog_tutorial_simple_function -> ok
Test: code_verilog_tutorial_simple_if -> ok
Test: code_verilog_tutorial_task_global -> ok
Test: code_verilog_tutorial_tri_buf -> ok
Test: code_verilog_tutorial_v2k_reg -> ok
Test: code_verilog_tutorial_which_clock -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/asicworld'
# +cd tests/realmath && bash run-test.sh "-S 314159265359"
cd tests/share && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
[0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]
cd tests/opt_share && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/opt_share'
[0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/opt_share'
cd tests/fsm && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/fsm'
[0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[4]K[5]K[6]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
T[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[16]K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
T[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[24]K[25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[26]K[27]K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[29]K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[31]K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[33]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[34]T[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[38]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[39]K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[41]K[42]K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
T[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[47]K[48]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
T[49]K
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/fsm'
cd tests/techmap && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/techmap'
Passed abc9.ys
Warning: wire '\Q' is assigned in a block at <<EOT:9.5-9.11.
Warning: wire '\Q' is assigned in a block at <<EOT:11.5-11.11.
Passed adff2dff.ys
Passed aigmap.ys
Warning: Resizing cell port top.s0.f.j from 2 bits to 1 bits.
Passed autopurge.ys
Passed bmuxmap_pmux.ys
Passed booth.ys
Passed bug2183.ys
Passed bug2321.ys
Passed bug2332.ys
Passed bug2759.ys
Passed bug2972.ys
Passed cellname.ys
Passed clkbufmap.ys
Passed cmp2lcu.ys
Warning: wire '\Q' is assigned in a block at <<EOT:8.3-8.9.
Passed dff2ff.ys
Passed dffinit.ys
Passed dfflegalize_adff.ys
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff0
Passed dfflegalize_adff_init.ys
Passed dfflegalize_adlatch.ys
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff0
Passed dfflegalize_adlatch_init.ys
Passed dfflegalize_aldff.ys
Passed dfflegalize_aldff_init.ys
Passed dfflegalize_dff.ys
Passed dfflegalize_dff_init.ys
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff0
Passed dfflegalize_dffsr.ys
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff0 [$_DFFSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff0 [$_DFFSR_PPP_].
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff0 [$_DFFSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff0 [$_DFFSR_PPP_].
Passed dfflegalize_dffsr_init.ys
Passed dfflegalize_dlatch.ys
Passed dfflegalize_dlatch_const.ys
Passed dfflegalize_dlatch_init.ys
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff0
Passed dfflegalize_dlatchsr.ys
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff0 [$_DLATCHSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff0 [$_DLATCHSR_PPP_].
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff0 [$_DLATCHSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff0 [$_DLATCHSR_PPP_].
Passed dfflegalize_dlatchsr_init.ys
Passed dfflegalize_inv.ys
Passed dfflegalize_mince.ys
Passed dfflegalize_minsrst.ys
Passed dfflegalize_sr.ys
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff0 [$_SR_PP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff0 [$_SR_PP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff0 [$_SR_PP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff0 [$_SR_PP_].
Passed dfflegalize_sr_init.ys
Warning: Complex async reset for dff `\Q'.
Passed dfflibmap.ys
Passed dffunmap.ys
Passed extractinv.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:23)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:29)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:35)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:58)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:14)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:18)
Passed iopadmap.ys
Passed pmux2mux.ys
Passed shiftx2mux.ys
Passed techmap_replace.ys
Passed wireinit.ys
Passed zinit.ys
Passed mem_simple_4x1_runtest.sh
Passed recursive_runtest.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/techmap'
cd tests/memories && bash run-test.sh "-A /usr/bin/abc" "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/memories'
Test: amber23_sram_byte_en -> ok
Test: firrtl_938 -> ok
Test: implicit_en -> ok
Test: issue00335 -> ok
Test: issue00710 -> ok
Test: no_implicit_en -> ok
Test: read_arst -> ok
Test: read_two_mux -> ok
Test: shared_ports -> ok
Test: simple_sram_byte_en -> ok
Test: trans_addr_enable -> ok
Test: trans_sdp -> ok
Test: trans_sp -> ok
Test: wide_all -> ok
Test: wide_read_async -> ok
Test: wide_read_mixed -> ok
Test: wide_read_sync -> ok
Test: wide_read_trans -> ok
Test: wide_thru_priority -> ok
Test: wide_write -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/memories'
egrep: warning: egrep is obsolescent; using grep -E
Testing expectations for amber23_sram_byte_en.v .. ok.
Testing expectations for implicit_en.v .. ok.
Testing expectations for issue00335.v .. ok.
Testing expectations for issue00710.v .. ok.
Testing expectations for no_implicit_en.v .. ok.
Testing expectations for read_arst.v .. ok.
Testing expectations for read_two_mux.v .. ok.
Testing expectations for shared_ports.v .. ok.
Testing expectations for simple_sram_byte_en.v .. ok.
Testing expectations for trans_addr_enable.v .. ok.
Testing expectations for trans_sdp.v .. ok.
Testing expectations for trans_sp.v .. ok.
Testing expectations for wide_all.v .. ok.
Testing expectations for wide_read_async.v .. ok.
Testing expectations for wide_read_mixed.v .. ok.
Testing expectations for wide_read_sync.v .. ok.
Testing expectations for wide_read_trans.v .. ok.
Testing expectations for wide_thru_priority.v .. ok.
Testing expectations for wide_write.v .. ok.
cd tests/memlib && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/memlib'
Test: t_async_big -> ok
Test: t_async_big_block -> ok
Test: t_async_small -> ok
Test: t_async_small_block -> ok
Test: t_sync_big -> ok
Test: t_sync_big_sdp -> ok
Test: t_sync_big_lut -> ok
Test: t_sync_small -> ok
Test: t_sync_small_block -> ok
Test: t_sync_small_block_attr -> ok
Test: t_init_lut_zeros_zero -> ok
Test: t_init_lut_zeros_any -> ok
Test: t_init_lut_val_zero -> ok
Test: t_init_lut_val_any -> ok
Test: t_init_lut_val_no_undef -> ok
Test: t_init_lut_val2_any -> ok
Test: t_init_lut_val2_no_undef -> ok
Test: t_init_lut_x_none -> ok
Test: t_init_lut_x_zero -> ok
Test: t_init_lut_x_any -> ok
Test: t_init_lut_x_no_undef -> ok
Test: t_ram_18b2B -> ok
Test: t_ram_9b1B -> ok
Test: t_ram_4b1B -> ok
Test: t_ram_2b1B -> ok
Test: t_ram_1b1B -> ok
Test: t_init_9b1B_zeros_zero -> ok
Test: t_init_9b1B_zeros_any -> ok
Test: t_init_9b1B_val_zero -> ok
Test: t_init_9b1B_val_any -> ok
Test: t_init_9b1B_val_no_undef -> ok
Test: t_init_13b2B_val_any -> ok
Test: t_init_18b2B_val_any -> ok
Test: t_init_18b2B_val_no_undef -> ok
Test: t_init_4b1B_x_none -> ok
Test: t_init_4b1B_x_zero -> ok
Test: t_init_4b1B_x_any -> ok
Test: t_init_4b1B_x_no_undef -> ok
Test: t_clock_a4_wANYrANYsFalse -> ok
Test: t_clock_a4_wANYrNEGsFalse -> ok
Test: t_clock_a4_wANYrPOSsFalse -> ok
Test: t_clock_a4_wNEGrANYsFalse -> ok
Test: t_clock_a4_wNEGrPOSsFalse -> ok
Test: t_clock_a4_wNEGrNEGsFalse -> ok
Test: t_clock_a4_wPOSrANYsFalse -> ok
Test: t_clock_a4_wPOSrNEGsFalse -> ok
Test: t_clock_a4_wPOSrPOSsFalse -> ok
Test: t_clock_a4_wANYrANYsTrue -> ok
Test: t_clock_a4_wNEGrPOSsTrue -> ok
Test: t_clock_a4_wNEGrNEGsTrue -> ok
Test: t_clock_a4_wPOSrNEGsTrue -> ok
Test: t_clock_a4_wPOSrPOSsTrue -> ok
Test: t_unmixed -> ok
Test: t_mixed_9_18 -> ok
Test: t_mixed_18_9 -> ok
Test: t_mixed_36_9 -> ok
Test: t_mixed_4_2 -> ok
Test: t_tdp -> ok
Test: t_sync_2clk -> ok
Test: t_sync_shared -> ok
Test: t_sync_2clk_shared -> ok
Test: t_sync_trans_old_old -> ok
Test: t_sync_trans_old_new -> ok
Test: t_sync_trans_old_none -> ok
Test: t_sync_trans_new_old -> ok
Test: t_sync_trans_new_new -> ok
Test: t_sync_trans_new_none -> ok
Test: t_sp_nc_none -> ok
Test: t_sp_new_none -> ok
Test: t_sp_old_none -> ok
Test: t_sp_nc_nc -> ok
Test: t_sp_new_nc -> ok
Test: t_sp_old_nc -> ok
Test: t_sp_nc_new -> ok
Test: t_sp_new_new -> ok
Test: t_sp_old_new -> ok
Test: t_sp_nc_old -> ok
Test: t_sp_new_old -> ok
Test: t_sp_old_old -> ok
Test: t_sp_nc_new_only -> ok
Test: t_sp_new_new_only -> ok
Test: t_sp_old_new_only -> ok
Test: t_sp_nc_new_only_be -> ok
Test: t_sp_new_new_only_be -> ok
Test: t_sp_old_new_only_be -> ok
Test: t_sp_nc_new_be -> ok
Test: t_sp_new_new_be -> ok
Test: t_sp_old_new_be -> ok
Test: t_sp_nc_old_be -> ok
Test: t_sp_new_old_be -> ok
Test: t_sp_old_old_be -> ok
Test: t_sp_nc_nc_be -> ok
Test: t_sp_new_nc_be -> ok
Test: t_sp_old_nc_be -> ok
Test: t_sp_nc_auto -> ok
Test: t_sp_new_auto -> ok
Test: t_sp_old_auto -> ok
Test: t_sp_nc_auto_be -> ok
Test: t_sp_new_auto_be -> ok
Test: t_sp_old_auto_be -> ok
Test: t_sp_init_x_x -> ok
Test: t_sp_init_x_x_re -> ok
Test: t_sp_init_x_x_ce -> ok
Test: t_sp_init_0_x -> ok
Test: t_sp_init_0_x_re -> ok
Test: t_sp_init_0_0 -> ok
Test: t_sp_init_0_0_re -> ok
Test: t_sp_init_0_any -> ok
Test: t_sp_init_0_any_re -> ok
Test: t_sp_init_v_x -> ok
Test: t_sp_init_v_x_re -> ok
Test: t_sp_init_v_0 -> ok
Test: t_sp_init_v_0_re -> ok
Test: t_sp_init_v_any -> ok
Test: t_sp_init_v_any_re -> ok
Test: t_sp_arst_x_x -> ok
Test: t_sp_arst_x_x_re -> ok
Test: t_sp_arst_0_x -> ok
Test: t_sp_arst_0_x_re -> ok
Test: t_sp_arst_0_0 -> ok
Test: t_sp_arst_0_0_re -> ok
Test: t_sp_arst_0_any -> ok
Test: t_sp_arst_0_any_re -> ok
Test: t_sp_arst_0_init -> ok
Test: t_sp_arst_0_init_re -> ok
Test: t_sp_arst_v_x -> ok
Test: t_sp_arst_v_x_re -> ok
Test: t_sp_arst_v_0 -> ok
Test: t_sp_arst_v_0_re -> ok
Test: t_sp_arst_v_any -> ok
Test: t_sp_arst_v_any_re -> ok
Test: t_sp_arst_v_init -> ok
Test: t_sp_arst_v_init_re -> ok
Test: t_sp_arst_e_x -> ok
Test: t_sp_arst_e_x_re -> ok
Test: t_sp_arst_e_0 -> ok
Test: t_sp_arst_e_0_re -> ok
Test: t_sp_arst_e_any -> ok
Test: t_sp_arst_e_any_re -> ok
Test: t_sp_arst_e_init -> ok
Test: t_sp_arst_e_init_re -> ok
Test: t_sp_arst_n_x -> ok
Test: t_sp_arst_n_x_re -> ok
Test: t_sp_arst_n_0 -> ok
Test: t_sp_arst_n_0_re -> ok
Test: t_sp_arst_n_any -> ok
Test: t_sp_arst_n_any_re -> ok
Test: t_sp_arst_n_init -> ok
Test: t_sp_arst_n_init_re -> ok
Test: t_sp_srst_x_x -> ok
Test: t_sp_srst_x_x_re -> ok
Test: t_sp_srst_0_x -> ok
Test: t_sp_srst_0_x_re -> ok
Test: t_sp_srst_0_0 -> ok
Test: t_sp_srst_0_0_re -> ok
Test: t_sp_srst_0_any -> ok
Test: t_sp_srst_0_any_re -> ok
Test: t_sp_srst_0_init -> ok
Test: t_sp_srst_0_init_re -> ok
Test: t_sp_srst_v_x -> ok
Test: t_sp_srst_v_x_re -> ok
Test: t_sp_srst_v_0 -> ok
Test: t_sp_srst_v_0_re -> ok
Test: t_sp_srst_v_any -> ok
Test: t_sp_srst_v_any_re -> ok
Test: t_sp_srst_v_any_re_gated -> ok
Test: t_sp_srst_v_any_ce -> ok
Test: t_sp_srst_v_any_ce_gated -> ok
Test: t_sp_srst_v_init -> ok
Test: t_sp_srst_v_init_re -> ok
Test: t_sp_srst_e_x -> ok
Test: t_sp_srst_e_x_re -> ok
Test: t_sp_srst_e_0 -> ok
Test: t_sp_srst_e_0_re -> ok
Test: t_sp_srst_e_any -> ok
Test: t_sp_srst_e_any_re -> ok
Test: t_sp_srst_e_init -> ok
Test: t_sp_srst_e_init_re -> ok
Test: t_sp_srst_n_x -> ok
Test: t_sp_srst_n_x_re -> ok
Test: t_sp_srst_n_0 -> ok
Test: t_sp_srst_n_0_re -> ok
Test: t_sp_srst_n_any -> ok
Test: t_sp_srst_n_any_re -> ok
Test: t_sp_srst_n_init -> ok
Test: t_sp_srst_n_init_re -> ok
Test: t_sp_srst_gv_x -> ok
Test: t_sp_srst_gv_x_re -> ok
Test: t_sp_srst_gv_0 -> ok
Test: t_sp_srst_gv_0_re -> ok
Test: t_sp_srst_gv_any -> ok
Test: t_sp_srst_gv_any_re -> ok
Test: t_sp_srst_gv_any_re_gated -> ok
Test: t_sp_srst_gv_any_ce -> ok
Test: t_sp_srst_gv_any_ce_gated -> ok
Test: t_sp_srst_gv_init -> ok
Test: t_sp_srst_gv_init_re -> ok
Test: t_wren_a4d4_NO_BYTE -> ok
Test: t_wren_a5d4_NO_BYTE -> ok
Test: t_wren_a6d4_NO_BYTE -> ok
Test: t_wren_a3d8_NO_BYTE -> ok
Test: t_wren_a4d8_NO_BYTE -> ok
Test: t_wren_a4d4_W4_B4 -> ok
Test: t_wren_a4d8_W4_B4_separate -> ok
Test: t_wren_a4d8_W8_B4 -> ok
Test: t_wren_a4d8_W8_B4_separate -> ok
Test: t_wren_a4d8_W8_B8 -> ok
Test: t_wren_a4d8_W8_B8_separate -> ok
Test: t_wren_a4d2w8_W16_B4 -> ok
Test: t_wren_a4d2w8_W16_B4_separate -> ok
Test: t_wren_a4d4w4_W16_B4 -> ok
Test: t_wren_a4d4w4_W16_B4_separate -> ok
Test: t_wren_a5d4w2_W16_B4 -> ok
Test: t_wren_a5d4w2_W16_B4_separate -> ok
Test: t_wren_a5d4w4_W16_B4 -> ok
Test: t_wren_a5d4w4_W16_B4_separate -> ok
Test: t_wren_a4d8w2_W16_B4 -> ok
Test: t_wren_a4d8w2_W16_B4_separate -> ok
Test: t_wren_a5d8w1_W16_B4 -> ok
Test: t_wren_a5d8w1_W16_B4_separate -> ok
Test: t_wren_a5d8w2_W16_B4 -> ok
Test: t_wren_a5d8w2_W16_B4_separate -> ok
Test: t_wren_a4d16w1_W16_B4 -> ok
Test: t_wren_a4d16w1_W16_B4_separate -> ok
Test: t_wren_a4d4w2_W8_B8 -> ok
Test: t_wren_a4d4w2_W8_B8_separate -> ok
Test: t_wren_a4d4w1_W8_B8 -> ok
Test: t_wren_a4d4w1_W8_B8_separate -> ok
Test: t_wren_a4d8w2_W8_B8 -> ok
Test: t_wren_a4d8w2_W8_B8_separate -> ok
Test: t_wren_a3d8w2_W8_B8 -> ok
Test: t_wren_a3d8w2_W8_B8_separate -> ok
Test: t_wren_a4d4w2_W8_B4 -> ok
Test: t_wren_a4d4w2_W8_B4_separate -> ok
Test: t_wren_a4d2w4_W8_B4 -> ok
Test: t_wren_a4d2w4_W8_B4_separate -> ok
Test: t_wren_a4d4w4_W8_B4 -> ok
Test: t_wren_a4d4w4_W8_B4_separate -> ok
Test: t_wren_a4d4w4_W4_B4 -> ok
Test: t_wren_a4d4w4_W4_B4_separate -> ok
Test: t_wren_a4d4w5_W4_B4 -> ok
Test: t_wren_a4d4w5_W4_B4_separate -> ok
Test: t_geom_a4d64_wren -> ok
Test: t_geom_a5d32_wren -> ok
Test: t_geom_a5d64_wren -> ok
Test: t_geom_a6d16_wren -> ok
Test: t_geom_a6d30_wren -> ok
Test: t_geom_a6d64_wren -> ok
Test: t_geom_a7d4_wren -> ok
Test: t_geom_a7d6_wren -> ok
Test: t_geom_a7d8_wren -> ok
Test: t_geom_a7d17_wren -> ok
Test: t_geom_a8d4_wren -> ok
Test: t_geom_a8d6_wren -> ok
Test: t_geom_a9d4_wren -> ok
Test: t_geom_a9d8_wren -> ok
Test: t_geom_a9d5_wren -> ok
Test: t_geom_a9d6_wren -> ok
Test: t_geom_a3d18_9b1B -> ok
Test: t_geom_a4d4_9b1B -> ok
Test: t_geom_a4d18_9b1B -> ok
Test: t_geom_a5d32_9b1B -> ok
Test: t_geom_a6d4_9b1B -> ok
Test: t_geom_a7d11_9b1B -> ok
Test: t_geom_a7d18_9b1B -> ok
Test: t_geom_a11d1_9b1B -> ok
Test: t_wide_sdp_a6r1w1b1x1 -> ok
Test: t_wide_sdp_a7r1w1b1x1 -> ok
Test: t_wide_sdp_a8r1w1b1x1 -> ok
Test: t_wide_sdp_a6r0w0b0x0 -> ok
Test: t_wide_sdp_a6r1w0b0x0 -> ok
Test: t_wide_sdp_a6r2w0b0x0 -> ok
Test: t_wide_sdp_a6r3w0b0x0 -> ok
Test: t_wide_sdp_a6r4w0b0x0 -> ok
Test: t_wide_sdp_a6r5w0b0x0 -> ok
Test: t_wide_sdp_a6r0w1b0x0 -> ok
Test: t_wide_sdp_a6r0w1b1x0 -> ok
Test: t_wide_sdp_a6r0w2b0x0 -> ok
Test: t_wide_sdp_a6r0w2b2x0 -> ok
Test: t_wide_sdp_a6r0w3b2x0 -> ok
Test: t_wide_sdp_a6r0w4b2x0 -> ok
Test: t_wide_sdp_a6r0w5b2x0 -> ok
Test: t_wide_sdp_a7r0w0b0x0 -> ok
Test: t_wide_sdp_a7r1w0b0x0 -> ok
Test: t_wide_sdp_a7r2w0b0x0 -> ok
Test: t_wide_sdp_a7r3w0b0x0 -> ok
Test: t_wide_sdp_a7r4w0b0x0 -> ok
Test: t_wide_sdp_a7r5w0b0x0 -> ok
Test: t_wide_sdp_a7r0w1b0x0 -> ok
Test: t_wide_sdp_a7r0w1b1x0 -> ok
Test: t_wide_sdp_a7r0w2b0x0 -> ok
Test: t_wide_sdp_a7r0w2b2x0 -> ok
Test: t_wide_sdp_a7r0w3b2x0 -> ok
Test: t_wide_sdp_a7r0w4b2x0 -> ok
Test: t_wide_sdp_a7r0w5b2x0 -> ok
Test: t_wide_sp_mix_a6r1w1b1 -> ok
Test: t_wide_sp_mix_a7r1w1b1 -> ok
Test: t_wide_sp_mix_a8r1w1b1 -> ok
Test: t_wide_sp_mix_a6r0w0b0 -> ok
Test: t_wide_sp_mix_a6r1w0b0 -> ok
Test: t_wide_sp_mix_a6r2w0b0 -> ok
Test: t_wide_sp_mix_a6r3w0b0 -> ok
Test: t_wide_sp_mix_a6r4w0b0 -> ok
Test: t_wide_sp_mix_a6r5w0b0 -> ok
Test: t_wide_sp_mix_a6r0w1b0 -> ok
Test: t_wide_sp_mix_a6r0w1b1 -> ok
Test: t_wide_sp_mix_a6r0w2b0 -> ok
Test: t_wide_sp_mix_a6r0w2b2 -> ok
Test: t_wide_sp_mix_a6r0w3b2 -> ok
Test: t_wide_sp_mix_a6r0w4b2 -> ok
Test: t_wide_sp_mix_a6r0w5b2 -> ok
Test: t_wide_sp_mix_a7r0w0b0 -> ok
Test: t_wide_sp_mix_a7r1w0b0 -> ok
Test: t_wide_sp_mix_a7r2w0b0 -> ok
Test: t_wide_sp_mix_a7r3w0b0 -> ok
Test: t_wide_sp_mix_a7r4w0b0 -> ok
Test: t_wide_sp_mix_a7r5w0b0 -> ok
Test: t_wide_sp_mix_a7r0w1b0 -> ok
Test: t_wide_sp_mix_a7r0w1b1 -> ok
Test: t_wide_sp_mix_a7r0w2b0 -> ok
Test: t_wide_sp_mix_a7r0w2b2 -> ok
Test: t_wide_sp_mix_a7r0w3b2 -> ok
Test: t_wide_sp_mix_a7r0w4b2 -> ok
Test: t_wide_sp_mix_a7r0w5b2 -> ok
Test: t_wide_sp_tied_a6r1w1b1 -> ok
Test: t_wide_sp_tied_a7r1w1b1 -> ok
Test: t_wide_sp_tied_a8r1w1b1 -> ok
Test: t_wide_sp_tied_a6r0w0b0 -> ok
Test: t_wide_sp_tied_a6r1w0b0 -> ok
Test: t_wide_sp_tied_a6r2w0b0 -> ok
Test: t_wide_sp_tied_a6r3w0b0 -> ok
Test: t_wide_sp_tied_a6r4w0b0 -> ok
Test: t_wide_sp_tied_a6r5w0b0 -> ok
Test: t_wide_sp_tied_a6r0w1b0 -> ok
Test: t_wide_sp_tied_a6r0w1b1 -> ok
Test: t_wide_sp_tied_a6r0w2b0 -> ok
Test: t_wide_sp_tied_a6r0w2b2 -> ok
Test: t_wide_sp_tied_a6r0w3b2 -> ok
Test: t_wide_sp_tied_a6r0w4b2 -> ok
Test: t_wide_sp_tied_a6r0w5b2 -> ok
Test: t_wide_sp_tied_a7r0w0b0 -> ok
Test: t_wide_sp_tied_a7r1w0b0 -> ok
Test: t_wide_sp_tied_a7r2w0b0 -> ok
Test: t_wide_sp_tied_a7r3w0b0 -> ok
Test: t_wide_sp_tied_a7r4w0b0 -> ok
Test: t_wide_sp_tied_a7r5w0b0 -> ok
Test: t_wide_sp_tied_a7r0w1b0 -> ok
Test: t_wide_sp_tied_a7r0w1b1 -> ok
Test: t_wide_sp_tied_a7r0w2b0 -> ok
Test: t_wide_sp_tied_a7r0w2b2 -> ok
Test: t_wide_sp_tied_a7r0w3b2 -> ok
Test: t_wide_sp_tied_a7r0w4b2 -> ok
Test: t_wide_sp_tied_a7r0w5b2 -> ok
Test: t_wide_read_a6r1w1b1 -> ok
Test: t_wide_write_a6r1w1b1 -> ok
Test: t_wide_read_a7r1w1b1 -> ok
Test: t_wide_write_a7r1w1b1 -> ok
Test: t_wide_read_a8r1w1b1 -> ok
Test: t_wide_write_a8r1w1b1 -> ok
Test: t_wide_read_a6r0w0b0 -> ok
Test: t_wide_write_a6r0w0b0 -> ok
Test: t_wide_read_a6r1w0b0 -> ok
Test: t_wide_write_a6r1w0b0 -> ok
Test: t_wide_read_a6r2w0b0 -> ok
Test: t_wide_write_a6r2w0b0 -> ok
Test: t_wide_read_a6r3w0b0 -> ok
Test: t_wide_write_a6r3w0b0 -> ok
Test: t_wide_read_a6r4w0b0 -> ok
Test: t_wide_write_a6r4w0b0 -> ok
Test: t_wide_read_a6r5w0b0 -> ok
Test: t_wide_write_a6r5w0b0 -> ok
Test: t_wide_read_a6r0w1b0 -> ok
Test: t_wide_write_a6r0w1b0 -> ok
Test: t_wide_read_a6r0w1b1 -> ok
Test: t_wide_write_a6r0w1b1 -> ok
Test: t_wide_read_a6r0w2b0 -> ok
Test: t_wide_write_a6r0w2b0 -> ok
Test: t_wide_read_a6r0w2b2 -> ok
Test: t_wide_write_a6r0w2b2 -> ok
Test: t_wide_read_a6r0w3b2 -> ok
Test: t_wide_write_a6r0w3b2 -> ok
Test: t_wide_read_a6r0w4b2 -> ok
Test: t_wide_write_a6r0w4b2 -> ok
Test: t_wide_read_a6r0w5b2 -> ok
Test: t_wide_write_a6r0w5b2 -> ok
Test: t_wide_read_a7r0w0b0 -> ok
Test: t_wide_write_a7r0w0b0 -> ok
Test: t_wide_read_a7r1w0b0 -> ok
Test: t_wide_write_a7r1w0b0 -> ok
Test: t_wide_read_a7r2w0b0 -> ok
Test: t_wide_write_a7r2w0b0 -> ok
Test: t_wide_read_a7r3w0b0 -> ok
Test: t_wide_write_a7r3w0b0 -> ok
Test: t_wide_read_a7r4w0b0 -> ok
Test: t_wide_write_a7r4w0b0 -> ok
Test: t_wide_read_a7r5w0b0 -> ok
Test: t_wide_write_a7r5w0b0 -> ok
Test: t_wide_read_a7r0w1b0 -> ok
Test: t_wide_write_a7r0w1b0 -> ok
Test: t_wide_read_a7r0w1b1 -> ok
Test: t_wide_write_a7r0w1b1 -> ok
Test: t_wide_read_a7r0w2b0 -> ok
Test: t_wide_write_a7r0w2b0 -> ok
Test: t_wide_read_a7r0w2b2 -> ok
Test: t_wide_write_a7r0w2b2 -> ok
Test: t_wide_read_a7r0w3b2 -> ok
Test: t_wide_write_a7r0w3b2 -> ok
Test: t_wide_read_a7r0w4b2 -> ok
Test: t_wide_write_a7r0w4b2 -> ok
Test: t_wide_read_a7r0w5b2 -> ok
Test: t_wide_write_a7r0w5b2 -> ok
Test: t_quad_port_a2d2 -> ok
Test: t_quad_port_a4d2 -> ok
Test: t_quad_port_a5d2 -> ok
Test: t_quad_port_a4d4 -> ok
Test: t_quad_port_a6d2 -> ok
Test: t_quad_port_a4d8 -> ok
Test: t_wide_quad_a4w2r1 -> ok
Test: t_wide_oct_a4w2r1 -> ok
Test: t_wide_quad_a4w2r2 -> ok
Test: t_wide_oct_a4w2r2 -> ok
Test: t_wide_quad_a4w2r3 -> ok
Test: t_wide_oct_a4w2r3 -> ok
Test: t_wide_quad_a4w2r4 -> ok
Test: t_wide_oct_a4w2r4 -> ok
Test: t_wide_quad_a4w2r5 -> ok
Test: t_wide_oct_a4w2r5 -> ok
Test: t_wide_quad_a4w2r6 -> ok
Test: t_wide_oct_a4w2r6 -> ok
Test: t_wide_quad_a4w2r7 -> ok
Test: t_wide_oct_a4w2r7 -> ok
Test: t_wide_quad_a4w2r8 -> ok
Test: t_wide_oct_a4w2r8 -> ok
Test: t_wide_quad_a4w2r9 -> ok
Test: t_wide_oct_a4w2r9 -> ok
Test: t_wide_quad_a4w4r1 -> ok
Test: t_wide_oct_a4w4r1 -> ok
Test: t_wide_quad_a4w4r4 -> ok
Test: t_wide_oct_a4w4r4 -> ok
Test: t_wide_quad_a4w4r6 -> ok
Test: t_wide_oct_a4w4r6 -> ok
Test: t_wide_quad_a4w4r9 -> ok
Test: t_wide_oct_a4w4r9 -> ok
Test: t_wide_quad_a5w2r1 -> ok
Test: t_wide_oct_a5w2r1 -> ok
Test: t_wide_quad_a5w2r4 -> ok
Test: t_wide_oct_a5w2r4 -> ok
Test: t_wide_quad_a5w2r9 -> ok
Test: t_wide_oct_a5w2r9 -> ok
Test: t_no_reset -> ok
Test: t_gclken -> ok
Test: t_ungated -> ok
Test: t_gclken_ce -> ok
Test: t_grden -> ok
Test: t_grden_ce -> ok
Test: t_exclwr -> ok
Test: t_excl_rst -> ok
Test: t_transwr -> ok
Test: t_trans_rst -> ok
Test: t_wr_byte -> ok
Test: t_trans_byte -> ok
Test: t_wr_rst_byte -> ok
Test: t_rst_wr_byte -> ok
Test: t_rdenrst_wr_byte -> ok
Test: t_rom_case -> ok
Test: t_rom_case_block -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/memlib'
cd tests/bram && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/bram'
Passed memory_bram test 00_01.
Passed memory_bram test 00_02.
Passed memory_bram test 00_03.
Passed memory_bram test 00_04.
Passed memory_bram test 01_00.
Passed memory_bram test 01_02.
Passed memory_bram test 01_03.
Passed memory_bram test 01_04.
Passed memory_bram test 02_00.
Passed memory_bram test 02_01.
Passed memory_bram test 02_03.
Passed memory_bram test 02_04.
Passed memory_bram test 03_00.
Passed memory_bram test 03_01.
Passed memory_bram test 03_02.
Passed memory_bram test 03_04.
Passed memory_bram test 04_00.
Passed memory_bram test 04_01.
Passed memory_bram test 04_02.
Passed memory_bram test 04_03.
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/bram'
cd tests/various && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/various'
Warning: Wire abc9_test027.$abc$91$o is used but has no driver.
Passed abc9.ys
Passed aiger_dff.ys
Passed attrib05_port_conn.ys
Passed attrib07_func_call.ys
Passed autoname.ys
Passed blackbox_wb.ys
Passed bug1496.ys
Passed bug1531.ys
Passed bug1614.ys
Passed bug1710.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
<<EOT:3: ERROR: syntax error, unexpected TOK_CONSTVAL
Expected error pattern 'syntax error, unexpected TOK_CONSTVAL' found !!!
Passed bug1745.ys
Passed bug1781.ys
Passed bug1876.ys
Passed bug2014.ys
Passed bug3462.ys
Passed cellarray_array_connections.ys
Passed chformal_coverenable.ys
Passed const_arg_loop.ys
Passed const_func.ys
Passed const_func_block_var.ys
Warning: Drivers conflicting with a constant 1'1 driver:
    module input A[0]
Warning: Drivers conflicting with a constant 1'1 driver:
    port Y[0] of cell some_buffer (buffer)
Warning: reg '\Q' is assigned in a continuous assignment at <<EOT:5.9-5.14.
Warning: Drivers conflicting with a constant 1'1 driver:
    action \Q <= $0\Q[0:0] (sync rule) in process $proc$<<EOT:3$1
Passed constant_drive_conflict.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_BASE
Expected error pattern 'syntax error, unexpected TOK_BASE' found !!!
Passed constcomment.ys
Passed constmsk_test.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:3)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:5)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:6)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:7)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:8)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:9)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:10)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:11)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:12)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:13)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:14)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:15)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:52)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:53)
Passed countbits.ys
Passed deminout_unused.ys
Passed design.ys
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Passed design1.ys
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Passed design2.ys
Passed dynamic_part_select.ys
elab_sys_tasks.sv:8: Warning: X is 1.
elab_sys_tasks.sv:22: Warning: 
Passed elab_sys_tasks.ys
Passed equiv_make_make_assert.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/simcells.v:456)
Passed equiv_opt_multiclock.ys
Passed equiv_opt_undef.ys
ERROR: Command stdout did have a line matching given regex "giraffe".
Expected error pattern 'stdout did have a line' found !!!
Passed exec.ys
Passed fib.ys
Passed fib_tern.ys
Passed func_port_implied_dir.ys
Passed gen_if_null.ys
Passed global_scope.ys
Passed gzip_verilog.ys
Passed help.ys
Passed hierarchy_defer.ys
Passed hierarchy_param.ys
Passed ice40_mince_abc9.ys
<<EOT:2: ERROR: syntax error, unexpected '[', expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected' found !!!
Passed integer_range_bad_syntax.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_REAL, expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected TOK_REAL' found !!!
Passed integer_real_bad_syntax.ys
attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"
Passed json_escape_chars.ys
ERROR: Identifier `\b' is implicitly declared.
Expected error pattern 'is implicitly declared.' found !!!
Passed logger_error.ys
Passed logger_nowarning.ys
Warning: Found log message matching -W regex:
Added regex 'Successfully finished Verilog frontend.' for warnings to expected warning list.
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Warning: Found log message matching -W regex:
Successfully finished Verilog frontend.
Passed logger_warn.ys
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Passed logger_warning.ys
Passed logic_param_simple.ys
Passed mem2reg.ys
Passed memory_word_as_index.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/simcells.v:456)
Passed muxcover.ys
Passed muxpack.ys
Passed param_struct.ys
Passed peepopt.ys
Passed pmgen_reduce.ys
Passed pmux2shiftx.ys
Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.os2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.os1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits.
Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits.
Passed port_sign_extend.ys
Passed primitives.ys
Passed printattr.ys
Passed rand_const.ys
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21.
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18.
Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22.
Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16.
Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17.
Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70
Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68
Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63
Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61
Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58
Passed reg_wire_error.ys
Passed rename_scramble_name.ys
Passed rtlil_z_bits.ys
Passed scratchpad.ys
Passed script.ys
Passed sformatf.ys
Passed shregmap.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '['
Expected error pattern 'syntax error, unexpected TOK_INTEGER' found !!!
Passed signed.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:5)
Passed signext.ys
Passed sim_const.ys
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string.
Warning: No SAT model available for cell B_0 ($specrule).
Warning: No SAT model available for cell C_0 ($specrule).
Warning: No SAT model available for cell A_0 ($specify3).
Warning: No SAT model available for cell A_0 ($specify2).
Warning: No SAT model available for cell B_0 ($specify2).
Passed specify.ys
Warning: wire '\o' is assigned in a block at <<EOT:2.11-2.17.
Warning: wire '\p' is assigned in a block at <<EOT:3.11-3.16.
Passed src.ys
Warning: Critical-path does not terminate in a recognised endpoint.
Warning: Cell type 'const0' not recognised! Ignoring.
Passed sta.ys
Passed struct_access.ys
Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports.
Passed submod.ys
Passed submod_extract.ys
Passed sv_defines.ys
ERROR: Duplicate macro arguments with name `x'.
Expected error pattern 'Duplicate macro arguments with name `x'' found !!!
Passed sv_defines_dup.ys
ERROR: Mismatched brackets in macro argument: [ and }.
Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!!
Passed sv_defines_mismatch.ys
ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default).
Expected error pattern 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' found !!!
Passed sv_defines_too_few.ys
Passed wreduce.ys
Passed write_gzip.ys
Passed xaiger.ys
Passed async.sh
Passed chparam.sh
Passed hierarchy.sh
Passed logger_fail.sh
Passed plugin.sh
Passed smtlib2_module.sh
Passed sv_implicit_ports.sh
Passed svalways.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/various'
cd tests/select && bash run-test.sh
Running blackboxes.ys..
Running no_warn_assert.ys..
Running no_warn_prefixed_arg_memb.ys..
Running no_warn_prefixed_empty_select_arg.ys..
Running unset.ys..
ERROR: Selection '\foo' does not exist!
Expected error pattern 'Selection '\\foo' does not exist!' found !!!
Running unset2.ys..
ERROR: Selection @foo is not defined!
Expected error pattern 'Selection @foo is not defined!' found !!!
Running warn_empty_select_arg.ys..
Warning: Selection "foo" did not match any module.
Warning: Selection "bar" did not match any object.
cd tests/sat && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/sat'
Passed asserts.ys
Passed asserts_seq.ys
Passed bug2595.ys
Warning: Complex async reset for dff `\q [12]'.
Warning: Complex async reset for dff `\q [8]'.
Passed clk2fflogic.ys
Passed counters-repeat.ys
Passed counters.ys
Passed dff.ys
Passed expose_dff.ys
Passed grom.ys
Passed initval.ys
Passed share.ys
Warning: Wire top.\cnt [7] is used but has no driver.
Warning: Wire top.\cnt [6] is used but has no driver.
Warning: Wire top.\cnt [5] is used but has no driver.
Warning: Wire top.\cnt [4] is used but has no driver.
Warning: Wire top.\cnt [3] is used but has no driver.
Warning: Wire top.\cnt [2] is used but has no driver.
Warning: Wire top.\cnt [1] is used but has no driver.
Warning: Wire top.\cnt [0] is used but has no driver.
Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000'
ERROR: Signal difference
Expected error pattern 'Signal difference' found !!!
Passed sim_counter.ys
Passed sizebits.ys
Passed splice.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/sat'
cd tests/sim && bash run-test.sh
Generate FST for sim models
Test tb_adff
FST info: dumpfile tb_adff.fst opened for output.
tb/tb_adff.v:38: $finish called at 110 (1ns)
Test tb_adffe
FST info: dumpfile tb_adffe.fst opened for output.
tb/tb_adffe.v:56: $finish called at 190 (1ns)
Test tb_adlatch
FST info: dumpfile tb_adlatch.fst opened for output.
tb/tb_adlatch.v:68: $finish called at 250 (1ns)
Test tb_aldff
FST info: dumpfile tb_aldff.fst opened for output.
tb/tb_aldff.v:71: $finish called at 270 (1ns)
Test tb_aldffe
FST info: dumpfile tb_aldffe.fst opened for output.
tb/tb_aldffe.v:73: $finish called at 270 (1ns)
Test tb_dff
FST info: dumpfile tb_dff.fst opened for output.
tb/tb_dff.v:45: $finish called at 150 (1ns)
Test tb_dffe
FST info: dumpfile tb_dffe.fst opened for output.
tb/tb_dffe.v:40: $finish called at 120 (1ns)
Test tb_dffsr
FST info: dumpfile tb_dffsr.fst opened for output.
tb/tb_dffsr.v:67: $finish called at 250 (1ns)
Test tb_dlatch
FST info: dumpfile tb_dlatch.fst opened for output.
tb/tb_dlatch.v:48: $finish called at 160 (1ns)
Test tb_dlatchsr
FST info: dumpfile tb_dlatchsr.fst opened for output.
tb/tb_dlatchsr.v:63: $finish called at 250 (1ns)
Test tb_sdff
FST info: dumpfile tb_sdff.fst opened for output.
tb/tb_sdff.v:46: $finish called at 150 (1ns)
Test tb_sdffce
FST info: dumpfile tb_sdffce.fst opened for output.
tb/tb_sdffce.v:77: $finish called at 300 (1ns)
Test tb_sdffe
FST info: dumpfile tb_sdffe.fst opened for output.
tb/tb_sdffe.v:68: $finish called at 250 (1ns)
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/sim'
Passed sim_adff.ys
Passed sim_adffe.ys
Passed sim_adlatch.ys
Warning: Async reset value `\ad' is not constant!
Passed sim_aldff.ys
Warning: Async reset value `\ad' is not constant!
Passed sim_aldffe.ys
Passed sim_dff.ys
Passed sim_dffe.ys
Warning: Complex async reset for dff `\q'.
Passed sim_dffsr.ys
Passed sim_dlatch.ys
Passed sim_dlatchsr.ys
Passed sim_sdff.ys
Passed sim_sdffce.ys
Passed sim_sdffe.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/sim'
cd tests/svinterfaces && bash run-test.sh "-S 314159265359"
Test: svinterface1 -> svinterface1_tb.v:50: $finish called at 420000 (10ps)
svinterface1_tb.v:50: $finish called at 420000 (10ps)
ok
Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps)
svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps)
ERROR!
Test: load_and_derive ->ok
Test: resolve_types ->ok
cd tests/svtypes && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/svtypes'
Passed enum_simple.ys
Passed logic_rom.ys
<<EOT:7: ERROR: Insufficient number of array indices for a.
Expected error pattern 'Insufficient number of array indices for a.' found !!!
Passed multirange_subarray_access.ys
<<EOT:1: ERROR: Static cast with zero or negative size!
Expected error pattern 'Static cast with zero or negative size' found !!!
Passed static_cast_negative.ys
<<EOT:1: ERROR: Static cast with non constant expression!
Expected error pattern 'Static cast with non constant expression' found !!!
Passed static_cast_nonconst.ys
<<EOT:1: ERROR: Static cast is only supported in SystemVerilog mode.
Expected error pattern 'Static cast is only supported in SystemVerilog mode' found !!!
Passed static_cast_verilog.ys
<<EOT:1: ERROR: Static cast with zero or negative size!
Expected error pattern 'Static cast with zero or negative size' found !!!
Passed static_cast_zero.ys
Passed struct_dynamic_range.ys
Warning: reg '\var_12' is assigned in a continuous assignment at typedef_initial_and_assign.sv:67.9-67.19.
Warning: reg '\var_13' is assigned in a continuous assignment at typedef_initial_and_assign.sv:71.9-71.19.
Warning: reg '\var_14' is assigned in a continuous assignment at typedef_initial_and_assign.sv:74.9-74.19.
Warning: reg '\var_15' is assigned in a continuous assignment at typedef_initial_and_assign.sv:78.9-78.19.
Warning: reg '\var_16' is assigned in a continuous assignment at typedef_initial_and_assign.sv:81.9-81.19.
Warning: reg '\var_17' is assigned in a continuous assignment at typedef_initial_and_assign.sv:85.9-85.19.
Warning: reg '\var_18' is assigned in a continuous assignment at typedef_initial_and_assign.sv:88.9-88.19.
Warning: reg '\var_19' is assigned in a continuous assignment at typedef_initial_and_assign.sv:92.9-92.19.
Passed typedef_initial_and_assign.ys
Passed typedef_memory.ys
Passed typedef_memory_2.ys
Passed typedef_struct_port.ys
Passed multirange_array.sv
Passed static_cast_simple.sv
struct_array.sv:22: Warning: Range [3:-4] select out of bounds on signal `\s': Setting 4 LSB bits to undef.
struct_array.sv:23: Warning: Range select [23:16] out of bounds on signal `\s': Setting all 8 result bits to undef.
struct_array.sv:24: Warning: Range [19:12] select out of bounds on signal `\s': Setting 4 MSB bits to undef.
struct_array.sv:15: Warning: Range [-1:-8] select out of bounds on signal `\s': Setting 8 LSB bits to undef.
Passed struct_array.sv
Passed struct_simple.sv
Passed struct_sizebits.sv
Passed typedef_package.sv
Passed typedef_param.sv
Passed typedef_scopes.sv
Passed typedef_simple.sv
Passed typedef_struct.sv
Passed union_simple.sv
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/svtypes'
cd tests/proc && bash run-test.sh
Running bug2619.ys..
Running bug2656.ys..
Warning: wire '\q1' is assigned in a block at <<EOT:8.3-8.11.
Warning: wire '\q2' is assigned in a block at <<EOT:12.3-12.10.
Warning: wire '\q2' is assigned in a block at <<EOT:14.3-14.11.
Running bug2962.ys..
Running bug_1268.ys..
Running clean_undef_case.ys..
Running proc_rom.ys..
Warning: wire '\d' is assigned in a block at <<EOT:7.10-7.20.
Warning: wire '\d' is assigned in a block at <<EOT:8.10-8.20.
Warning: wire '\d' is assigned in a block at <<EOT:9.10-9.20.
Warning: wire '\d' is assigned in a block at <<EOT:10.10-10.20.
Warning: wire '\d' is assigned in a block at <<EOT:11.10-11.20.
Warning: wire '\d' is assigned in a block at <<EOT:12.10-12.20.
Warning: wire '\d' is assigned in a block at <<EOT:13.10-13.20.
Warning: wire '\d' is assigned in a block at <<EOT:14.10-14.20.
Warning: wire '\d' is assigned in a block at <<EOT:15.10-15.20.
Warning: wire '\d' is assigned in a block at <<EOT:16.10-16.20.
Warning: wire '\d' is assigned in a block at <<EOT:17.10-17.20.
Warning: wire '\d' is assigned in a block at <<EOT:18.10-18.20.
Warning: wire '\d' is assigned in a block at <<EOT:19.10-19.20.
Warning: wire '\d' is assigned in a block at <<EOT:20.10-20.20.
Warning: wire '\d' is assigned in a block at <<EOT:21.10-21.20.
Warning: wire '\d' is assigned in a block at <<EOT:22.10-22.20.
Warning: wire '\d' is assigned in a block at <<EOT:25.3-25.9.
Warning: wire '\d' is assigned in a block at <<EOT:20.13-20.23.
Warning: wire '\d' is assigned in a block at <<EOT:23.3-23.9.
Warning: wire '\d' is assigned in a block at <<EOT:7.7-7.17.
Warning: wire '\d' is assigned in a block at <<EOT:8.7-8.17.
Warning: wire '\d' is assigned in a block at <<EOT:9.7-9.17.
Warning: wire '\d' is assigned in a block at <<EOT:10.7-10.17.
Warning: wire '\d' is assigned in a block at <<EOT:11.7-11.17.
Warning: wire '\d' is assigned in a block at <<EOT:12.7-12.17.
Warning: wire '\d' is assigned in a block at <<EOT:13.7-13.17.
Warning: wire '\d' is assigned in a block at <<EOT:14.7-14.17.
Warning: wire '\d' is assigned in a block at <<EOT:15.7-15.17.
Warning: wire '\d' is assigned in a block at <<EOT:16.7-16.17.
Warning: wire '\d' is assigned in a block at <<EOT:17.8-17.18.
Warning: wire '\d' is assigned in a block at <<EOT:18.8-18.18.
Warning: wire '\d' is assigned in a block at <<EOT:19.8-19.18.
Warning: wire '\d' is assigned in a block at <<EOT:7.9-7.19.
Warning: wire '\d' is assigned in a block at <<EOT:8.9-8.19.
Warning: wire '\d' is assigned in a block at <<EOT:9.9-9.19.
Warning: wire '\d' is assigned in a block at <<EOT:10.9-10.19.
Warning: wire '\d' is assigned in a block at <<EOT:11.9-11.19.
Warning: wire '\d' is assigned in a block at <<EOT:12.9-12.19.
Warning: wire '\d' is assigned in a block at <<EOT:13.9-13.19.
Warning: wire '\d' is assigned in a block at <<EOT:14.9-14.19.
Warning: wire '\d' is assigned in a block at <<EOT:15.9-15.19.
Warning: wire '\d' is assigned in a block at <<EOT:16.9-16.19.
Warning: wire '\d' is assigned in a block at <<EOT:17.9-17.19.
Warning: wire '\d' is assigned in a block at <<EOT:18.9-18.19.
Warning: wire '\d' is assigned in a block at <<EOT:19.9-19.19.
Warning: wire '\d' is assigned in a block at <<EOT:20.9-20.19.
Warning: wire '\d' is assigned in a block at <<EOT:21.9-21.19.
Warning: wire '\d' is assigned in a block at <<EOT:22.9-22.19.
Running rmdead.ys..
cd tests/blif && bash run-test.sh
Running bug2729.ys..
Running bug3374.ys..
ERROR: Syntax error in line 1!
Expected error pattern 'Syntax error in line 1!' found !!!
Running bug3385.ys..
ERROR: Syntax error in line 4: names' input plane must have fewer than 13 signals.
Expected error pattern 'Syntax error in line 4: names' input plane must have fewer than 13 signals.' found !!!
cd tests/opt && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/opt'
Passed bug1525.ys
Passed bug1758.ys
Passed bug1854.ys
Passed bug2010.ys
Passed bug2221.ys
Passed bug2311.ys
Passed bug2318.ys
Passed bug2623.ys
Passed bug2765.ys
Passed bug2766.ys
Passed bug2824.ys
Passed bug2920.ys
Passed bug3047.ys
Passed bug3117.ys
Passed bug3848.ys
Passed bug3867.ys
Passed memory_bmux2rom.ys
Passed memory_dff_trans.ys
Passed memory_map_offset.ys
Passed opt_clean_init.ys
Passed opt_clean_mem.ys
Passed opt_dff_arst.ys
Passed opt_dff_clk.ys
Passed opt_dff_const.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:2)
Passed opt_dff_dffmux.ys
<<EOT:19: Warning: Range select [13:12] out of bounds on signal `\Q': Setting all 2 result bits to undef.
<<EOT:20: Warning: Range select [15:14] out of bounds on signal `\Q': Setting all 2 result bits to undef.
Passed opt_dff_en.ys
Passed opt_dff_mux.ys
<<EOT:24: Warning: Range select [21:20] out of bounds on signal `\Q': Setting all 2 result bits to undef.
<<EOT:25: Warning: Range select [23:22] out of bounds on signal `\Q': Setting all 2 result bits to undef.
Passed opt_dff_qd.ys
Passed opt_dff_sr.ys
Passed opt_dff_srst.ys
Passed opt_expr.ys
Passed opt_expr_alu.ys
Passed opt_expr_and.ys
Passed opt_expr_cmp.ys
Warning: wire '\a' is assigned in a block at <<EOT:4.2-4.8.
Warning: wire '\a' is assigned in a block at <<EOT:5.2-5.8.
Warning: wire '\a' is assigned in a block at <<EOT:4.9-4.15.
Warning: wire '\a' is assigned in a block at <<EOT:5.9-5.15.
Passed opt_expr_combined_assign.ys
Passed opt_expr_constconn.ys
Passed opt_expr_consumex.ys
Passed opt_expr_or.ys
Passed opt_expr_xnor.ys
Passed opt_expr_xor.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:41)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:86)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:87)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2153)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2154)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2155)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2156)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2157)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2158)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2925)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2926)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2988)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2989)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:2990)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:3203)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/ice40/cells_sim.v:3210)
Passed opt_lut.ys
Passed opt_lut_elim.ys
Passed opt_lut_ins.ys
Passed opt_lut_port.ys
Passed opt_mem_feedback.ys
Passed opt_mem_priority.ys
Passed opt_merge_init.ys
Passed opt_merge_keep.ys
Passed opt_reduce_bmux.ys
Passed opt_reduce_demux.ys
Warning: Wire opt_rmdff_test.\Q [22] is used but has no driver.
Passed opt_rmdff.ys
Passed opt_rmdff_sat.ys
Passed opt_share_add_sub.ys
Passed opt_share_bug2334.ys
Passed opt_share_bug2335.ys
Passed opt_share_bug2336.ys
Passed opt_share_bug2538.ys
Passed opt_share_cat.ys
Passed opt_share_cat_multiuser.ys
Passed opt_share_diff_port_widths.ys
Passed opt_share_extend.ys
Passed opt_share_large_pmux_cat.ys
Passed opt_share_large_pmux_cat_multipart.ys
Passed opt_share_large_pmux_multipart.ys
Passed opt_share_large_pmux_part.ys
Passed opt_share_mux_tree.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/opt'
cd tests/aiger && bash run-test.sh "-A /usr/bin/abc"
Checking and_.aag.
Checking buffer.aag.
Checking cnt1.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking cnt1e.aag.
Checking empty.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Warning: The current network has no primary outputs. Some commands may not work correctly.
Checking false.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking halfadder.aag.
Checking inverter.aag.
Checking notcnt1.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking notcnt1e.aag.
Checking or_.aag.
Checking symbols.aag.
Checking toggle-re.aag.
Checking toggle.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking true.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking and_.aig.
Checking buffer.aig.
Checking cnt1.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking cnt1e.aig.
Checking empty.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Warning: The current network has no primary outputs. Some commands may not work correctly.
Checking false.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking halfadder.aig.
Checking inverter.aig.
Checking notcnt1.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking notcnt1e.aig.
Checking or_.aig.
Checking symbols.aig.
Checking toggle-re.aig.
Checking toggle.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking true.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Running neg.ys.
cd tests/arch && bash run-test.sh
Running syntax check on arch sim models
Test ../../techlibs/achronix/speedster22i/cells_sim.v -> ok
Test ../../techlibs/anlogic/cells_sim.v -> ok
Test ../../techlibs/coolrunner2/cells_sim.v -> ok
Test ../../techlibs/ecp5/cells_sim.v -> ok
Test ../../techlibs/efinix/cells_sim.v -> ok
Test ../../techlibs/gatemate/cells_sim.v -> ok
Test ../../techlibs/gowin/cells_sim.v -> ok
Test ../../techlibs/greenpak4/cells_sim.v -> ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
 ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
 ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
 ok
Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok
Test ../../techlibs/intel/max10/cells_sim.v -> ok
Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok
Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok
Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok
Test ../../techlibs/nexus/cells_sim.v -> ok
Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v -> ok
Test ../../techlibs/quicklogic/common/cells_sim.v -> ok
Test ../../techlibs/quicklogic/pp3/cells_sim.v -> ok
Test ../../techlibs/sf2/cells_sim.v -> ok
Test ../../techlibs/xilinx/cells_sim.v -> ok
Test ../../techlibs/common/simcells.v -> ok
Test ../../techlibs/common/simlib.v -> ok
cd tests/arch/ice40 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/ice40'
Passed add_sub.ys
Passed adffs.ys
Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits.
Passed bug1597.ys
Passed bug1598.ys
Passed bug1626.ys
Passed bug1644.ys
Passed bug2061.ys
Passed counter.ys
Passed dffs.ys
Passed dpram.ys
Passed fsm.ys
Passed ice40_dsp.ys
Passed ice40_opt.ys
Passed ice40_wrapcarry.ys
Passed latches.ys
Passed logic.ys
Passed macc.ys
Passed memories.ys
Passed mul.ys
Passed mux.ys
Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15.
Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16.
Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21.
Passed rom.ys
Passed shifter.ys
Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25.
Passed spram.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/ice40'
cd tests/arch/xilinx && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/xilinx'
Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Passed abc9_dff.ys
Warning: Shift register inference not yet supported for family xc3s.
Passed add_sub.ys
Passed adffs.ys
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits.
Warning: Selection "asym_ram_sdp_read_wider" did not match any module.
Passed asym_ram_sdp.ys
Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits.
Passed attributes_test.ys
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits.
Passed blockram.ys
Passed bug1460.ys
Passed bug1462.ys
Passed bug1480.ys
Passed bug1598.ys
Warning: Wire top.\t is used but has no driver.
Warning: Wire top.\in is used but has no driver.
Passed bug1605.ys
Passed bug3670.ys
Passed counter.ys
Passed dffs.ys
Passed dsp_abc9.ys
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed dsp_cascade.ys
Passed dsp_fastfir.ys
Passed dsp_simd.ys
Warning: Shift register inference not yet supported for family xc3se.
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Warning: Shift register inference not yet supported for family xc3s.
Passed lutram.ys
Passed macc.ys
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed mul.ys
Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed mul_unsigned.ys
Passed mux.ys
Warning: Shift register inference not yet supported for family xc3se.
Passed mux_lut4.ys
Passed nosrl.ys
Passed opt_lut_ins.ys
Passed pmgen_xilinx_srl.ys
Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits.
Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits.
Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits.
Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits.
Passed priority_memory.ys
Passed shifter.ys
Passed tribuf.ys
Passed xilinx_dffopt.ys
Passed xilinx_dsp.ys
Passed xilinx_srl.ys
Passed macc.sh
Passed tribuf.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/xilinx'
cd tests/arch/ecp5 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/ecp5'
Passed add_sub.ys
Passed adffs.ys
Passed bug1459.ys
Passed bug1598.ys
Passed bug1630.ys
Warning: Literal has a width of 16 bit, but value requires 184 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 183 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 182 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 165 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 152 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 126 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 108 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 150 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 164 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 181 bit. (<<EOT:1)
Passed bug1836.ys
Passed bug2409.ys
Warning: Whitebox '$paramod\TRELLIS_FF\REGSET=t24'010100110100010101010100' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Passed bug2731.ys
Passed counter.ys
Passed dffs.ys
Passed dpram.ys
Passed fsm.ys
Passed latches.ys
Passed latches_abc9.ys
Passed logic.ys
Passed lutram.ys
Passed macc.ys
Passed memories.ys
Passed mul.ys
Passed mux.ys
Passed opt_lut_ins.ys
Warning: wire '\data' is assigned in a block at rom.v:9.5-9.15.
Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
Warning: wire '\data' is assigned in a block at rom.v:12.6-12.16.
Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
Warning: wire '\data' is assigned in a block at rom.v:15.11-15.21.
Passed rom.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/ecp5'
cd tests/arch/machxo2 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/machxo2'
Passed add_sub.ys
Passed adffs.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/machxo2'
cd tests/arch/efinix && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/efinix'
Passed add_sub.ys
Passed adffs.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/efinix'
cd tests/arch/anlogic && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/anlogic'
Passed add_sub.ys
Passed blockram.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/anlogic'
cd tests/arch/gowin && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/gowin'
Passed add_sub.ys
Passed adffs.ys
Passed compare.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
ERROR: FF myDFFP.$auto$ff.cc:266:slice$928 (type $_DFF_PP1_) cannot be legalized: unsupported initial value and async reset value combination
Expected error pattern 'unsupported initial value and async reset value combination' found !!!
Passed init-error.ys
Passed init.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/gowin'
cd tests/arch/intel_alm && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/intel_alm'
Passed add_sub.ys
Passed adffs.ys
Passed blockram.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed logic.ys
Passed lutram.ys
Passed mul.ys
Passed mux.ys
Passed quartus_ice.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/intel_alm'
cd tests/arch/nexus && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/nexus'
Passed add_sub.ys
Passed adffs.ys
Passed blockram.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed logic.ys
Passed lutram.ys
Passed mul.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/nexus'
cd tests/arch/quicklogic/pp3 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/quicklogic/pp3'
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed add_sub.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed adffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed counter.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed dffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed fsm.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed latches.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed logic.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed mux.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/quicklogic/pp3'
cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/quicklogic/qlf_k6n10f'
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed add_sub.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Wire adff.q has an unprocessed 'init' attribute.
Warning: Wire adffn.q has an unprocessed 'init' attribute.
Warning: Wire dffs.q has an unprocessed 'init' attribute.
Warning: Wire ndffnr.q has an unprocessed 'init' attribute.
Passed adffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed counter.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Wire my_dffe.q has an unprocessed 'init' attribute.
Passed dffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed dsp.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed fsm.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed latches.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed logic.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2663: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_RDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2709: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_RDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Range [4:1] select out of bounds on signal `\PORT_A1_WR_BE': Setting 3 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Ignoring assignment to constant bits:
    old assignment: { 3'x \PORT_A1_WR_BE [1] } = 4'0000
    new assignment: \PORT_A1_WR_BE [1] = 1'0.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Range [3:0] select out of bounds on signal `\PORT_A1_WR_BE': Setting 2 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Ignoring assignment to constant bits:
    old assignment: { 2'x \PORT_A1_WR_BE } = \PORT_A1_WR_BE_i
    new assignment: \PORT_A1_WR_BE = \PORT_A1_WR_BE_i [1:0].
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Range [4:1] select out of bounds on signal `\PORT_B1_WR_BE': Setting 3 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Ignoring assignment to constant bits:
    old assignment: { 3'x \PORT_B1_WR_BE [1] } = 4'0000
    new assignment: \PORT_B1_WR_BE [1] = 1'0.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Range [3:0] select out of bounds on signal `\PORT_B1_WR_BE': Setting 2 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Ignoring assignment to constant bits:
    old assignment: { 2'x \PORT_B1_WR_BE } = \PORT_B1_WR_BE_i
    new assignment: \PORT_B1_WR_BE = \PORT_B1_WR_BE_i [1:0].
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Range [36:17] select out of bounds on signal `\PORT_A1_WDATA': Setting 19 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Ignoring assignment to constant bits:
    old assignment: { 19'x \PORT_A1_WDATA [17] } = 20'00000000000000000000
    new assignment: \PORT_A1_WDATA [17] = 1'0.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_WDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Ignoring assignment to constant bits:
    old assignment: { 18'x \PORT_A1_WDATA } = \PORT_A1_WR_DATA_i
    new assignment: \PORT_A1_WDATA = \PORT_A1_WR_DATA_i [17:0].
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Range [36:17] select out of bounds on signal `\PORT_B1_WDATA': Setting 19 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Ignoring assignment to constant bits:
    old assignment: { 19'x \PORT_B1_WDATA [17] } = 20'00000000000000000000
    new assignment: \PORT_B1_WDATA [17] = 1'0.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_WDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Ignoring assignment to constant bits:
    old assignment: { 18'x \PORT_B1_WDATA } = \PORT_B1_WR_DATA_i
    new assignment: \PORT_B1_WDATA = \PORT_B1_WR_DATA_i [17:0].
Warning: Complex async reset for dff `\Q'.
Warning: Drivers conflicting with a constant 1'0 driver:
    module input PORT_A1_WR_BE_i[1]
    module input PORT_A1_WR_DATA_i[17]
    module input PORT_B1_WR_BE_i[1]
    module input PORT_B1_WR_DATA_i[17]
Passed meminit.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed mux.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Wire TB.\rq_b [35] is used but has no driver.
Warning: Wire TB.\rq_b [34] is used but has no driver.
Warning: Wire TB.\rq_b [33] is used but has no driver.
Warning: Wire TB.\rq_b [32] is used but has no driver.
Warning: Wire TB.\rq_b [31] is used but has no driver.
Warning: Wire TB.\rq_b [30] is used but has no driver.
Warning: Wire TB.\rq_b [29] is used but has no driver.
Warning: Wire TB.\rq_b [28] is used but has no driver.
Warning: Wire TB.\rq_b [27] is used but has no driver.
Warning: Wire TB.\rq_b [26] is used but has no driver.
Warning: Wire TB.\rq_b [25] is used but has no driver.
Warning: Wire TB.\rq_b [24] is used but has no driver.
Warning: Wire TB.\rq_b [23] is used but has no driver.
Warning: Wire TB.\rq_b [22] is used but has no driver.
Warning: Wire TB.\rq_b [21] is used but has no driver.
Warning: Wire TB.\rq_b [20] is used but has no driver.
Warning: Wire TB.\rq_b [19] is used but has no driver.
Warning: Wire TB.\rq_b [18] is used but has no driver.
Warning: Wire TB.\rq_b [17] is used but has no driver.
Warning: Wire TB.\rq_b [16] is used but has no driver.
Warning: Wire TB.\rq_b [15] is used but has no driver.
Warning: Wire TB.\rq_b [14] is used but has no driver.
Warning: Wire TB.\rq_b [13] is used but has no driver.
Warning: Wire TB.\rq_b [12] is used but has no driver.
Warning: Wire TB.\rq_b [11] is used but has no driver.
Warning: Wire TB.\rq_b [10] is used but has no driver.
Warning: Wire TB.\rq_b [9] is used but has no driver.
Warning: Wire TB.\rq_b [8] is used but has no driver.
Warning: Wire TB.\rq_b [7] is used but has no driver.
Warning: Wire TB.\rq_b [6] is used but has no driver.
Warning: Wire TB.\rq_b [5] is used but has no driver.
Warning: Wire TB.\rq_b [4] is used but has no driver.
Warning: Wire TB.\rq_b [3] is used but has no driver.
Warning: Wire TB.\rq_b [2] is used but has no driver.
Warning: Wire TB.\rq_b [1] is used but has no driver.
Warning: Wire TB.\rq_b [0] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [35] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [34] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [33] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [32] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [31] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [30] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [29] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [28] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [27] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [26] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [25] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [24] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [23] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [22] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [21] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [20] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [19] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [18] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [17] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [16] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [15] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [14] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [13] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [12] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [11] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [10] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [9] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [8] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$17889 [7] is used but has no driver.
Warning: Resizing cell port TB.uut.address_in_w from 11 bits to 10 bits.
Warning: Resizing cell port TB.uut.data_in from 18 bits to 36 bits.
Warning: Resizing cell port TB.uut.address_in_w from 10 bits to 8 bits.
Warning: Resizing cell port TB.uut.data_in from 8 bits to 32 bits.
Warning: Resizing cell port TB.uut.data_out from 18 bits to 36 bits.
Warning: Resizing cell port TB.uut.address_in_r from 11 bits to 10 bits.
Passed t_mem0.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Resizing cell port TB.uut.data_out from 8 bits to 32 bits.
Warning: Resizing cell port TB.uut.address_in_r from 10 bits to 8 bits.
Warning: Wire TB.\rq_b [7] is used but has no driver.
Warning: Wire TB.\rq_b [6] is used but has no driver.
Warning: Wire TB.\rq_b [5] is used but has no driver.
Warning: Wire TB.\rq_b [4] is used but has no driver.
Warning: Wire TB.\rq_b [3] is used but has no driver.
Warning: Wire TB.\rq_b [2] is used but has no driver.
Warning: Wire TB.\rq_b [1] is used but has no driver.
Warning: Wire TB.\rq_b [0] is used but has no driver.
Passed t_mem1.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem2.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem3.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem4.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem5.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem6.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/quicklogic/qlf_k6n10f'
cd tests/arch/gatemate && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/gatemate'
Passed add_sub.ys
Passed adffs.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Passed luttrees.ys
Passed memory.ys
Passed mul.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/arch/gatemate'
cd tests/rpc && bash run-test.sh
Running exec.ys..
cd tests/memfile && bash run-test.sh
Running from the parent directory with content1.dat
Running from the parent directory with temp/content2.dat
Running from the parent directory with memfile/temp/content2.dat
Running from the same directory with content1.dat
Running from the same directory with temp/content2.dat
Running from a child directory with content1.dat
Running from a child directory with temp/content2.dat
Running from a child directory with content2.dat
Checking a failure when zero length filename is provided
memory.v:15: ERROR: Can not open file `` for \$readmemb.
Execution failed, which is OK.
Checking a failure when not existing filename is provided
memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb.
Execution failed, which is OK.
cd tests/verilog && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/verilog'
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Passed absurd_width.ys
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Passed absurd_width_const.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_1.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_2.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_3.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$3.y' from always_comb process `\top.$proc$<<EOF:0$4'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process' found !!!
Passed always_comb_latch_4.ys
Passed always_comb_nolatch_1.ys
Passed always_comb_nolatch_2.ys
Passed always_comb_nolatch_3.ys
Passed always_comb_nolatch_4.ys
Passed always_comb_nolatch_5.ys
Passed always_comb_nolatch_6.ys
Passed asgn_expr.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_1.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_2.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_3.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_4.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_5.ys
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Passed asgn_expr_not_sv_1.ys
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Passed asgn_expr_not_sv_2.ys
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Passed asgn_expr_not_sv_3.ys
<<EOF:3: ERROR: syntax error, unexpected TOK_ID
Expected error pattern 'syntax error, unexpected TOK_ID' found !!!
Passed asgn_expr_not_sv_4.ys
Passed atom_type_signedness.ys
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
Passed block_end_label_only.ys
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed block_end_label_wrong.ys
<<EOT:5: ERROR: Begin label (a) and end label (b) don't match.
Expected error pattern 'Begin label \(a\) and end label \(b\) don't match\.' found !!!
Passed block_labels.ys
Passed bug2037.ys
<<EOT:6: ERROR: syntax error, unexpected TOK_ENDTASK, expecting ';'
Expected error pattern 'syntax error, unexpected TOK_ENDTASK, expecting ';'' found !!!
Passed bug2042-sv.ys
<<EOT:5: ERROR: task/function argument direction missing
Expected error pattern 'task/function argument direction missing' found !!!
Passed bug2042.ys
<<EOT:6: ERROR: Failed to detect width for identifier \genblk1.y!
Expected error pattern 'Failed to detect width for identifier \\genblk1\.y!' found !!!
Passed bug2493.ys
Passed bug656.ys
<<EOT:4: ERROR: Cannot add procedural assertion `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add procedural assertion `\\x' because a signal with the same name was already created' found !!!
Passed conflict_assert.ys
<<EOT:5: ERROR: Cannot add cell `\x' because a memory with the same name was already created at <<EOT:4.15-4.16!
Expected error pattern 'Cannot add cell `\\x' because a memory with the same name was already created' found !!!
Passed conflict_cell_memory.ys
<<EOT:0: ERROR: Cannot add interface port `\i' because a signal with the same name was already created at <<EOT:9.10-9.11!
Expected error pattern 'Cannot add interface port `\\i' because a signal with the same name was already created' found !!!
Passed conflict_interface_port.ys
<<EOT:3: ERROR: Cannot add memory `\x' because a signal with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add memory `\\x' because a signal with the same name was already created' found !!!
Passed conflict_memory_wire.ys
<<EOT:3: Warning: Ignoring assignment to constant bits:
    old assignment: 2 = 1
    new assignment: { } = { }.
<<EOT:4: ERROR: Cannot add pwire `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add pwire `\\x' because a signal with the same name was already created' found !!!
Passed conflict_pwire.ys
<<EOT:3: ERROR: Cannot add signal `\x' because a memory with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add signal `\\x' because a memory with the same name was already created' found !!!
Passed conflict_wire_memory.ys
Passed const_arst.ys
Warning: Complex async reset for dff `\q'.
Passed const_sr.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Passed delay_mintypmax.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Passed delay_risefall.ys
Passed delay_time_scale.ys
Passed doubleslash.ys
<<EOT:4: ERROR: For loop variable declaration is missing initialization!
Expected error pattern 'For loop variable declaration is missing initialization!' found !!!
Passed for_decl_no_init.ys
<<EOT:4: ERROR: For loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'For loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
Passed for_decl_no_sv.ys
Passed for_decl_shadow.ys
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!
Passed func_arg_mismatch_1.ys
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
Passed func_arg_mismatch_2.ys
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!
Passed func_arg_mismatch_3.ys
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
Passed func_arg_mismatch_4.ys
Passed func_tern_hint.ys
Passed func_typename_ret.ys
Passed func_upto.ys
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
Passed gen_block_end_label_only.ys
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed gen_block_end_label_wrong.ys
Passed genblk_case.ys
<<EOT:4: ERROR: Cannot declare module port `\x' within a generate block.
Expected error pattern 'Cannot declare module port `\\x' within a generate block\.' found !!!
Passed genblk_port_decl.ys
<<EOT:2: ERROR: Generate for loop variable declaration is missing initialization!
Expected error pattern 'Generate for loop variable declaration is missing initialization!' found !!!
Passed genfor_decl_no_init.ys
<<EOT:2: ERROR: Generate for loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'Generate for loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
Passed genfor_decl_no_sv.ys
Passed genvar_loop_decl_1.ys
Passed genvar_loop_decl_2.ys
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:13.12-13.21.
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:27.12-27.21.
Passed genvar_loop_decl_3.ys
<<EOF:0: ERROR: Can't find object for defparam `$1`!
Expected error pattern 'Can't find object for defparam' found !!!
Passed global_parameter.ys
<<EOT:7: ERROR: Identifier `\y' is implicitly declared and `default_nettype is set to none.
Expected error pattern 'Identifier `\\y' is implicitly declared and `default_nettype is set to none' found !!!
Passed hidden_decl.ys
Passed ifdef_nest.ys
ERROR: Unterminated preprocessor conditional!
Expected error pattern 'Unterminated preprocessor conditional!' found !!!
Passed ifdef_unterminated.ys
Passed include_self.ys
Passed int_types.ys
<<EOF:3: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Passed localparam_no_default_1.ys
<<EOF:2: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Passed localparam_no_default_2.ys
Passed macro_arg_tromp.ys
ERROR: Expected to find '(' to begin macro arguments for 'MACRO', but instead found ';'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'' found !!!
Passed macro_unapplied.ys
ERROR: Expected to find '(' to begin macro arguments for 'foo', but instead found '\x0a'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'' found !!!
Passed macro_unapplied_newline.ys
Passed mem_bounds.ys
<<EOF:3: ERROR: Module name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Module name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed module_end_label.ys
Passed net_types.ys
<<EOF:3: ERROR: Package name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Package name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed package_end_label.ys
Passed package_task_func.ys
Passed param_int_types.ys
Passed param_no_default.ys
<<EOF:3: ERROR: Parameter defaults can only be omitted in SystemVerilog mode!
Expected error pattern 'Parameter defaults can only be omitted in SystemVerilog mode!' found !!!
Passed param_no_default_not_svmode.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_1.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_2.ys
<<EOF:2: ERROR: Parameter `\Y' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\Y' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_3.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_4.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_5.ys
Passed parameters_across_files.ys
Passed past_signedness.ys
Passed port_int_types.ys
Passed prefix.ys
Passed sign_array_query.ys
Passed size_cast.ys
Passed struct_access.ys
<<EOT:6: ERROR: syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT
Expected error pattern 'syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT' found !!!
Passed task_attr.ys
Passed typedef_across_files.ys
Passed typedef_const_shadow.ys
Passed typedef_legacy_conflict.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:17)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:21)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:25)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:30)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:34)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:38)
Passed unbased_unsized.ys
Warning: Resizing cell port top.pt.inp from 32 bits to 64 bits.
Passed unbased_unsized_shift.ys
Warning: Resizing cell port gate.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt1.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt1.out from 64 bits to 40 bits.
Passed unbased_unsized_tern.ys
ERROR: Found `else outside of macro conditional branch!
Expected error pattern 'Found `else outside of macro conditional branch!' found !!!
Passed unmatched_else.ys
ERROR: Found `elsif outside of macro conditional branch!
Expected error pattern 'Found `elsif outside of macro conditional branch!' found !!!
Passed unmatched_elsif.ys
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Passed unmatched_endif.ys
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Passed unmatched_endif_2.ys
<<EOT:3: ERROR: Local declaration in unnamed block is only supported in SystemVerilog mode!
Expected error pattern 'Local declaration in unnamed block is only supported in SystemVerilog mode!' found !!!
Passed unnamed_block.ys
Passed unnamed_genblk.ys
Passed unreachable_case_sign.ys
Passed upto.ys
Warning: wire '\b' is assigned in a block at <<EOF:2.38-2.43.
Warning: wire '\b' is assigned in a block at <<EOF:3.42-3.48.
Warning: wire '\b' is assigned in a block at <<EOF:12.29-12.34.
Warning: wire '\b' is assigned in a block at <<EOF:13.33-13.39.
Warning: wire '\b' is assigned in a block at <<EOF:23.9-23.14.
Warning: wire '\b' is assigned in a block at <<EOF:24.9-24.15.
Warning: wire '\b' is assigned in a block at <<EOF:25.9-25.15.
Passed void_func.ys
Warning: wire '\wire_1' is assigned in a block at wire_and_var.sv:21.41-21.51.
Warning: reg '\reg_2' is assigned in a continuous assignment at wire_and_var.sv:22.57-22.66.
Warning: reg '\var_reg_2' is assigned in a continuous assignment at wire_and_var.sv:26.77-26.90.
Warning: wire '\wire_logic_1' is assigned in a block at wire_and_var.sv:30.65-30.81.
Warning: wire '\wire_integer_1' is assigned in a block at wire_and_var.sv:31.73-31.91.
Passed wire_and_var.ys
Passed dynamic_range_lhs.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/verilog'
cd tests/xprop && bash run-test.sh "-S 314159265359"
xprop PRNG seed: 314159265359
make[1]: Entering directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/xprop'
xprop_not_3s_5: ok
xprop_not_3s_5: ok
xprop_pos_3s_5: ok
xprop_pos_3s_5: ok
xprop_neg_3s_5: ok
xprop_neg_3s_5: ok
xprop_and_1u1_1: ok
xprop_and_1u1_1: ok
xprop_and_1s1_2: ok
xprop_and_1s1_2: ok
xprop_and_2u2_2: ok
xprop_and_2u2_2: ok
xprop_or_1u1_1: ok
xprop_or_1u1_1: ok
xprop_or_1s1_2: ok
xprop_or_1s1_2: ok
xprop_or_2u2_2: ok
xprop_or_2u2_2: ok
xprop_xor_1u1_1: ok
xprop_xor_1u1_1: ok
xprop_xor_1s1_2: ok
xprop_xor_1s1_2: ok
xprop_xor_2u2_2: ok
xprop_xor_2u2_2: ok
xprop_xnor_1u1_1: ok
xprop_xnor_1u1_1: ok
xprop_xnor_1s1_2: ok
xprop_xnor_1s1_2: ok
xprop_xnor_2u2_2: ok
xprop_xnor_2u2_2: ok
xprop_add_5u3_3: ok
xprop_add_5u3_3: ok
xprop_add_5s3_3: ok
xprop_add_5s3_3: ok
xprop_sub_5u3_3: ok
xprop_sub_5u3_3: ok
xprop_sub_5s3_3: ok
xprop_sub_5s3_3: ok
xprop_mul_5u3_3: ok
xprop_mul_5u3_3: ok
xprop_mul_5s3_3: ok
xprop_mul_5s3_3: ok
xprop_div_5u3_3: ok
xprop_div_5u3_3: ok
xprop_div_5s3_3: ok
xprop_div_5s3_3: ok
xprop_mod_5u3_3: ok
xprop_mod_5u3_3: ok
xprop_mod_5s3_3: ok
xprop_mod_5s3_3: ok
xprop_divfloor_5u3_3: ok
xprop_divfloor_5u3_3: ok
xprop_divfloor_5s3_3: ok
xprop_divfloor_5s3_3: ok
xprop_modfloor_5u3_3: ok
xprop_modfloor_5u3_3: ok
xprop_modfloor_5s3_3: ok
xprop_modfloor_5s3_3: ok
xprop_lt_5u3_2: ok
xprop_lt_5u3_2: ok
xprop_lt_5s3_2: ok
xprop_lt_5s3_2: ok
xprop_le_5u3_2: ok
xprop_le_5u3_2: ok
xprop_le_5s3_2: ok
xprop_le_5s3_2: ok
xprop_eq_5u3_2: ok
xprop_eq_5u3_2: ok
xprop_eq_5s3_2: ok
xprop_eq_5s3_2: ok
xprop_ne_5u3_2: ok
xprop_ne_5u3_2: ok
xprop_ne_5s3_2: ok
xprop_ne_5s3_2: ok
xprop_eqx_5u3_2: ok
xprop_eqx_5u3_2: ok
xprop_eqx_5s3_2: ok
xprop_eqx_5s3_2: ok
xprop_nex_5u3_2: ok
xprop_nex_5u3_2: ok
xprop_nex_5s3_2: ok
xprop_nex_5s3_2: ok
xprop_ge_5u3_2: ok
xprop_ge_5u3_2: ok
xprop_ge_5s3_2: ok
xprop_ge_5s3_2: ok
xprop_gt_5u3_2: ok
xprop_gt_5u3_2: ok
xprop_gt_5s3_2: ok
xprop_gt_5s3_2: ok
xprop_reduce_and_3u_3: ok
xprop_reduce_and_3u_3: ok
xprop_reduce_and_3s_3: ok
xprop_reduce_and_3s_3: ok
xprop_reduce_or_3u_3: ok
xprop_reduce_or_3u_3: ok
xprop_reduce_or_3s_3: ok
xprop_reduce_or_3s_3: ok
xprop_reduce_xor_3u_3: ok
xprop_reduce_xor_3u_3: ok
xprop_reduce_xor_3s_3: ok
xprop_reduce_xor_3s_3: ok
xprop_reduce_xnor_3u_3: ok
xprop_reduce_xnor_3u_3: ok
xprop_reduce_xnor_3s_3: ok
xprop_reduce_xnor_3s_3: ok
xprop_reduce_bool_1u_1: ok
xprop_reduce_bool_1u_1: ok
xprop_reduce_bool_3u_3: ok
xprop_reduce_bool_3u_3: ok
xprop_reduce_bool_3s_3: ok
xprop_reduce_bool_3s_3: ok
xprop_reduce_bool_3s_1: ok
xprop_reduce_bool_3s_1: ok
xprop_logic_not_1u_1: ok
xprop_logic_not_1u_1: ok
xprop_logic_not_3u_3: ok
xprop_logic_not_3u_3: ok
xprop_logic_not_3s_3: ok
xprop_logic_not_3s_3: ok
xprop_logic_not_3s_1: ok
xprop_logic_not_3s_1: ok
xprop_logic_and_1u1_1: ok
xprop_logic_and_1u1_1: ok
xprop_logic_and_3u3_3: ok
xprop_logic_and_3u3_3: ok
xprop_logic_and_3s3_3: ok
xprop_logic_and_3s3_3: ok
xprop_logic_and_3s3_1: ok
xprop_logic_and_3s3_1: ok
xprop_logic_or_1u1_1: ok
xprop_logic_or_1u1_1: ok
xprop_logic_or_3u3_3: ok
xprop_logic_or_3u3_3: ok
xprop_logic_or_3s3_3: ok
xprop_logic_or_3s3_3: ok
xprop_logic_or_3s3_1: ok
xprop_logic_or_3s3_1: ok
xprop_shl_4u3u_3: ok
xprop_shl_4u3u_3: ok
xprop_shl_4s3u_3: ok
xprop_shl_4s3u_3: ok
xprop_shr_4u3u_3: ok
xprop_shr_4u3u_3: ok
xprop_shr_4s3u_3: ok
xprop_shr_4s3u_3: ok
xprop_sshl_4u3u_3: ok
xprop_sshl_4u3u_3: ok
xprop_sshl_4s3u_3: ok
xprop_sshl_4s3u_3: ok
xprop_sshr_4u3u_3: ok
xprop_sshr_4u3u_3: ok
xprop_sshr_4s3u_3: ok
xprop_sshr_4s3u_3: ok
xprop_shift_4u3u_3: ok
xprop_shift_4u3u_3: ok
xprop_shift_4s3u_3: ok
xprop_shift_4s3u_3: ok
xprop_shift_4u2s_8: ok
xprop_shift_4u2s_8: ok
xprop_shift_4s2s_8: ok
xprop_shift_4s2s_8: ok
xprop_shift_4u3s_3: ok
xprop_shift_4u3s_3: ok
xprop_shift_4s3s_3: ok
xprop_shift_4s3s_3: ok
xprop_shiftx_4u2s_8: ok
xprop_shiftx_4u2s_8: ok
xprop_shiftx_4u3s_3: ok
xprop_shiftx_4u3s_3: ok
xprop_mux_1: ok
xprop_mux_1: ok
xprop_mux_3: ok
xprop_mux_3: ok
xprop_bmux_1_2: ok
xprop_bmux_1_2: ok
xprop_bmux_2_2: ok
xprop_bmux_2_2: ok
xprop_bmux_3_1: ok
xprop_bmux_3_1: ok
xprop_demux_1_2: ok
xprop_demux_1_2: ok
xprop_demux_2_2: ok
xprop_demux_2_2: ok
xprop_demux_3_1: ok
xprop_demux_3_1: ok
xprop_pmux_1_4: ok
xprop_pmux_1_4: ok
xprop_pmux_2_2: ok
xprop_pmux_2_2: ok
xprop_pmux_3_1: ok
xprop_pmux_3_1: ok
xprop_pmux_4_4: ok
xprop_pmux_4_4: ok
xprop_bwmux_1: ok
xprop_bwmux_1: ok
xprop_bwmux_3: ok
xprop_bwmux_3: ok
xprop_bweqx_1: ok
xprop_bweqx_1: ok
xprop_bweqx_3: ok
xprop_bweqx_3: ok
xprop_ff_1: ok
xprop_ff_1: ok
xprop_ff_3: ok
xprop_ff_3: ok
xprop_dff_1pd: ok
xprop_dff_1pd: ok
xprop_dff_1nd: ok
xprop_dff_1nd: ok
xprop_dff_3pd: ok
xprop_dff_3pd: ok
xprop_dff_3nd: ok
xprop_dff_3nd: ok
xprop_dffe_1pnd: ok
xprop_dffe_1pnd: ok
xprop_dffe_1nnd: ok
xprop_dffe_1nnd: ok
xprop_dffe_3pnd: ok
xprop_dffe_3pnd: ok
xprop_dffe_3nnd: ok
xprop_dffe_3nnd: ok
xprop_dffe_1ppd: ok
xprop_dffe_1ppd: ok
xprop_dffe_1npd: ok
xprop_dffe_1npd: ok
xprop_dffe_3ppd: ok
xprop_dffe_3ppd: ok
xprop_dffe_3npd: ok
xprop_dffe_3npd: ok
done
make[1]: Leaving directory '/builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/tests/xprop'
cd tests/fmt && bash run-test.sh
+ ../../yosys -p 'read_verilog initial_display.v'
+ awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}'
+ iverilog -o iverilog-initial_display initial_display.v
+ ./iverilog-initial_display
+ diff yosys-initial_display.log iverilog-initial_display.log
+ test_always_display clk -DEVENT_CLK
+ local subtest=clk
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:4$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:4$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-always_display-clk-1.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 0de35d2746, CPU: user 0.08s system 0.00s, MEM: 12.97 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 39% 2x opt_expr (0 sec), 26% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v
Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-always_display-clk-2.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: e35e8bb689, CPU: user 0.08s system 0.00s, MEM: 13.19 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 39% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ...
+ diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v
+ test_always_display clk_rst -DEVENT_CLK_RST
+ local subtest=clk_rst
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:7$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:7$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: c95608ddf0, CPU: user 0.08s system 0.00s, MEM: 13.06 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 39% 2x opt_expr (0 sec), 26% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v
Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: faf50513c3, CPU: user 0.08s system 0.00s, MEM: 13.18 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 37% 2x opt_expr (0 sec), 26% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v
+ test_always_display star -DEVENT_STAR
+ local subtest=star
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:10$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:10$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-always_display-star-1.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 7b2c5274a5, CPU: user 0.06s system 0.02s, MEM: 13.08 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 40% 2x opt_expr (0 sec), 27% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v
Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-always_display-star-2.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 8979c5de0b, CPU: user 0.06s system 0.02s, MEM: 13.22 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 39% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ...
+ diff yosys-always_display-star-1.v yosys-always_display-star-2.v
+ test_always_display clk_en -DEVENT_CLK -DCOND_EN
+ local subtest=clk_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:4$1'.
     1/1: $display$always_display.v:15$2_EN
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'.
Removing empty process `m.$proc$always_display.v:4$1'.
Cleaned up 1 empty switch.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.
-- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 4f8a3b339c, CPU: user 0.07s system 0.01s, MEM: 13.23 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 42% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v
Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
     1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'.
Cleaned up 1 empty switch.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.
-- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 51e7fa3902, CPU: user 0.07s system 0.01s, MEM: 13.23 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 41% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v
+ test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN
+ local subtest=clk_rst_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:7$1'.
     1/1: $display$always_display.v:15$2_EN
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'.
Removing empty process `m.$proc$always_display.v:7$1'.
Cleaned up 1 empty switch.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.
-- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: f9b4876f33, CPU: user 0.07s system 0.01s, MEM: 13.38 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 41% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v
Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
     1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
Cleaned up 1 empty switch.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.
-- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.09s system 0.00s, MEM: 13.32 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 42% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v
+ test_always_display star_en -DEVENT_STAR -DCOND_EN
+ local subtest=star_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:10$1'.
     1/1: $display$always_display.v:15$2_EN
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'.
Removing empty process `m.$proc$always_display.v:10$1'.
Cleaned up 1 empty switch.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.
-- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: d6a7335726, CPU: user 0.07s system 0.02s, MEM: 13.35 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 43% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' --
1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v
Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
     1/1: $write$yosys-always_display-star_en-1.v:20$2_EN
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'.
Cleaned up 1 empty switch.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.
-- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' --
4. Executing Verilog backend.
4.1. Executing BMUXMAP pass.
4.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 18895a2046, CPU: user 0.09s system 0.00s, MEM: 13.31 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 41% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ...
+ diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v
+ test_roundtrip dec_unsigned -DBASE_DEC -DSIGN=
+ local subtest=dec_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: bfb187b86d, CPU: user 0.05s system 0.02s, MEM: 13.11 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 32% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 4be9539e85, CPU: user 0.07s system 0.01s, MEM: 13.02 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 31% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_unsigned
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_unsigned-1
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_unsigned-1
+ diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log
+ diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log
+ test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed
+ local subtest=dec_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: bbdfa5ca92, CPU: user 0.06s system 0.02s, MEM: 13.08 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 34% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v
Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: b233de92a6, CPU: user 0.08s system 0.00s, MEM: 13.06 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 31% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_signed
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_signed-1
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_signed-1
+ diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log
+ diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log
+ test_roundtrip hex_unsigned -DBASE_HEX -DSIGN=
+ local subtest=hex_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 2377f2e106, CPU: user 0.07s system 0.00s, MEM: 13.12 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 33% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 06bfea69c8, CPU: user 0.06s system 0.01s, MEM: 13.18 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 32% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_unsigned
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_unsigned-1
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_unsigned-1
+ diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log
+ diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log
+ test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed
+ local subtest=hex_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 824c3b1e65, CPU: user 0.06s system 0.01s, MEM: 13.14 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 33% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v
Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: f18b3fa15b, CPU: user 0.08s system 0.00s, MEM: 13.14 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 32% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_signed
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_signed-1
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_signed-1
+ diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log
+ diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log
+ test_roundtrip oct_unsigned -DBASE_HEX -DSIGN=
+ local subtest=oct_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: b768358a65, CPU: user 0.06s system 0.01s, MEM: 12.91 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 34% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 762621cd95, CPU: user 0.05s system 0.02s, MEM: 13.24 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 32% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_unsigned
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_unsigned-1
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_unsigned-1
+ diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log
+ diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log
+ test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed
+ local subtest=oct_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 7ec82b15e3, CPU: user 0.07s system 0.00s, MEM: 13.12 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 33% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v
Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: a747b9bd4f, CPU: user 0.06s system 0.01s, MEM: 12.94 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 32% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_signed
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_signed-1
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_signed-1
+ diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log
+ diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log
+ test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=
+ local subtest=bin_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 270b564880, CPU: user 0.05s system 0.02s, MEM: 13.19 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 33% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: dc9f56cb10, CPU: user 0.06s system 0.01s, MEM: 13.20 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 32% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_unsigned
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_unsigned-1
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_unsigned-1
+ diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log
+ diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log
+ test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed
+ local subtest=bin_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --
1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 7709253822, CPU: user 0.07s system 0.00s, MEM: 13.19 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 33% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' --
1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v
Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
Cleaned up 1 empty switch.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.
-- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\m'.
End of script. Logfile hash: 7e2d8271c4, CPU: user 0.04s system 0.03s, MEM: 13.04 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 31% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_signed
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_signed-1
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_signed-1
+ diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log
+ diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log
+ test_cxxrtl always_full
+ local subtest=always_full
+ shift
+ ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc'
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' --
1. Executing Verilog-2005 frontend: always_full.v
Parsing Verilog input from `always_full.v' to AST representation.
Generating RTLIL representation for module `\always_full'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 207 redundant assignments.
Promoted 207 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\always_full.$proc$always_full.v:3$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `always_full.$proc$always_full.v:3$1'.
Cleaned up 0 empty switches.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
Removed 0 unused cells and 207 unused wires.
3. Executing CXXRTL backend.
3.1. Executing HIERARCHY pass (managing design hierarchy).
3.1.1. Finding top of design hierarchy..
root of   0 design levels: always_full         
Automatically selected always_full as design top module.
3.1.2. Analyzing design hierarchy..
Top module:  \always_full
3.1.3. Analyzing design hierarchy..
Top module:  \always_full
Removed 0 unused modules.
3.2. Executing FLATTEN pass (flatten design).
3.3. Executing PROC pass (convert processes to netlists).
3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
3.3.4. Executing PROC_INIT pass (extract init attributes).
3.3.5. Executing PROC_ARST pass (detect async resets in processes).
3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
<suppressed ~11 debug messages>
End of script. Logfile hash: 6abd135c0a, CPU: user 0.29s system 0.01s, MEM: 14.63 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 26% 2x read_verilog (0 sec), 21% 2x opt_expr (0 sec), ...
+ gcc -std=c++11 -o yosys-always_full -I../../backends/cxxrtl/runtime always_full_tb.cc -lstdc++
+ ./yosys-always_full
+ iverilog -o iverilog-always_full always_full.v always_full_tb.v
+ ./iverilog-always_full
+ grep -v '\$finish called'
+ diff iverilog-always_full.log yosys-always_full.log
+ test_cxxrtl always_comb
+ local subtest=always_comb
+ shift
+ ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc'
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' --
1. Executing Verilog-2005 frontend: always_comb.v
Parsing Verilog input from `always_comb.v' to AST representation.
Generating RTLIL representation for module `\top'.
Generating RTLIL representation for module `\sub'.
Successfully finished Verilog frontend.
2. Executing PROC pass (convert processes to netlists).
2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 4 assignments to connections.
2.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$always_comb.v:3$13'.
  Set init value: \b = 1'0
Found init rule in `\top.$proc$always_comb.v:2$12'.
  Set init value: \a = 1'0
2.5. Executing PROC_ARST pass (detect async resets in processes).
2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\sub.$proc$always_comb.v:23$15'.
     1/1: $display$always_comb.v:23$19_EN
Creating decoders for process `\top.$proc$always_comb.v:3$13'.
Creating decoders for process `\top.$proc$always_comb.v:2$12'.
Creating decoders for process `\top.$proc$always_comb.v:8$1'.
2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'.
  created $dff cell `$procdff$22' with positive edge clock.
Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'.
  created $dff cell `$procdff$23' with positive edge clock.
2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'.
Removing empty process `sub.$proc$always_comb.v:23$15'.
Removing empty process `top.$proc$always_comb.v:3$13'.
Removing empty process `top.$proc$always_comb.v:2$12'.
Removing empty process `top.$proc$always_comb.v:8$1'.
Cleaned up 1 empty switch.
2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module sub.
Optimizing module top.
Removed 0 unused cells and 7 unused wires.
3. Executing CXXRTL backend.
3.1. Executing HIERARCHY pass (managing design hierarchy).
3.1.1. Finding top of design hierarchy..
root of   0 design levels: sub                 
root of   1 design levels: top                 
Automatically selected top as design top module.
3.1.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \sub
3.1.3. Analyzing design hierarchy..
Top module:  \top
Used module:     \sub
Removed 0 unused modules.
3.2. Executing FLATTEN pass (flatten design).
Deleting now unused module sub.
<suppressed ~1 debug messages>
3.3. Executing PROC pass (convert processes to netlists).
3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.
3.3.4. Executing PROC_INIT pass (extract init attributes).
3.3.5. Executing PROC_ARST pass (detect async resets in processes).
3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~11 debug messages>
End of script. Logfile hash: 03fe26efda, CPU: user 0.10s system 0.01s, MEM: 13.29 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 32% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
+ gcc -std=c++11 -o yosys-always_comb -I../../backends/cxxrtl/runtime always_comb_tb.cc -lstdc++
+ ./yosys-always_comb
+ iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v
+ ./iverilog-always_comb
+ grep -v '\$finish called'
+ diff iverilog-always_comb.log yosys-always_comb.log
+ ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog always_full.v; prep; clean' --
1. Executing Verilog-2005 frontend: always_full.v
Parsing Verilog input from `always_full.v' to AST representation.
Generating RTLIL representation for module `\always_full'.
Successfully finished Verilog frontend.
2. Executing PREP pass.
2.1. Executing HIERARCHY pass (managing design hierarchy).
2.2. Executing PROC pass (convert processes to netlists).
2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 207 redundant assignments.
Promoted 207 assignments to connections.
2.2.4. Executing PROC_INIT pass (extract init attributes).
2.2.5. Executing PROC_ARST pass (detect async resets in processes).
2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\always_full.$proc$always_full.v:3$1'.
2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `always_full.$proc$always_full.v:3$1'.
Cleaned up 0 empty switches.
2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
2.3. Executing FUTURE pass.
2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..
Removed 0 unused cells and 207 unused wires.
<suppressed ~1 debug messages>
2.6. Executing CHECK pass (checking for obvious problems).
Checking module always_full...
Found and reported 0 problems.
2.7. Executing OPT pass (performing simple optimizations).
2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.
2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \always_full..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.
2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \always_full.
Performed a total of 0 changes.
2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.
2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..
2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
2.7.8. Finished OPT passes. (There is nothing left to do.)
2.8. Executing WREDUCE pass (reducing word size of cells).
2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..
2.10. Executing MEMORY_COLLECT pass (generating $mem cells).
2.11. Executing OPT pass (performing simple optimizations).
2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.
2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..
2.11.4. Finished fast OPT passes.
2.12. Printing statistics.
=== always_full ===
   Number of wires:                  1
   Number of wire bits:              1
   Number of public wires:           1
   Number of public wire bits:       1
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                207
     $print                        207
2.13. Executing CHECK pass (checking for obvious problems).
Checking module always_full...
Found and reported 0 problems.
-- Writing to `yosys-always_full-1.v' using backend `verilog' --
3. Executing Verilog backend.
3.1. Executing BMUXMAP pass.
3.2. Executing DEMUXMAP pass.
Dumping module `\always_full'.
End of script. Logfile hash: 78a861be63, CPU: user 0.73s system 0.04s, MEM: 13.30 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 20% 4x opt_clean (0 sec), 20% 5x opt_expr (0 sec), ...
+ iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v
+ ./iverilog-always_full-1
+ grep -v '\$finish called'
+ diff iverilog-always_full.log iverilog-always_full-1.log
+ ../../yosys -p 'read_verilog display_lm.v'
+ ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc'
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/
 Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
-- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' --
1. Executing Verilog-2005 frontend: display_lm.v
Parsing Verilog input from `display_lm.v' to AST representation.
Generating RTLIL representation for module `\top'.
Generating RTLIL representation for module `\mid'.
Generating RTLIL representation for module `\bot'.
%l: \bot
%m: \bot
Successfully finished Verilog frontend.
2. Executing CXXRTL backend.
2.1. Executing HIERARCHY pass (managing design hierarchy).
2.1.1. Finding top of design hierarchy..
root of   0 design levels: bot                 
root of   1 design levels: mid                 
root of   2 design levels: top                 
Automatically selected top as design top module.
2.1.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \mid
Used module:         \bot
2.1.3. Analyzing design hierarchy..
Top module:  \top
Used module:     \mid
Used module:         \bot
Removed 0 unused modules.
2.2. Executing FLATTEN pass (flatten design).
Deleting now unused module bot.
Deleting now unused module mid.
<suppressed ~2 debug messages>
2.3. Executing PROC pass (convert processes to netlists).
2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'.
Cleaned up 0 empty switches.
2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.
2.3.4. Executing PROC_INIT pass (extract init attributes).
2.3.5. Executing PROC_ARST pass (detect async resets in processes).
2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.
2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.
Cleaned up 0 empty switches.
2.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~11 debug messages>
End of script. Logfile hash: 1b689717a7, CPU: user 0.04s system 0.02s, MEM: 12.04 MB peak
Yosys 0.36+42 (git sha1 d87bd7ca3fc, gcc 13.2.1 -O2 -fexceptions -fstack-protector-strong -fasynchronous-unwind-tables -fno-omit-frame-pointer -fPIC -Os)
Time spent: 43% 1x opt_expr (0 sec), 13% 2x read_verilog (0 sec), ...
+ gcc -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
+ ./yosys-display_lm_cc
+ for log in yosys-display_lm.log yosys-display_lm_cc.log
+ grep '^%l: \\bot$' yosys-display_lm.log
%l: \bot
+ grep '^%m: \\bot$' yosys-display_lm.log
%m: \bot
+ for log in yosys-display_lm.log yosys-display_lm_cc.log
+ grep '^%l: \\bot$' yosys-display_lm_cc.log
%l: \bot
+ grep '^%m: \\bot$' yosys-display_lm_cc.log
%m: \bot
cd tests/cxxrtl && bash run-test.sh
+ run_subtest value
+ local subtest=value
+ shift
+ gcc -std=c++11 -O2 -o cxxrtl-test-value -I../../backends/cxxrtl/runtime test_value.cc -lstdc++
+ ./cxxrtl-test-value
+ run_subtest value_fuzz
+ local subtest=value_fuzz
+ shift
+ gcc -std=c++11 -O2 -o cxxrtl-test-value_fuzz -I../../backends/cxxrtl/runtime test_value_fuzz.cc -lstdc++
+ ./cxxrtl-test-value_fuzz
Randomized tests for value::shl:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::shr:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sshr:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::add:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sub:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::ctlz:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
  Passed "make test".
+ RPM_EC=0
++ jobs -p
+ exit 0
Processing files: yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64
Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.PrmbLl
+ umask 022
+ cd /builddir/build/BUILD
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ DOCDIR=/builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/doc/yosys
+ export LC_ALL=
+ LC_ALL=
+ export DOCDIR
+ /usr/bin/mkdir -p /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/doc/yosys
+ cp -pr /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/README.md /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/doc/yosys
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.IAnIIg
+ umask 022
+ cd /builddir/build/BUILD
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ LICENSEDIR=/builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/licenses/yosys
+ export LC_ALL=
+ LC_ALL=
+ export LICENSEDIR
+ /usr/bin/mkdir -p /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/licenses/yosys
+ cp -pr /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544/COPYING /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64/usr/share/licenses/yosys
+ RPM_EC=0
++ jobs -p
+ exit 0
Provides: yosys = 0.36-1.20231218gitd87bd7c.fc40 yosys(riscv-64) = 0.36-1.20231218gitd87bd7c.fc40
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Requires: /usr/bin/python3 ld-linux-riscv64-lp64d.so.1()(64bit) ld-linux-riscv64-lp64d.so.1(GLIBC_2.27)(64bit) libc.so.6()(64bit) libc.so.6(GLIBC_2.27)(64bit) libc.so.6(GLIBC_2.32)(64bit) libc.so.6(GLIBC_2.33)(64bit) libc.so.6(GLIBC_2.34)(64bit) libc.so.6(GLIBC_2.38)(64bit) libffi.so.8()(64bit) libffi.so.8(LIBFFI_BASE_8.0)(64bit) libgcc_s.so.1()(64bit) libgcc_s.so.1(GCC_3.0)(64bit) libm.so.6()(64bit) libm.so.6(GLIBC_2.27)(64bit) libreadline.so.8()(64bit) libstdc++.so.6()(64bit) libstdc++.so.6(CXXABI_1.3)(64bit) libstdc++.so.6(CXXABI_1.3.5)(64bit) libstdc++.so.6(GLIBCXX_3.4)(64bit) libstdc++.so.6(GLIBCXX_3.4.11)(64bit) libstdc++.so.6(GLIBCXX_3.4.14)(64bit) libstdc++.so.6(GLIBCXX_3.4.15)(64bit) libstdc++.so.6(GLIBCXX_3.4.18)(64bit) libstdc++.so.6(GLIBCXX_3.4.20)(64bit) libstdc++.so.6(GLIBCXX_3.4.21)(64bit) libstdc++.so.6(GLIBCXX_3.4.26)(64bit) libstdc++.so.6(GLIBCXX_3.4.29)(64bit) libstdc++.so.6(GLIBCXX_3.4.30)(64bit) libstdc++.so.6(GLIBCXX_3.4.32)(64bit) libstdc++.so.6(GLIBCXX_3.4.5)(64bit) libstdc++.so.6(GLIBCXX_3.4.9)(64bit) libtcl8.6.so()(64bit) libz.so.1()(64bit) libz.so.1(ZLIB_1.2.0)(64bit) rtld(GNU_HASH)
Processing files: yosys-doc-0.36-1.20231218gitd87bd7c.fc40.riscv64
Provides: yosys-doc = 0.36-1.20231218gitd87bd7c.fc40 yosys-doc(riscv-64) = 0.36-1.20231218gitd87bd7c.fc40
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Processing files: yosys-share-0.36-1.20231218gitd87bd7c.fc40.noarch
Provides: yosys-share = 0.36-1.20231218gitd87bd7c.fc40
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Processing files: yosys-devel-0.36-1.20231218gitd87bd7c.fc40.riscv64
Provides: yosys-devel = 0.36-1.20231218gitd87bd7c.fc40 yosys-devel(riscv-64) = 0.36-1.20231218gitd87bd7c.fc40
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Requires: /usr/bin/bash
Processing files: yosys-debugsource-0.36-1.20231218gitd87bd7c.fc40.riscv64
Provides: yosys-debugsource = 0.36-1.20231218gitd87bd7c.fc40 yosys-debugsource(riscv-64) = 0.36-1.20231218gitd87bd7c.fc40
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Processing files: yosys-debuginfo-0.36-1.20231218gitd87bd7c.fc40.riscv64
Provides: debuginfo(build-id) = 858d1be2511383655ae7fec6e93d6d3590b66236 debuginfo(build-id) = 8c35b13a3ce671acaafeafdd15d117b6ef13b360 yosys-debuginfo = 0.36-1.20231218gitd87bd7c.fc40 yosys-debuginfo(riscv-64) = 0.36-1.20231218gitd87bd7c.fc40
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Recommends: yosys-debugsource(riscv-64) = 0.36-1.20231218gitd87bd7c.fc40
Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64
Wrote: /builddir/build/RPMS/yosys-share-0.36-1.20231218gitd87bd7c.fc40.noarch.rpm
Wrote: /builddir/build/RPMS/yosys-devel-0.36-1.20231218gitd87bd7c.fc40.riscv64.rpm
Wrote: /builddir/build/RPMS/yosys-doc-0.36-1.20231218gitd87bd7c.fc40.riscv64.rpm
Wrote: /builddir/build/RPMS/yosys-debugsource-0.36-1.20231218gitd87bd7c.fc40.riscv64.rpm
Wrote: /builddir/build/RPMS/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64.rpm
Wrote: /builddir/build/RPMS/yosys-debuginfo-0.36-1.20231218gitd87bd7c.fc40.riscv64.rpm
Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.ZxIP63
+ umask 022
+ cd /builddir/build/BUILD
+ cd yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544
+ /usr/bin/rm -rf /builddir/build/BUILDROOT/yosys-0.36-1.20231218gitd87bd7c.fc40.riscv64
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.imwS0z
+ umask 022
+ cd /builddir/build/BUILD
+ rm -rf /builddir/build/BUILD/yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544-SPECPARTS
+ rm -rf yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544 yosys-d87bd7ca3fcd898cbc310904a55150e9bce7b544.gemspec
+ RPM_EC=0
++ jobs -p
+ exit 0
Child return code was: 0